CN214848641U - Super junction MOSFET - Google Patents
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- CN214848641U CN214848641U CN202121129551.XU CN202121129551U CN214848641U CN 214848641 U CN214848641 U CN 214848641U CN 202121129551 U CN202121129551 U CN 202121129551U CN 214848641 U CN214848641 U CN 214848641U
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Abstract
The application discloses surpass knot MOSFET, it surpasses knot MOSFET based on tradition, through the below at P type post corresponds sets up N type buffer, has the interval between N type buffer and the P type post, and the N type buffer that so sets up can increase surpass the inside body diode's that exists of knot MOSFET negative pole district reverse recovery period carrier concentration for required time t when reverse recovery current reaches 90% of maximum reverse recovery currentbIncreasing the time t required for the reverse recovery current to reach 10% of the maximum reverse recovery currentaThe softness factor S is increased under the constant condition, and S is equal totb/ta. In addition, the N-type buffer region is only arranged below the body diode, and the increase of the on-resistance caused by the increase of the ion concentration of the doping of the N-drift region can be reduced. Thus, the super junction MOSFET increases the soft recovery characteristics of the device in the reverse recovery phase, which can be referred to as a soft recovery super junction MOSFET.
Description
Technical Field
The application relates to the technical field of semiconductor power devices, in particular to a super junction MOSFET.
Background
The super-junction charge balance theory is provided, and the compromise relation between breakdown voltage and on-resistance is improved. Referring to fig. 1, compared to a conventional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), the super-junction MOSFET introduces N-type columns and P-type columns alternately arranged in an N-drift region, so that a lateral electric Field can be formed between the P-type columns and the N-type columns during a forward conduction phase, i.e., so-called charge balance; however, the super-junction MOSFET is still a MOSFET in nature, a parasitic body diode (body diode for short) still exists inside the super-junction MOSFET, the source of the super-junction MOSFET is the anode of the body diode, and the drain of the super-junction MOSFET is the cathode of the body diode.
In the forward conduction stage of the super-junction MOSFET, free carriers exist in an N-drift region in a body diode, in order to realize the process from forward bias to reverse bias, the free carriers in the N-drift region are extracted by an external voltage to form a depletion region capable of bearing reverse voltage, and the process from an on state to an off state of the body diode becomes reverse recovery; the waveform of the current and voltage in the reverse recovery process with time is shown in FIG. 2, wherein I in the waveformFIndicates a forward conduction current, VFDenotes the forward conduction voltage, VRDenotes the reverse recovery voltage, IrrmRepresenting the maximum reverse recovery current, di/dt representing the rate of rise of the current, trrFor the total time of the reverse recovery process, trrThe shorter the reverse recovery, the faster the reverse recovery, which can be referred to as fast recovery, t in the waveforma、tbRespectively, the reverse recovery current reaches 90 percent IrrmCompared with 10 percentIrrmTime required trr＝ta+tb(ii) a Introducing a softness factor (S), wherein T isb/taThe larger the value of S, the softer the anti-positive recovery characteristic, which may be referred to as soft recovery. The reverse recovery characteristic of the existing super-junction MOSFET cannot meet the requirements of partial application fields on the super-junction MOSFET.
Therefore, a super junction MOSFET having good reverse recovery characteristics is desired to be developed.
SUMMERY OF THE UTILITY MODEL
In view of this, the present application provides a super-junction MOSFET to improve the problem of poor reverse recovery characteristics of the existing super-junction MOSFET.
The application provides a super junction MOSFET, on the cross section of super junction MOSFET, super junction MOSFET includes: an N + substrate having first and second oppositely disposed major surfaces; a drain electrode provided on the first main surface; an N-drift region disposed on the second major surface, comprising: the N-type buffer areas are arranged on the second main surface at intervals and are distributed in an array along the horizontal direction; the P-type columns are correspondingly arranged on the N-type buffer area and are spaced from the N-type buffer area, the N-drift area between the P-type columns is defined as the N-type columns, and the P-type columns and the N-type columns are alternately arranged along the horizontal direction to form a super-junction structure; a plurality of P-type body regions (P bodies) distributed in an array along the horizontal direction, wherein the P-type body regions are correspondingly arranged on the P-type columns; a plurality of N-type source regions (N source) are arranged in each P-type body region at intervals and distributed in an array mode along the horizontal direction, and the upper surfaces of the N-drift regions are respectively flush with the upper surfaces of the N-type source regions and the upper surfaces of the P-type body regions; the grid electrodes are arranged on the N-drift region at intervals and distributed in an array mode along the horizontal direction, and the lower surface of each grid electrode is respectively contacted with the upper surfaces of parts of two adjacent P-type body regions, the upper surface of the N-drift region positioned between the two adjacent P-type body regions and the upper surfaces of parts of two adjacent N-type source regions positioned in different P-type body regions; the grid oxide layer covers the grid and is in contact with the N-type source region; and the source electrode is arranged on the grid oxide layer and the N-drift region, covers the grid oxide layer and fills the region between the grid oxide layers, and the region between the grid oxide layers is respectively contacted with part of the P-type body region and part of the N-type source region.
In some embodiments, a space is provided between an outer side of the N-type source region near a left side of the P-type body region and a left side of the P-type body region, and a space is provided between an outer side of the N-type source region near a right side of the P-type body region and a right side of the P-type body region.
In some embodiments, the width of the N-type buffer region is greater than the width of the P-type pillar.
In some embodiments, the width of the P-type body region is greater than the width of the P-type pillar.
In some embodiments, the width of the P-type body region is greater than the width of the N-type buffer region.
In some embodiments, more than 3P + regions are spaced in each P-type body region, the upper surfaces of the P + regions are respectively flush with the upper surface of the N-drift region, the upper surface of the N-type source region and the upper surface of the P-type body region, and the P + regions are respectively in contact with the P-type body region and the N-type source region.
In some embodiments, the 3 or more P + regions include a first P + region, one or more second P + regions, and a third P + region, the first P + region includes a first convex portion and a first non-convex portion, an outer side of the first convex portion of the first P + region is flush with an outer side of the first non-convex portion to form an outer side of the first P + region, the outer side of the first P + region is close to and spaced apart from a left side of the P-type body region, an inner side of the first convex portion of the first P + region and an upper surface of the first non-convex portion are in contact with the N-type source region, and the upper surface of the first convex portion of the first P + region is in contact with one gate; the second P + region comprises a second convex part and a second non-convex part, the second convex part of the second P + region is positioned between two adjacent N-type source regions, one side of the second convex part is in contact with one N-type source region, the other side of the second convex part is in contact with the other N-type source region, and the upper surfaces of the second non-convex parts are in contact with the two adjacent N-type source regions respectively; the third P + region comprises a third protruding part and a third non-protruding part, the third P + region is opposite to the first P + region, the outer side of the third protruding part of the third P + region is flush with the outer side of the third non-protruding part to form the outer side of the third P + region, the outer side of the third P + region is close to the right side of the P-type body region and is spaced from the right side of the P-type body region, the inner side of the third protruding part of the third P + region and the upper surface of the third non-protruding part are in contact with the N-type source region, and the upper surface of the third protruding part of the third P + region is in contact with the other gate.
In some embodiments, the gate is in full contact with an upper surface of the first raised portion of the first P + region in one P-type body region and an upper surface of the third raised portion of the third P + region in another P-type body region, and the source is in full contact with an upper surface of the second raised portion of the second P + region.
In some embodiments, 2N-type source regions are spaced in each P-type body region, and 3P + regions are spaced in each P-type body region.
In some embodiments, the depth of the P-type body region is greater than the depth of the P + region, and the depth of the P + region is greater than the depth of the N-type source region.
According to the super-junction MOSFET, the N-type buffer area is correspondingly arranged below the P-type column, the N-type buffer area and the P-type column are spaced, and the N-type buffer area can increase the carrier concentration during the reverse recovery of the cathode area of a body diode (the source electrode and the drain electrode of the super-junction MOSFET are respectively used as the anode and the cathode) in the super-junction MOSFET, so that tbIncrease, taThus making S large without change. In addition, the N-type buffer region is only arranged below the body diode, and the increase of the on-resistance caused by the increase of the ion concentration of the doping of the N-drift region can be reduced. Therefore, the above-described super junction MOSFET of the present application increases the soft recovery characteristics of the super junction MOSFET in the reverse recovery phase, and it may be referred to as a soft recovery super junction MOSFET.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure diagram of a super junction MOSFET in the prior art;
fig. 2 is a waveform diagram of current and voltage variations with time during the body diode reverse recovery process in the super junction MOSFET shown in fig. 1;
fig. 3 is a schematic cross-sectional structure diagram of a super junction MOSFET of an embodiment of the present application;
fig. 4 is a schematic cross-sectional structure diagram of a super junction MOSFET according to another embodiment of the present application.
Each reference numeral represents: 1. a drain electrode; 2. an N + substrate; 3. an N-drift region; 4. a body diode; 5. a gate electrode; 6. a gate oxide layer; 7. a source electrode; 21. a first major surface; 22. a second major surface; 31. an N-type buffer region; 32. a P-type column; 33. an N-type column; 34. a P-type body region; 35. an N-type source region; 36. a P + region; 361. a first P + region; 362. a second P + region; 363. a third P + region; 3611. a first convex portion; 3612. a first non-convex portion; 3621. a second convex portion; 3622. a second non-convex portion; 3631. a third convex portion; 3632. a third non-convex portion.
Detailed Description
The technical solutions in the embodiments of the present application are described below with reference to the accompanying drawings, and the embodiments and technical features thereof described below may be combined with each other without conflict.
Referring to fig. 3, the present application provides an embodiment of a super junction MOSFET, which includes, in a cross section thereof: an N + substrate 2 having a first main surface 21 and a second main surface 22 disposed oppositely; a drain electrode 1 provided on the first main surface 21; an N-drift region 3, provided on the second main surface 22, comprising: a plurality of N-type buffer regions 31 spaced apart from each other on the second main surface 22 and arranged in an array in the horizontal direction; a plurality of P-type columns 32 distributed in an array along the horizontal direction, wherein the P-type columns 32 are correspondingly arranged on the N-type buffer region 31 and spaced from the N-type buffer region 31, the N-drift region 3 between the P-type columns 32 is defined as an N-type column 33, and the P-type columns 32 and the N-type column 33 are alternately arranged along the horizontal direction to form a super junction structure; a plurality of P-type body regions 34 distributed in an array along the horizontal direction, wherein the P-type body regions 34 are correspondingly arranged on the P-type columns 32; a plurality of N-type source regions 35 (e.g., 2, 3, 5, etc., 2 shown in the figure) are spaced in each P-type body region 34 and distributed in an array along the horizontal direction, and the upper surfaces of the N-drift regions 3 are flush with the upper surfaces of the N-type source regions 35 and the P-type body regions 34, respectively; a plurality of gates 5, which are arranged on the N-drift region 3 at intervals and distributed in an array along the horizontal direction, wherein the lower surface of each gate 5 is in contact with the upper surfaces of parts of two adjacent P-type body regions 34, the upper surface of the N-drift region 3 between the two adjacent P-type body regions 34 and the upper surfaces of parts of two adjacent N-type source regions 35 of different P-type body regions 34; a gate oxide layer 6 covering the gate 5 and contacting the N-type source region 35; and the source electrode 7 is arranged on the gate oxide layer 6 and the N-drift region 3, covers the gate oxide layer 6 and fills the region between the gate oxide layers 6, and the region between the gate oxide layers 6 is respectively contacted with a part of the P-type body region 34 and a part of the N-type source region 35. Specifically, a portion inside the super junction MOSFET shown as a dotted area in fig. 3 constitutes the body diode 4, and the body diode 4 has the source 7 of the super junction MOSFET as an anode and the drain 1 of the super junction MOSFET as a cathode.
In the super-junction MOSFET of the embodiment, the N-type buffer area is correspondingly arranged below the P-type column, and the N-type buffer area and the P-type column are spaced, so that the concentration of carriers in the cathode region of a body diode existing in the super-junction MOSFET during reverse recovery can be increased by the arranged N-type buffer area, and t is enabled to be tbIncrease, taThus making S large without change. In addition, the N-type buffer region is only arranged below the body diode, and the increase of the on-resistance caused by the increase of the ion concentration of the doping of the N-drift region can be reduced. Therefore, the super junction MOSFET of the present embodiment increases the soft recovery characteristics of the super junction MOSFET in the reverse recovery phase, and it may be referred to as a soft recovery super junction MOSFET.
In some embodiments, the N + substrate 2 may be, but is not limited to, a silicon-based semiconductor substrate, and the N + substrate 2 may be, for example, a silicon wafer.
In some embodiments, the Drain (Drain, D)1 may be a metal electrode or a non-metal electrode; and/or, the Source electrode (Source, S)7 may be, but is not limited to, a metal electrode, and for example, the Source electrode 7 may be an aluminum electrode, a copper electrode, an aluminum-copper alloy electrode, or the like; and/or, the gate 5 may be, but is not limited to, a polysilicon (poly-Si) gate.
In some embodiments, the gate oxide layer 6 may be, but is not limited to, silicon dioxide (SiO)2) A layer; and/or, the N-drift region 3 may be, but is not limited to, a phosphorus doped N-type semiconductor material layer; and/or, the N-type buffer region 31 may be, but is not limited to, a phosphorus-doped N-type semiconductor material layer implanted with arsenic (As) ions and/or phosphorus (P) ions.
In some embodiments, the doping concentration of the N-type buffer region 31 is greater than the doping concentration of the N-drift region 3. In some embodiments, there is a spacing between the outside of N-type source region 35 near the left side of P-type body region 34 and the left side of P-type body region 34, and a spacing between the outside of N-type source region 35 near the right side of P-type body region 34 and the right side of P-type body region 34.
In some embodiments, the width of the N-type buffer 31 is greater than the width of the P-type pillar 32.
In some embodiments, the width of the P-type body regions 34 is greater than the width of the P-type pillars 32.
In some embodiments, the width of the P-type body region 34 is greater than the width of the N-type buffer region 31.
Referring to fig. 4, in some embodiments, more than 3P + regions 36 (e.g., 3, 4, 5, etc., 3 shown) are spaced apart from each other in each P-type body region 34, an upper surface of the P + regions 36 is flush with an upper surface of the N-drift region 3, an upper surface of the N-type source region 35, and an upper surface of the P-type body region 34, and the P + regions 36 are in contact with the P-type body region 34 and the N-type source region 35, respectively. By arranging more than 3P + regions in the P-type body region, the injection efficiency of the anode of the body diode existing in the super-junction MOSFET can be reduced, so that the maximum reverse recovery current is reduced, the total time trr of the reverse recovery process is reduced, and the reverse recovery speed is improved. In addition, the presence of the P + region helps to improve device avalanche capability (EAS). Therefore, the Super-Junction MOSFET of the present embodiment simultaneously increases the Soft recovery and Fast recovery characteristics of the Super-Junction MOSFET in the reverse recovery phase, and it may be referred to as a Fast & Soft recovery Super Junction (FSSJ) MOSFET.
In some embodiments, the P-type pillars 32 may have a cylindrical structure or a prismatic (e.g., quadrangular) structure, and the P-type pillars 32 may be a P-type semiconductor material layer; and/or the N-type source region 35 may be a P-type semiconductor material layer implanted with arsenic ions.
In some embodiments, the P + region 36 may be, but is not limited to, a layer of P-type semiconductor material implanted with boron ions.
In some embodiments, the doping concentration of the P + regions 36 is greater than the doping concentration of the P-type body regions 34.
In some embodiments, the 3 or more P + regions 36 include a first P + region 361, one or more second P + regions 362 and a third P + region 363, the first P + region 361 includes a first convex portion 3611 and a first non-convex portion 3612, an outer side of the first convex portion 3611 of the first P + region 361 is flush with an outer side of the first non-convex portion 3612 to form an outer side of the first P + region 361, the outer side of the first P + region 361 is close to a left side of the P-type body region 34 and spaced apart from the left side of the P-type body region 34, the inner side of the first convex portion 3611 of the first P + region 361 and an upper surface of the first non-convex portion 3612 are in contact with the N-type source region 35, and the upper surface of the first convex portion 3611 of the first P + region 361 is in contact with a gate 5;
the second P + region 362 includes a second convex portion 3621 and a second non-convex portion 3622, the second convex portion 3621 of the second P + region 362 is located between two adjacent N-type source regions 35, one side of the second convex portion 3621 contacts one N-type source region 35, the other side contacts the other N-type source region 35, and the upper surface of the second non-convex portion 3622 contacts the two adjacent N-type source regions 35 respectively;
the third P + region 363 includes a third protruding portion 3631 and a third non-protruding portion 3632, the third P + region 363 is opposite to the first P + region 361, an outer side of the third protruding portion 3631 of the third P + region 363 is flush with an outer side of the third non-protruding portion 3632 to form an outer side of the third P + region 363, the outer side of the third P + region 363 is close to the right side of the P-type body region 34 and spaced from the right side of the P-type body region 34, an inner side of the third protruding portion 3631 of the third P + region 363 and an upper surface of the third non-protruding portion 3632 are in contact with the N-type source region 35, and an upper surface of the third protruding portion 3631 of the third P + region 363 is in contact with another gate 5.
In some embodiments, the depth of the first P + region 361, the second P + region 362 and the third P + region 363 is the same.
In some embodiments, the gate electrode 5 is in full contact with an upper surface of the first protrusion portion 3611 of the first P + region 361 in one P-type body region 34 and an upper surface of the third protrusion portion 3631 of the third P + region 363 in the other P-type body region 34, and the source electrode 7 is in full contact with an upper surface of the second protrusion portion 3621 of the second P + region 362.
In some embodiments, 2N-type source regions 35 are spaced apart in each P-type body region 34, and 3P + regions 36 are spaced apart in each P-type body region 34.
In some embodiments, the depth of the P-type body regions 34 is greater than the depth of the P + regions 36, and the depth of the P + regions 36 is greater than the depth of the N-type source regions 35.
In some embodiments, the sum of the depth of the P-type body regions 34 and the depth of the P-type pillars 32 is 5-50 micrometers (μm).
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, in the description of the present application, it is to be understood that the terms "lateral," "width," "depth," "upper," "lower," "left," "right," "horizontal," "inner," "outer," and the like refer to orientations or positional relationships based on those shown in the drawings, which are merely for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application. In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second", "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Claims (10)
1. A super-junction MOSFET, comprising, in a cross section of the super-junction MOSFET:
an N + substrate having first and second oppositely disposed major surfaces;
a drain electrode provided on the first main surface;
an N-drift region disposed on the second major surface, comprising: the N-type buffer areas are arranged on the second main surface at intervals and are distributed in an array along the horizontal direction; the P-type columns are correspondingly arranged on the N-type buffer area and are spaced from the N-type buffer area, the N-drift area between the P-type columns is defined as the N-type columns, and the P-type columns and the N-type columns are alternately arranged along the horizontal direction to form a super-junction structure; the plurality of P-shaped body regions are distributed in an array along the horizontal direction, and the P-shaped body regions are correspondingly arranged on the P-shaped columns; a plurality of N-type source regions are arranged in each P-type body region at intervals and distributed in an array mode along the horizontal direction, and the upper surfaces of the N-drift regions are respectively flush with the upper surfaces of the N-type source regions and the upper surfaces of the P-type body regions;
the grid electrodes are arranged on the N-drift region at intervals and distributed in an array mode along the horizontal direction, and the lower surface of each grid electrode is respectively contacted with the upper surfaces of parts of two adjacent P-type body regions, the upper surface of the N-drift region positioned between the two adjacent P-type body regions and the upper surfaces of parts of two adjacent N-type source regions positioned in different P-type body regions;
the grid oxide layer covers the grid and is in contact with the N-type source region;
and the source electrode is arranged on the grid oxide layer and the N-drift region, covers the grid oxide layer and fills the region between the grid oxide layers, and the region between the grid oxide layers is respectively contacted with part of the P-type body region and part of the N-type source region.
2. The super-junction MOSFET of claim 1, wherein an outer side of the N-type source region near the left side of the P-type body region is spaced apart from the left side of the P-type body region, and an outer side of the N-type source region near the right side of the P-type body region is spaced apart from the right side of the P-type body region.
3. The super-junction MOSFET of claim 1, wherein the width of the N-type buffer region is greater than the width of the P-type pillar.
4. The super-junction MOSFET of claim 1 wherein the width of the P-type body regions is greater than the width of the P-type pillars.
5. The super-junction MOSFET of claim 1, wherein the width of the P-type body region is greater than the width of the N-type buffer region.
6. The super-junction MOSFET of claim 1, wherein more than 3P + regions are spaced within each P-type body region, the upper surfaces of the P + regions are flush with the upper surfaces of the N-drift region, the N-type source region and the P-type body region, respectively, and the P + regions are in contact with the P-type body region and the N-type source region, respectively.
7. The super-junction MOSFET of claim 6, wherein the 3 or more P + regions include a first P + region, one or more second P + regions and a third P + region, the first P + region includes a first convex portion and a first non-convex portion, the outer side of the first convex portion of the first P + region is flush with the outer side of the first non-convex portion to form the outer side of the first P + region, the outer side of the first P + region is close to and spaced apart from the left side of the P-type body region, the inner side of the first convex portion of the first P + region and the upper surface of the first non-convex portion are in contact with the N-type source region, and the upper surface of the first convex portion of the first P + region is in contact with a gate;
the second P + region comprises a second convex part and a second non-convex part, the second convex part of the second P + region is positioned between two adjacent N-type source regions, one side of the second convex part is in contact with one N-type source region, the other side of the second convex part is in contact with the other N-type source region, and the upper surfaces of the second non-convex parts are in contact with the two adjacent N-type source regions respectively;
the third P + region comprises a third protruding part and a third non-protruding part, the third P + region is opposite to the first P + region, the outer side of the third protruding part of the third P + region is flush with the outer side of the third non-protruding part to form the outer side of the third P + region, the outer side of the third P + region is close to the right side of the P-type body region and is spaced from the right side of the P-type body region, the inner side of the third protruding part of the third P + region and the upper surface of the third non-protruding part are in contact with the N-type source region, and the upper surface of the third protruding part of the third P + region is in contact with the other gate.
8. The super-junction MOSFET of claim 7 wherein the gate is in full contact with an upper surface of the first raised portion of the first P + region in one P-type body region and an upper surface of the third raised portion of the third P + region in the other P-type body region, and the source is in full contact with an upper surface of the second raised portion of the second P + region.
9. The super-junction MOSFET according to claim 6, wherein 2N-type source regions are spaced in each P-type body region, and 3P + regions are spaced in each P-type body region.
10. The super-junction MOSFET of claim 6, wherein the depth of the P-type body region is greater than the depth of the P + region, which is greater than the depth of the N-type source region.
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| WO2023098626A1 (en) * | 2021-12-03 | 2023-06-08 | 华润微电子（重庆）有限公司 | Super-junction mosfet device |
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| WO2023098626A1 (en) * | 2021-12-03 | 2023-06-08 | 华润微电子（重庆）有限公司 | Super-junction mosfet device |
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