CN208352295U - A kind of MOS control thyristor chip - Google Patents

Abstract

A kind of MOS control thyristor chip, first electrode including being formed in chip-side, it is formed in the second electrode lay that the chip other side includes second electrode and coordination electrode, form single cell structure between the first electrode and the second electrode, the single cell structure includes multiple first kind unit cells being connected in parallel and multiple Second Type unit cells being connected in parallel, first kind unit cell is to open unit cell, and Second Type unit cell is shutdown unit cell；And terminal structure, it is located at single cell structure periphery.

Description

A kind of MOS control thyristor chip

Technical field

The utility model relates to technical field of semiconductors.Thyristor chip is controlled more particularly, to a kind of MOS.

Background technique

In recent years, due to the progress of semiconductor technology and the market expansion etc., power electronics field has very big Development.Currently, widely used one kind power electronic devices is turned on and off by the control of control signal, this kind includes several The different type of device of kind, such as IGBT and GTO.But IGBT is confined to intermediate frequency field, although GTO is in the application of 2000V or more Field is needed very strong protective current and gate drive circuit, is connected in parallel the defects of difficult and frequency is limited due to IGBT. Therefore, have many advantages, such as high input impedance, be more easily controlled, MOS that blocking voltage is high control thyristor comes into being.

But current MOS controls thyristor, and when multiple thyristors are used in conjunction with, existing thoroughly quickly to open and close Disconnected problem, the more such problems of thyristor are just more obvious, if the resistance to electric current for influencing device is special without all open-minded Property, in addition, can then enable device there is the wind of damage once there is the high current of remaining due to not all off when shutdown Danger, but some products open pipe and shutdown pipe, such shape to solve the problems, such as to be each equipped in each thyristor above At MOS control thyristor chip complex process, also improve production cost.

Accordingly, it is desirable to provide a kind of simple process and can provide and excellent open shutdown consistency and guarantee quick The MOS control thyristor chip thoroughly turned off.

Utility model content

The purpose of this utility model is to provide a kind of simple process, with the good MOS control for opening shutdown consistency Thyristor chip processed.

In order to achieve the above objectives, the utility model adopts the following technical solutions:

A kind of thyristor chip of MOS control, which is characterized in that the first electrode including being formed in chip-side is formed In the second electrode lay that the chip other side includes second electrode and coordination electrode, formed between the first electrode and the second electrode Single cell structure, the single cell structure include multiple first kind unit cells being connected in parallel and multiple Second Type lists being connected in parallel Born of the same parents, first kind unit cell are to open unit cell, and Second Type unit cell is shutdown unit cell；And terminal structure, it is located at single cell structure Periphery.

Preferably, multiple unit cells of opening surround multiple shutdown unit cells.

Preferably, multiple unit cells of opening are arranged in multiple shutdown unit cell periphery individual pens.

Preferably, multiple quantity for opening unit cell are less than the quantity of multiple shutdown unit cells.

Preferably, the first unit cell includes being sequentially formed in the first conductivity type substrate: the buffering of the second conduction type； The epitaxial layer of second conduction type；Form the first well region of the first conduction type in the epitaxial layer；It is formed in the first well region The second conduction type the second well region；The control electrode insulating layer being formed on the first well region and the second well region, it is partially exposed Second well region；The control electrode being formed on control electrode insulating layer；The first electrode being formed on the second exposed well region；And shape At the second electrode on the substrate other side.

Preferably, the second unit cell includes being sequentially formed in the first conductivity type substrate: the buffering of the second conduction type Layer；The epitaxial layer of second conduction type；Form the first well region of the first conduction type in the epitaxial layer；It is formed in the first well region In the second conduction type the second well region；The third well region being formed in the second well region, between including in each second well region Every two third well regions of arrangement；The control electrode insulating layer being formed on the first well region, the second well region and third well region, partly The second well region of exposure and third well region；The control electrode being formed on control electrode insulating layer；It is formed in exposed the second well region and First electrode on three well regions；And

The second electrode being formed on the substrate other side.

Preferably, the first conduction type is p-type, and the second conduction type is N-type.

Preferably, the first conduction type is N-type, and the second conduction type is p-type.

Preferably, terminal structure includes multiple field plates and multiple field limiting rings, and multiple field limiting rings are spaced apart, multiple field plate cloth It sets above multiple field limiting rings and partially covers the corresponding field limiting ring in multiple field limiting rings.

The beneficial effects of the utility model are as follows:

The consistency that technical solution described in the utility model is capable of providing a kind of simple process, turns on and off is good, tool There is the high voltage MOS control thyristor chip of dual shutdown mechanism.

Detailed description of the invention

Specific embodiment of the present utility model is described in further detail with reference to the accompanying drawing；

Fig. 1 is the schematic top plan view for showing the integral layout that thyristor chip is controlled according to the MOS of the disclosure；

Fig. 2 is the first unit cell schematically shown among the single cell structure for controlling thyristor chip according to the MOS of the disclosure With the amplification assumption diagram of the second unit cell exemplary layout relationship；

Fig. 3 is the cross-sectional view being exaggerated for being located at line AA above section along the part that line AA shown in Fig. 2 is intercepted；

Fig. 4 is that amplification shows line BB in section shown in Fig. 3 with the view of the exemplary structure of left half；

Fig. 5 is the circuit diagram according to first unit cell of an embodiment of the present disclosure；

Fig. 6 is the circuit diagram according to second unit cell of an embodiment of the present disclosure；And

Fig. 7 to Figure 13 is the view for showing the chip structure of the disclosure formed according to exemplary method steps.

Specific embodiment

In order to illustrate more clearly of the utility model, the utility model is done into one below with reference to preferred embodiments and drawings The explanation of step.Similar component is indicated in attached drawing with identical appended drawing reference.It will be appreciated by those skilled in the art that below Specifically described content is illustrative and be not restrictive, and should not be limited the protection scope of the present invention.

In the accompanying drawings, in order to be explicitly described, the thickness in each layer and region etc. is enlargedly shown.Moreover, in order to just In explanation, expands show the thickness of part layer and region in the accompanying drawings.It will be understood by those skilled in the art that this is only signal Property, it is not intended to limit the utility model.

In the description unless otherwise clearly opposite record, " having ", " containing ", "include", "comprise" etc. are expressed Be it is open, they indicate described structure, the presence of element or feature, but additional element or feature is not precluded.

It should be understood that ordinal number first, second described in the specification etc. is intended merely to the clear of description, rather than in order to limit The sequence of component, assembly unit processed or component etc., that is, be described as first element, component and component and second element, component or component It can also be expressed as second element, component and component and first element, component or component.

Fig. 1 is the schematic top plan view that the integral layout of thyristor chip 10 is controlled according to the MOS of the disclosure.As schemed Show, the MOS control thyristor chip 10 of the disclosure includes the first electrode for being formed in chip-side, is formed in chip other side packet The second electrode lay for including second electrode and coordination electrode forms single cell structure 110 between the first electrode and the second electrode, Single cell structure periphery further includes terminal structure 130.In addition, MOS control thyristor chip 10 further includes coordination electrode G, negative electrode K With positive electrode A.Due to the layout in order to show single cell structure 110 and terminal structure 130, control has only been indicated in Fig. 1 The region of electrode G processed.In practical structures, if MOS control thyristor chip 10 is that NMOS controls thyristor chip (N- MCT), then first electrode is positive electrode A, and second electrode is negative electrode K；If MOS controls thyristor chip 10 as PMOS control Thyristor chip (P-MCT), then first electrode is negative electrode K, and second electrode is positive electrode A.

The structural principle of the MOS control thyristor chip 10 of the disclosure is described by taking N-MCT as an example below with reference to Fig. 2 to Fig. 6 And its controlling mechanism.

The specific structure of single cell structure 110 is to schematically show to control thyristor according to the MOS of the disclosure referring to Fig. 2, Fig. 2 In chip 10 among single cell structure 110 the first unit cell 111 (i) (i ∈ 1,2 ... N, N are equal with the first unit cell sum Positive integer) and the second unit cell 113 (j) (j ∈ 1,2 ... the positive integer that M, M are and the second unit cell sum is equal) exemplary layout The amplification assumption diagram of relationship.The composition and exemplary arrangement mode of single cell structure 110 are shown in further detail in figure.

As shown in Fig. 2, single cell structure 110 includes multiple first lists for being arranged successively into a circle in the exemplary layout Born of the same parents 111 (i) (i ∈ 1,2 ... the positive integer that N, N are and the first unit cell sum is equal) and be arranged successively and be arranged in by multiple the One unit cell 111 (i) (i ∈ 1,2 ... the positive integer that N, N are and the first unit cell sum is equal) in the region that surrounds multiple the Two unit cells 113 (j) (j ∈ 1,2 ... the positive integer that M, M are and the second unit cell sum is equal), blank parts omit portion in figure Point the second unit cell 113 (j) (j ∈ 1,2 ... the positive integer that M, M are and the second unit cell sum is equal).In single cell structure 110 All unit cells share identical coordination electrode G, negative electrode K and positive electrode A, multiple first unit cells 111 (i) (i ∈ 1,2 ... N, N be and the equal positive integer of the first unit cell sum) be connected in parallel to each other, the second unit cell 113 (j) (j ∈ 1,2 ... M, M are and second The equal positive integer of unit cell sum) be connected in parallel to each other, and the first unit cell 111 (i) (i ∈ 1,2 ... N, N are and the first unit cell sum Equal positive integer) and the second unit cell 113 (j) (j ∈ 1,2 ... the positive integer that M, M are and the second unit cell sum is equal) each other It is in parallel.

It should be understood that in figure merely to schematically show the first unit cell 111 (i) (i ∈ 1,2 ... N, N are and first The equal positive integer of unit cell sum) with the second unit cell 113 (j) (j ∈ 1,2 ... M, M be it is equal with the second unit cell sum just Integer) exemplary layout relationship, be not for purposes of limitation, the first unit cell 111 (i) of other numbers (i ∈ 1, 2 ... N, N be and the equal positive integer of the first unit cell sum) with the second unit cell 113 (j) (j ∈ 1,2 ... M, M are and second The equal positive integer of unit cell sum) it is also possible, the unit cell positioned at outside can also be halfway around the unit cell for being located inside.

Preferably, in the embodiment shown in Figure 2, positioned at periphery the first unit cell 111 (i) (i ∈ 1,2 ... N, N are With the equal positive integer of the first unit cell sum) be responsible for opening open unit cell, open the second unit cell 113 (j) of unit cell encirclement (j ∈ 1,2 ... the positive integer that M, M are and the second unit cell sum is equal) be responsible for the shutdown unit cell of shutdown, and as shown in Fig. 2, The quantity for opening unit cell is less than the quantity of shutdown unit cell.This is because in the present embodiment, once the completion of chip 10 is opened and will be flowed Through super-high-current, complete switching off for high current is difficult, in order to guarantee good turn-off performance, the quantity of unit cell will be turned off It is set greater than the quantity for opening unit cell.It will be understood by those skilled in the art that embodiment of the disclosure is not limited to this, some In the case of, the quantitative relation of the two can also change.

In addition, the parallel connectivity of single cell structure 110 can guarantee the energy of resistance to electric current of MOS control thyristor chip 10 Power, it should be appreciated that when needing to carry high current, it is only necessary to the quantity of adjustment the first unit cell and the second unit cell as needed.

Fig. 3 is the cross-sectional view being exaggerated for being located at line AA above section along the part that line AA shown in Fig. 2 is intercepted, purport In the structural relation for further showing above-mentioned component by Fig. 3.As shown in figure 3,111 (1) and 113 (m) indicate cross-sectional views in First unit cell 111 (1) and adjacent the second unit cell of the first unit cell 111 (2), wherein m indicate from the cross-sectional view it can be seen that The total number of second unit cell.

Fig. 4 is that amplification shows line BB in section shown in Fig. 3 with the view of the exemplary structure of left half, passes through edge The interception of line BB only shows section, the first unit cell 111 (1) of the terminal structure 130 positioned at cross-sectional view left-half in Fig. 4 With the second unit cell 113 (1).As shown in figure 4, the first unit cell 111 (1), the second unit cell 113 (1) are with terminal structure 130 with identical Substrate 200, buffer layer 205 and epitaxial layer 210.In addition, the first unit cell 111 (1) and the second unit cell 113 (1) are having the same First well region 220 and anode 255.

Specifically, the first unit cell 111 (1) includes: the buffer layer of the substrate 200 of the first conduction type, the second conduction type 205, the second well region of the epitaxial layer 210 of the second conduction type, the first well region 220 of the first conduction type, the second conduction type 225-1, the first control electrode 250-1 and the first cathode 245-1.Second unit cell 113 (1) includes: the substrate of the first conduction type 200, the first well region of the buffer layer 205 of the second conduction type, the epitaxial layer 210 of the second conduction type, the first conduction type 220, the second well region 225-2 of the second conduction type, the third well region 230 of the first conduction type, the second control electrode 250-2 and Two cathode 245-2.

It is worth noting that, the first control electrode 250-1 and the second control electrode 250-2 are electrically connected, the first yin Pole 245-1 and the second cathode 245-2 be also be electrically connected, therefore in order in being subsequently formed step convenient for description and just In understanding, in addition the first control electrode 250-1 and the second control electrode 250-2 are marked into total label 250, therefore ought below not When distinguishing especially referred to as control electrode 250 when, the first cathode 245-1 and the second cathode 245-2 are marked into total label 245, when Referred to as cathode 245 when not distinguishing especially hereinafter.

It in addition, further include control electrode insulating layer 235 between the surface of chip 10 and control electrode 250, specifically such as Fig. 4 institute Show.For the first unit cell 111 (1), partially exposed second well region of the first unit cell control electrode insulating layer 235, therefore it is formed in control Control electrode 250 on pole insulating layer 235 processed also partially exposed second well region 225-1；It is single for the second unit cell 113 (1), first The partially exposed second well region 225-2 of born of the same parents' control electrode insulating layer 235 and third well region 230, therefore it is formed in control electrode insulating layer Control electrode 250 on 235 also partially exposed second well region 225-2 and third well region 230.

In addition, terminal structure 130 includes multiple as shown in figure 4, being surrounded by terminal structure 130 on the outside of single cell structure 110 Field limiting ring 215 and multiple field plates 240, each width can be different with interval in field limiting ring 215.It is exemplary in Fig. 4 Ground, which is shown, includes the case where 12 field limiting ring 215 and 7 field plates 240, and schematically illustrates field plate 240 in figure and be located at the Two to the 8th field limiting ring 215 the case where, the presence of terminal structure 130 can improve knot edge effect, enable thyristor chip 10 have high voltage ability, when bias increase when, depletion layer extends to the outside, until the last one field limiting ring 215 cylinder or Spherical surface ties breakdown.The exemplary thyristor chip 10 of field plate structure with the disclosure can bear 1400V high pressure.Ying Li Solution, the disclosure are not limited to this, and can according to need the quantity and layout for suitably increasing or decreasing field limiting ring 215 and field plate 240.

Below with reference to Fig. 5 and Fig. 6, detailed description using in single cell structure 110 the first unit cell (i) (i ∈ 1,2 ... N, N be and the equal positive integer of the first unit cell sum) and the second unit cell 113 (j) (j ∈ 1,2 ... M, M are and the second unit cell is total Equal positive integer) realize that the high consistency of MOS control thyristor chip 10 opens the control principle of function and turn-off function.Figure 5 be the circuit diagram and Fig. 6 according to first unit cell 111 (1) of one embodiment of the disclosure for according to the one of the disclosure The circuit diagram of second unit cell 113 (1) of a embodiment.

Because it is N-MCT that in this embodiment, MOS, which controls thyristor chip 10, therefore the first conduction type is p-type, the Two conduction types are N-type.Although it will be understood by those skilled in the art that the MOS control thyristor chip 10 of the disclosure may be P-MCT, when for P-MCT, the first conduction type is also possible to N-type, and the second conduction type is also possible to p-type.Continue with knot Close circuit theory and controlling mechanism that Fig. 5 and Fig. 6 describes the N-MCT of the present embodiment.In the present embodiment, it is responsible for opening function Unit cell surrounds the unit cell for being responsible for turn-off function.

With the structure principle chart description of the first unit cell 111 (1) in Fig. 5 according to first unit cell of one embodiment of the disclosure 111 (i) (i ∈ 1,2 ... the positive integer that N, N are and the first unit cell sum is equal) open principle.In conjunction with Fig. 4, P type substrate 200, the buffer layer 205 and epitaxial layer 210 and the first well region of p-type 220 of N-type form PNP transistor Q1；N-type buffer layer 205 NPN transistor Q2, PNP transistor and NPN are formed with epitaxial layer 210, the first well region of p-type 220 and N-type the second well region 225-1 Transistor forms parasitic PNPN thyristor structure, meanwhile, the unlatching that NPN transistor Q2 is responsible for MOS control thyristor chip 10 is made With, when applying threshold voltage of the positive voltage greater than NPN transistor Q2 on coordination electrode G, NPN transistor Q2 conducting, due to Positive electrode applies high potential, and electric current forms guiding path in the longitudinal direction, and parasitic PNPN thyristor enters latch mode.

Second list in MOS control thyristor chip 10 is described by taking the structure principle chart of the second unit cell 113 (1) in Fig. 6 as an example Born of the same parents 113 (j) (j ∈ 1,2 ... the positive integer that M, M are and the second unit cell sum is equal) turn-off function.P type substrate 200, N-type Buffer layer 205 and epitaxial layer 210 and the first well region of p-type 220 form PNP transistor Q3；The buffer layer 205 and extension of N-type Layer 210, the first well region of p-type 220 and N-type the second well region 225-2 form NPN transistor Q4, and PNP transistor Q3 and NPN are brilliant Body pipe Q4 forms parasitic PNPN thyristor structure, meanwhile, the first well region of p-type 220, N-type the second well region 225-2 and p-type third Well region 230 forms the Pmos for being responsible for turning off and turns off pipe, and the shutdown for being responsible for MOS control thyristor chip 10 acts on, when in control electricity When applying threshold voltage of the negative voltage absolute value greater than PNP transistor Q3 on the G of pole, Pmos turns off transistor turns, will be parasitic Emitter region (N-type the second well region 225-1 and 225-2) and base area (the first well region 220 of p-type) short circuit of PNPN thyristor, it is parasitic PNPN thyristor is forced to exit latch mode, and device turns off immediately.

All in all, in the present embodiment, be responsible for opening function the first unit cell 111 (i) (i ∈ 1,2 ... N, N be with The equal positive integer of first unit cell sum) be distributed in MOS control thyristor chip 10 the second unit cell 113 (j) (j ∈ 1, 2 ... M, M be and the equal positive integer of the second unit cell sum) outer edge, uniformly surround the second unit cell 113 (j) (j ∈ 1, 2 ... M, M are the positive integer equal with the second unit cell sum), MOS controls the turn-on and turn-off process tool of thyristor chip 10 Have the characteristics that quick, consistent.

Specifically, it is fast that turn off process speed is connected in the MOS control thyristor chip 10 of the disclosure.It is applied when to coordination electrode G Increase when the positive voltage of NPN transistor Q2, the first unit cell 111 (i) (i ∈ 1,2 ... N, N are equal with the first unit cell sum Positive integer) in each Nmos open pipe conducting, as positive electricity pole tension increases, the electric current of the first well region of p-type 220 gradually increases Greatly, all P (the first well region 220 of p-type) N (the second well region 225-1 of N-type) knots all turn on, and electric current forms lead completely in the longitudinal direction Path, parasitic PNPN thyristor enter latch mode, apply absolutely when to the control electrode 250 on MOS control thyristor chip 10 When the negative voltage of the threshold voltage to value greater than PNP transistor Q3, Nmos opens pipe closing, meanwhile, Pmos turns off pipe conducting, will Second unit cell 113 (j) (j ∈ 1,2 ... M, M are positive integer) in PNPN thyristor emitter region (the second well region of N-type 225- 2) and base area (220 short circuit of the first well region of p-type) short circuit, thyristor are forced to exit latch mode, and MOS controls 10 quilt of thyristor chip It rapidly switches off.

The MOS control thyristor chip 10 of the disclosure has dual shutdown mechanism, good reliability.It is undergone in turn off process Two stages.Equally by taking the first conduction type is p-type as an example.First stage is the termination of coordination electrode G positive voltage, in fact When opening pipe threshold voltage less than Nmos from the positive voltage of coordination electrode G, Nmos opens pipe conducting and closes, the first trap of p-type Area does not have current flowing, and MOS control thyristor chip 10 has come into turn off process.Second stage is coordination electrode G negative The application of voltage, so that Pmos shutdown pipe conducting, the emitter and base stage for the parasitic thyristor being longitudinally formed are short-circuited, thyristor It is forced to exit latch, MOS control thyristor chip 10 quickly turns off, and two stages ensure that the reliability of shutdown.

Fig. 7 to Figure 13 is the view for showing 10 structure of chip of the disclosure formed according to exemplary method steps, below The structure of Fig. 7 to Figure 13 detailed description chip will be combined.For ease of description, with p-type for the first conduction type, N-type second Conduction type.It should be understood that the disclosure is not limited to such form, N-type is the first conduction type, and p-type is the second conduction type It is also possible.

As shown in fig. 7, the substrate 200 of preparation P-type conduction type, it is preferable that substrate 200 used by the utility model is thick Degree can be 500 microns.It does so, the fragment rate in chip manufacturing proces can be reduced, reduce cost.The base of P type substrate 200 N-type buffer layer 205 is grown on plinth, the doping concentration of buffer layer 205 is greater than the doping concentration of substrate 200.The concentration of buffer layer 205 Higher than the doping concentration of substrate 200, the mutual erosion between metal ion can be effectively prevented, meanwhile, it can reduce bulk resistor, Increase current density.On N-type buffer layer 205, one layer of N-type epitaxy layer 210 is grown, the doping concentration of epitaxial layer 210 is less than The doping concentration of buffer layer 205.

In the design of plane high tension apparatus, knot curvature effect is reduced frequently with field limiting ring structure and causes surface field Concentration problem, to improve the breakdown voltage of component.It is gradually increased when being added in the main voltage tied, the depletion region of main knot is also gradually Toward external expansion, voltage is increased to before the avalanche voltage of main knot, and the depletion region of two knots (main knot and field limiting ring) has just converged It closes, the main voltage landing for tying receiving can be shared by ring using multiple field limiting rings, premature breakdown is prevented, to improve breakdown Voltage.

Based on the above principles, in order to improve the breakdown voltage that the MOS of the disclosure controls thyristor chip 10, as shown in figure 8, Multiple field limiting rings 215 in epitaxial layer 210 are extended by the surface of the separate substrate 200 of epitaxial layer 210.Preferably, it can adopt It can be properly arrived at predetermined voltage class with the field limiting ring 215 of 12 field limiting rings 215, the number, and not will cause MOS control The waste of 10 area of thyristor chip.Preferably, the distance between 215 middle ring of field limiting ring and ring in the disclosure, ring width can With difference, it can according to need and be modified.

As shown in figure 9, being extended into epitaxial layer 210 by upper surface, the trap of p-type is formed, constitutes the first well region of p-type 220, Its position is in the region that field limiting ring 215 surrounds.

Therefore, P type substrate 200, the buffer layer 205 of N-type and epitaxial layer 210, the first well region of p-type 220 form parasitic PNP Transistor (the PNP transistor Q1 or PNP transistor Q3 in such as Fig. 5 and Fig. 6).

Further, as shown in Figure 10, the first well region of p-type is extended by the upper surface of the separate substrate of the first well region The trap of multiple N-types in 220 forms the first unit cell 111 (i) (i ∈ close to the circle that field limiting ring 215 arranges in the trap of multiple N-type 1,2 ... N, N are positive integer) in the second well region 225-1, in the circle trap by rule, uniformly fill up the first well region of p-type 220 The trap of other N-types, constitute the second unit cell 113 (j) (j ∈ 1,2 ... M, M are positive integer) in the second well region 225-2.

Therefore, buffer layer 205 and epitaxial layer 210, the first well region of p-type 220, N-type the second well region 225-1 or 225-2 of N-type Form parasitic NPN transistor (the NPN transistor Q2 or NPN transistor Q4 in such as Fig. 5 and Fig. 6).

P type substrate 200, the buffer layer 205 of N-type and epitaxial layer 210, the first well region of p-type 220, N-type the second well region 225- 1 or 225-2 forms parasitic PNPN thyristor, provides circulation path to cathode current for anode.

As shown in figure 11, multiple p-type third well regions 230 by upper surface extend into multiple N-type the second well region 225-1 and In 225-2, still, circle N-type the second well region 225-1 or 225-2 close to the first well region 220 should not form multiple p-type thirds Well region 230.

Therefore, the first well region of p-type 220, the second well region of N-type 225-2, p-type third well region 230 form parasitic PNP crystal Pipe, can be used as the shutdown pipe of chip 10.

Further, as shown in figure 12, it grows and etches to form control electrode insulating layer 235 in the upper surface of chip 10.Its Thickness effect Nmos opens the threshold voltage size of pipe and Pmos shutdown pipe, needs accurately to control.

As shown in figure 13, it is deposited after 235 step of control electrode insulating layer and etches to form one layer of polysilicon 240,245, shape At the control electrode 245 in the field plate 240 and single cell structure 110 of terminal structure 130.

Preferably, the field plate 240 that polysilicon can be only formed on the 2nd to the 8th ring of field limiting ring 215, passes through change Surface potential distribution increases the radius of curvature of curved surface knot, inhibits the concentration of surface field, to improve the breakdown voltage of device. Preferably, applying bias voltage, the distribution of charges at dynamic regulation chip surface is not added using the form of floating in field plate 240.It is logical The compound use of field plate 240 and field limiting ring 215 is crossed, field limiting ring 215 has apparent effect to the effect of the partial pressure of single cell structure 110 Fruit, and field plate 240 is for the influence highly significant of inhibition surface charge effect, it can be ensured that reach scheduled backward voltage etc. Grade.

Control electrode 245 is formed in single cell structure 110 on the surface of control electrode insulating layer 235, is located at the second well region 225-1 Top between the second well region 225-2 or between two the second well region 225-2, and a part of p-type third well region 230 is covered, And the first well region 220 between covering the second well region 225-1 and the second well region 225-2 or between two the second well region 225-2 Part, multistage polysilicon 245 is connect with control electrode PAD, as coordination electrode G.

Finally, metal layer, such as Al are formed on each the second well region of N-type 225, with 245 spatial complementary of polysilicon, As cathode 250；The another side for being formed in the substrate of chip 10 forms metal layer, such as Ti/Ni/Ag, as anode 255, from And form complete structure shown in Fig. 4.

Obviously, the above embodiments of the present invention is merely examples for clearly illustrating the present invention, and It is not limitations of the embodiments of the present invention, for those of ordinary skill in the art, in above description On the basis of can also make other variations or changes in different ways, all embodiments can not be exhaustive here, It is all to belong to obvious changes or variations that the technical solution of the utility model is extended out still in the utility model The column of protection scope.

Claims (9)

1. a kind of MOS controls thyristor chip, which is characterized in that including

It is formed in the first electrode of chip-side,

It is formed in the second electrode lay that the chip other side includes second electrode and coordination electrode,

The single cell structure being formed between the first electrode and the second electrode, the single cell structure include multiple be connected in parallel First kind unit cell and multiple Second Type unit cells being connected in parallel, the first kind unit cell is to open unit cell, and described Second Type unit cell is shutdown unit cell；And

Terminal structure is located at the single cell structure periphery.

2. MOS according to claim 1 controls thyristor chip, which is characterized in that the multiple unit cell of opening surrounds institute State multiple shutdown unit cells.

3. MOS according to claim 2 controls thyristor chip, which is characterized in that the multiple unit cell of opening is described Multiple shutdown unit cell periphery individual pen settings.

4. MOS according to claim 2 controls thyristor chip, which is characterized in that the multiple quantity for opening unit cell Less than the quantity of the multiple shutdown unit cell.

5. MOS as described in claim 1 controls thyristor chip, which is characterized in that the first kind unit cell includes successively It is formed in the first conductivity type substrate:

The buffer layer of second conduction type；

The epitaxial layer of second conduction type；

It is formed in the first well region of the first conduction type in the epitaxial layer；

It is formed in the second well region of the second conduction type in first well region；

The control electrode insulating layer being formed on first well region and second well region, partially exposed second well region；

The control electrode being formed on the control electrode insulating layer；

The first electrode being formed on exposed second well region；And

The second electrode being formed on the substrate other side.

6. MOS as described in claim 1 controls thyristor chip, which is characterized in that the Second Type unit cell includes successively It is formed in the first conductivity type substrate:

The buffer layer of second conduction type；

The epitaxial layer of second conduction type；

It is formed in the first well region of the first conduction type in the epitaxial layer；

It is formed in the second well region of the second conduction type in first well region；

The third well region being formed in second well region includes described in spaced apart two in each second well region Third well region；

The control electrode insulating layer being formed on first well region, the second well region and third well region, partially exposed described second Well region and the third well region；

The control electrode being formed on the control electrode insulating layer；

The first electrode being formed on exposed second well region and the third well region；And

The second electrode being formed on the substrate other side.

7. as MOS described in claim 5 or 6 controls thyristor chip, which is characterized in that first conduction type is p-type, Second conduction type is N-type.

8. as MOS described in claim 5 or 6 controls thyristor chip, which is characterized in that first conduction type is N-type, Second conduction type is p-type.

9. MOS as described in claim 1 controls thyristor chip, which is characterized in that the terminal structure includes multiple field plates With multiple field limiting rings, the multiple field limiting ring is spaced apart, and the multiple field plate is arranged in above the multiple field limiting ring and portion Divide the corresponding field limiting ring in the multiple field limiting ring of covering.