CN205881911U - Ditch cell type siC primitive unit cell for MOSFET - Google Patents
Ditch cell type siC primitive unit cell for MOSFET Download PDFInfo
- Publication number
- CN205881911U CN205881911U CN201620773343.6U CN201620773343U CN205881911U CN 205881911 U CN205881911 U CN 205881911U CN 201620773343 U CN201620773343 U CN 201620773343U CN 205881911 U CN205881911 U CN 205881911U
- Authority
- CN
- China
- Prior art keywords
- region
- unit cell
- primitive unit
- groove
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000737 periodic effect Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
The utility model discloses a ditch cell type siC primitive unit cell for MOSFET, the below and the slot bottom of the base region of primitive unit cell all are provided with a doped region again, again the doped region the doping type with the base region keeps the doping type unanimous and drift region opposite, the doped region again of base region below is the B region, and the B region links to each other with the base region, the doped region again of slot bottom is the C region, and the C regional setting is under the slot, the ditch groove depth 0.2 of the depth ratio primitive unit cell of doped region again 1 mu m. The utility model provides a ditch cell type siC primitive unit cell for MOSFET has gone on respectively adulterateing in the base region below of primitive unit cell (B is regional) and slot bottom (C is regional) again, and B and C are regional to form opposite doping type with the drift region, is in at the device and blocks under the condition, forms the electric field of depletion region, shielding slot bottom at the drift region to the bottom and the corner of slot have been protected.
Description
Technical field
The present invention relates to power semiconductor field, be specifically related to a kind of groove-shaped SiC MOSFET primitive unit cell.
Background technology
SiC trench MOSFET (UMOSFET) has a lot of advantage, as p base can eliminate with being epitaxially-formed
The impact that when ion implanting forms p base, defect is brought, it addition, the primitive unit cell of trench MOSFET can be accomplished less, electric current is close
Du Genggao, especially for the price that SiC material is expensive, can significantly reduce chip cost.But there is trench bottom in UMOSFET
Portion's electric field is concentrated, so that the problem of gate medium poor reliability, Fig. 1 is the signal of the n-channel UMOSFET primitive unit cell of a kind of common specification
Figure, in the off case, the high pressure being added in drain electrode will act on drift layer, and the A point of channel bottom will be that electric field collects most
In place, the gate medium causing channel bottom is the most breakdown.In order to solve this problem, some those skilled in the art set
Count source groove structure, reached the effect of shield grid with the groove structure in source, reduce the electric field of grid.But this complex process,
Also can increase the size of primitive unit cell simultaneously.
Summary of the invention
For problems of the prior art, it is an object of the invention to provide a kind of groove-shaped SiC MOSFET with former
Born of the same parents, this primitive unit cell (B region) and channel bottom (C region) below the base of primitive unit cell carried out adulterating respectively again, B and C region with
Drift region forms contrary doping type, in the case of device is in blocking-up, forms depletion region in drift region, bottom shield trenches
Electric field, thus protect bottom and the corner of groove.
For achieving the above object, the present invention is by the following technical solutions:
A kind of groove-shaped SiC MOSFET primitive unit cell, the lower section of the base of described primitive unit cell and channel bottom are provided with one
Doped region again, the doping type of described doped region again and described base keep consistent, and the doping type of drift region is contrary；Base
The doped region again of lower section is B region, and B region is connected with base；The doped region again of channel bottom is C region, and C region is arranged on ditch
The underface of groove；The ditch groove depth 0.2-1 μm of the depth ratio primitive unit cell of described doped region again.
Further, described B region distance slot wedge 1-4 μm.
Further, described B region distance slot wedge 1.5 μm.
Further, the width little 0.4-2 μm of the width ratio groove in described C region.
Further, described B region and described C region are not attached to, therebetween be spaced apart 1.5-5 μm.
Further, described B region is connected with described C region, constitutes another kind of structure primitive unit cell.
Further, described primitive unit cell, when forming the active area structure of device, is not attached to described C region with described B region
The primitive unit cell of structure is main being arranged in parallel；The primitive unit cell sparse distribution of connected structure, in periodic arrangement.
The invention have the advantages that
The primitive unit cell of the application (B region) and channel bottom (C region) below the base of primitive unit cell have carried out adulterating respectively again,
B and C region forms contrary doping type with drift region, in the case of device is in blocking-up, forms depletion region, screen in drift region
Cover the electric field of channel bottom, thus protect bottom and the corner of groove.The disjunct general primitive cell structure in B region and C region
In, the interval between B region and C region more than without space width of depletion region between B and C region under applied voltage, B region and
Groove pitch is greater than without the space width of depletion region of drift layer under applied voltage, keeps current conducting path.
Accompanying drawing explanation
Fig. 1: SiC UMOSFET primitive unit cell schematic diagram in prior art；
The SiC UMOSFET primitive unit cell general structure schematic diagram of Fig. 2: the application；
The SiC UMOSFET another kind structure primitive cell structure schematic diagram of Fig. 3: the application；
In figure, 1-source electrode, 2-isolate passivation layer, 3-drain electrode, 4-base, 5-drift region, 6-substrate, 7-B region, 8-
C region, 9-polygate electrodes, 10-gate oxide.
Detailed description of the invention
Below, with reference to accompanying drawing, the present invention is more fully illustrated, shown in the drawings of the exemplary enforcement of the present invention
Example.But, the present invention can be presented as multiple multi-form, is not construed as the exemplary enforcement being confined to describe here
Example.And it is to provide these embodiments, so that the present invention is fully and completely, and will fully convey the scope of the invention to this
The those of ordinary skill in field.
For ease of explanation, here can use such as " on ", the space relative terms such as D score " left " " right ", be used for
Shown in bright figure a element or feature are relative to another element or the relation of feature.It should be understood that except in figure
Outside the orientation illustrated, spatial terminology is intended to include device different azimuth in use or operation.Such as, if in figure
Device is squeezed, be stated as being positioned at the element of other elements or feature D score will be located into other elements or feature " on ".Cause
This, exemplary term D score can comprise upper and lower both orientation.Device can otherwise position (90-degree rotation or be positioned at
Other orientation), relatively illustrate used herein of space correspondingly to explain.
Following content is all described in detail as a example by n-channel type UMOSFET.
As Figure 2-3, this application provides a kind of groove-shaped SiC MOSFET primitive unit cell, the lower section of the base 4 of primitive unit cell
And channel bottom is provided with a doped region again, then the doping type of doped region keeps consistent with the doping type of base 4, and
The doping type of drift region 5 is contrary；Doped region again below base 4 is B region 7, and B region 7 is connected with base 4；Channel bottom
Doped region again be C region 8, C region 8 is arranged on the underface of groove；Ditch groove depth 0.2-1 of the depth ratio primitive unit cell of doped region again
μm。
The SiC UMOSFET primitive unit cell of the present invention, by adulterating again at base 4 and channel bottom, it is achieved shield grid is situated between
The purpose of matter electric field.As a example by n-channel UMOSFET device, below the p base of primitive unit cell, carry out p-type respectively with channel bottom
Doping.B and C region forms contrary doping type with drift region, in the case of device is in blocking-up, is formed in drift region and exhausts
District, the electric field bottom shield trenches, thus protect bottom and the corner of groove.The interval in B and C region can be 1.5 μm-5 μ
Between m, interval is greater than nothing more than without space width of depletion region between B and C region under applied voltage, B region and groove pitch
The space width of depletion region of drift layer under applied voltage, keeps current conducting path.
In part primitive unit cell in the whole chip being made up of the primitive unit cell of the application, B region 7 with C region 8 is being electrically
Being connected, in the present invention, this part primitive unit cell is called second structure primitive unit cell.Electrically being connected is by between region 8, B region 7 and C
Drift region portion be also carried out p-type (as shown in Figure 3) doping content of realizing of doping can be identical with B, C district, it is also possible to
Difference is preferably consistent with B district and C district.The purpose that C district keeps electricity to be connected with B district is, makes C district and B district, simultaneously with source electricity
Pole keeps current potential consistent.The second structure primitive unit cell that these B regions 7 are connected with C region 8 is also periodic arrangement in whole chip active district
's.As for the primitive cell structure that surface is stripe array layout, can periodically be distributed second structure primitive unit cell, the primitive unit cell of second structure
Size is consistent with original structure, and in second structure, B region is that 1-3 μm is (for being perpendicular to paper in figure with the width L of the part of C regional internet
Direction, face).Interconnection portion is not as the passage of conduction, and therefore area needs the least.So, by these second structures
Primitive unit cell, the B region of all primitive unit cells of whole chip also forms electricity with C region and is connected.
For the primitive cell structure that surface is rectangular array layout, owing to groove interconnects together, the most only need
The C district bottom part of trench is wanted to connect with B district.The most periodically distribution second structure primitive unit cell, the primitive unit cell of second structure
Size is consistent with original structure, and in second structure, B region is little with the width of the part of C regional internet (for being perpendicular to paper direction in figure)
In the size equal to source table top.Interconnection portion is not as the passage of conduction, and therefore area needs the least.
For the primitive cell structure that surface is other layouts such as hexagon solid matter or atomic lattice, also it is by similar method.
Whole device architecture also includes tying terminal part and electrode briquetting part, and knot termination environment can use knot termination extension method
(JTE) and the structure such as field limiting ring method (FLR), known to the engineer of this area.
With a concrete SiC UMOSFET structure, the application is described further below:
Such as the SiC UMOSFET structure of a 1200V, the doping content of drift region is 5-7E15cm-3, thickness is 10-12 μ
m.Doping content 1E16-2E17 of p base, thickness is 1-2 μm.The doping content in n++ district is more than 1E19, and thickness is 0.3-0.5 μ
m.P++ doping content is more than 1E19, and thickness is more than or equal to n++ district thickness.Gash depth 0.2-0.5 deeper than p base μm, width is
1-2μm.Isolation passivation layer 2 width ratio groove width width 1-2 μm.Source Ohm contact electrode a size of 2 μm.Then primitive unit cell width is 6-
8μm.Centered by primitive cell structure axisymmetric.It is said that in general, primitive unit cell size is the least, the primitive unit cell density of unit are is the highest, electric current
Density is the biggest.But the ability of the design technique platform to be considered of primitive unit cell live width.
Between the depth ratio ditch groove depth 0.2-0.5 μm in B region and C region, doping type is consistent with base, with drift region phase
Instead.B district connects together with base.Primitive unit cell to general structure, B region distance slot wedge 1.5 μm.C region groove just under
Side, little 0.4 μm of width ratio groove width.The line space design in B with C region is wanted effectively to shield under device high pressure blocking state
Channel bottom and gate medium, therefore can not be the widest.Simultaneously in the structure of whole device, second structure primitive unit cell periodic arrangement, B and C
The width (for being perpendicular to paper direction in figure) of the interconnection portion in region is less than the size of source table top.
The PaD design of the source electrode 1 of device and polygate electrodes 9 and the general design side of the design reference of knot terminal
Method, wherein knot terminal can be field limiting ring (FLR) structure or tie termination extension (JTE) structure or other structures, in this area
Known to engineer.
Fill in groove for polygate electrodes 9, groove outer layer is gate oxide 10；It is drain electrode 3 bottom primitive unit cell, leakage
Electrode 3 is arranged above substrate 6.
Described above simply to illustrate that the present invention, it is understood that to the invention is not limited in above example, meet
The various variants of inventive concept are all within protection scope of the present invention.
Claims (7)
1. a groove-shaped SiC MOSFET primitive unit cell, it is characterised in that lower section and the channel bottom of the base of described primitive unit cell are equal
It is provided with a doped region again, the doping type of described doped region again and described base and keeps consistent, and the doping class of drift region
Type is contrary；Doped region again below base is B region, and B region is connected with base；The doped region again of channel bottom is C region, C
Region is arranged on the underface of groove；The ditch groove depth 0.2-1 μm of the depth ratio primitive unit cell of described doped region again.
Groove-shaped SiC MOSFET primitive unit cell the most according to claim 1, it is characterised in that described B region distance groove
Edge 1-4 μm.
Groove-shaped SiC MOSFET primitive unit cell the most according to claim 2, it is characterised in that described B region distance groove
Edge 1.5 μm.
Groove-shaped SiC MOSFET primitive unit cell the most according to claim 1, it is characterised in that the width ratio in described C region
The width little 0.4-2 μm of groove.
Groove-shaped SiC MOSFET primitive unit cell the most according to claim 1, it is characterised in that described B region and described C district
Territory is not attached to, therebetween be spaced apart 1.5-5 μm.
Groove-shaped SiC MOSFET primitive unit cell the most according to claim 1, it is characterised in that described B region and described C district
Territory is connected, and constitutes another kind of structure primitive unit cell.
7. according to the arbitrary described groove-shaped SiC MOSFET primitive unit cell of claim 1-6, it is characterised in that described primitive unit cell is in group
When becoming the active area structure of device, the primitive unit cell being not attached to structure with described B region and described C region is main being arranged in parallel；It is connected
The primitive unit cell sparse distribution of structure, in periodic arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620773343.6U CN205881911U (en) | 2016-07-21 | 2016-07-21 | Ditch cell type siC primitive unit cell for MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620773343.6U CN205881911U (en) | 2016-07-21 | 2016-07-21 | Ditch cell type siC primitive unit cell for MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205881911U true CN205881911U (en) | 2017-01-11 |
Family
ID=57698541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620773343.6U Active CN205881911U (en) | 2016-07-21 | 2016-07-21 | Ditch cell type siC primitive unit cell for MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205881911U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876485A (en) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof |
| CN109728075A (en) * | 2018-12-07 | 2019-05-07 | 北京大学深圳研究生院 | A kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure |
| CN109920854A (en) * | 2019-03-07 | 2019-06-21 | 中国科学院半导体研究所 | MOSFET element |
| CN114678413A (en) * | 2022-03-25 | 2022-06-28 | 电子科技大学 | High-reliability silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) device integrating P-type channel |
-
2016
- 2016-07-21 CN CN201620773343.6U patent/CN205881911U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876485A (en) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof |
| WO2018161412A1 (en) * | 2017-03-06 | 2018-09-13 | 北京世纪金光半导体有限公司 | Sic dual-trench mosfet device having integrated schottky diode and preparation method therefor |
| CN106876485B (en) * | 2017-03-06 | 2020-11-10 | 北京世纪金光半导体有限公司 | SiC double-groove MOSFET device integrated with Schottky diode and preparation method thereof |
| CN109728075A (en) * | 2018-12-07 | 2019-05-07 | 北京大学深圳研究生院 | A kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure |
| CN109920854A (en) * | 2019-03-07 | 2019-06-21 | 中国科学院半导体研究所 | MOSFET element |
| CN114678413A (en) * | 2022-03-25 | 2022-06-28 | 电子科技大学 | High-reliability silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) device integrating P-type channel |
| CN114678413B (en) * | 2022-03-25 | 2023-04-28 | 电子科技大学 | High reliability silicon carbide MOSFET device integrating P-channel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9698216B2 (en) | Semiconductor device having a breakdown voltage holding region | |
| CN105448961B (en) | The terminal protection structure of superjunction devices | |
| JP3979258B2 (en) | MIS semiconductor device and manufacturing method thereof | |
| CN205881911U (en) | Ditch cell type siC primitive unit cell for MOSFET | |
| US7282386B2 (en) | Schottky device and method of forming | |
| CN104752511B (en) | Field-effect semiconductor device and its manufacture | |
| CN112786587B (en) | Silicon carbide MOSFET device and cellular structure thereof | |
| CN108428740B (en) | IGBT chip with composite gate structure containing virtual gate | |
| CN108257953A (en) | The semiconductor devices of diode region not can be switched with IGBT areas and | |
| CN102694011A (en) | Semiconductor device | |
| US20150179758A1 (en) | Semiconductor device and method of manufacturing the same | |
| CN106469751A (en) | Semiconductor device and preparation method thereof | |
| CN104716168A (en) | Semiconductor Device with Recombination Region | |
| US9236500B2 (en) | Schottky barrier diode and method for manufacturing schottky barrier diode | |
| CN203351612U (en) | Schottky diode | |
| CN102263125A (en) | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides | |
| EP2860761A1 (en) | Semiconductor device | |
| CN103022114B (en) | High voltage and high power IGBT (Insulated Gate Bipolar Translator) chip based on cutoff rings and designing method of chip | |
| CN205376539U (en) | Diode, array substrate , display device | |
| CN104201253B (en) | A kind of gallium nitride device and its manufacture method | |
| CN105990153B (en) | The preparation method and power device of the partial-pressure structure of power device | |
| CN106558571B (en) | A kind of ESD layout structure, electronic device | |
| JP3301271B2 (en) | Horizontal power MOSFET | |
| CN102623496B (en) | Matrix type mos field effect transistor | |
| CN113629128B (en) | Semiconductor device with a plurality of transistors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| PP01 | Preservation of patent right | ||
| PP01 | Preservation of patent right |
Effective date of registration: 20180814 Granted publication date: 20170111 |
|
| PD01 | Discharge of preservation of patent | ||
| PD01 | Discharge of preservation of patent |
Date of cancellation: 20200810 Granted publication date: 20170111 |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231116 Address after: Room JZ2467, Yard 2, Junzhuang Road, Junzhuang Town, Mentougou District, Beijing, 102399 (cluster registration) Patentee after: Beijing Xingyun Lianzhong Technology Co.,Ltd. Address before: 101111 Courtyard 17, Tonghui Ganqu Road, Economic and Technological Development Zone, Tongzhou District, Beijing Patentee before: BEIJING CENTURY GOLDRAY SEMICONDUCTOR Co.,Ltd. |