CN109728075A - A kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure - Google Patents
A kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure Download PDFInfo
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Abstract
A kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure; the SiC-TMOS device includes the N+ substrate being arranged from bottom to top, N- drift layer; it further include AOD layers and the first metal layer; AOD layers are set to the upper surface of N- drift layer and contact to form SBD with the first metal layer, are equipped with symmetrical protection structure AOD layers of sides to carry out pressure-resistant protection to SBD.In a first aspect, symmetrical protection structure is arranged AOD layers of side, so that the SiC-TMOS device of the application has the turn-on effect of double channel, it can effectively reduce conducting resistance and enhance the stability of conducting；Second aspect; due to being equipped with p type island region domain, trench-gate region and P+ shielded layer in protection structure; so that its pressure-resistant protection feature for having three layers; each protective layer can form Charged Couple and reduce electric leakage when exhausting; the blocking voltage ability for promoting device also reduces influence suffered by basic property of the SiC-TMOS device in built-in SBD, with good application prospect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of SiC-TMOS device of built-in SBD protection structure and
Its production method.
Background technique
In the development process of power electronics industry, semiconductor technology plays decisive role, wherein power semiconductor
Device have always been considered as be power electronic equipment key components.With power electronic technique industry, medical treatment, traffic,
The extensive use of the industries such as consumption, power semiconductor directly affect the cost and efficiency of these power electronic equipments.
Traditional power semiconductor is dominated by silicon-based power devices, mainly with thyristor, power P IN device, function
Based on rate dipole device, Schottky barrier diode, power MOSFET and isolated-gate field effect transistor (IGFET), in total power
It is widely used in range.However, the performance of this kind of device has been approached the theoretical limit of silicon materials, it has been difficult
Reach the significantly promotion in performance by design to silicon-based power devices and optimization.
It is special to have excellent material with the semiconductor material with wide forbidden band that silicon carbide (SiC) and gallium nitride (GaN) etc. are representative
Property, it is considered as generation semiconductor material.Elastic braid semiconductor material its compared to silicon materials have biggish forbidden bandwidth, compared with
High thermal conductivity, higher electronics saturation drift velocity, and decuple the critical breakdown electric field of silicon materials, make its high temperature,
Become very ideal semiconductor material under high frequency, high-power, anti-radiation application, the energy of electronic equipment can be significantly reduced
Consumption.
Currently, wide band gap semiconductor device because its relative to silicon-based power devices have more superior performance, more
A field is applied.In terms of high voltage and high-power applications, the device based on SiC attracts attention, SiC-MOSFET device
Not only with the working mechanism of single polarization, also there is the cheap property for designing and manufacturing technique, therefore such device is received
And application.Although SiC material blocking voltage with higher and conducting resistance, biggish forbidden bandwidth will lead to SiC-
The problem of MOSFET element has biggish cut-in voltage, may cause bipolar degeneration when to the operation of the body diode of itself.Cause
This can take the external method with the reversed parallel SiC-SBD of SiC-MOSFET device in the design of most power electronic systems
It solves the problems, such as, due to the application requirement of high power density, is often combined using external SiC-SBD with SiC-MOSFET device
Method improve the reverse conductance energy of device, however, how SiC-SBD to be combined with SiC-MOSFET device without shadow
The performance of sound MOSFET element is still the technological challenge in field.
Summary of the invention
The present invention solves the technical problem of influence when how to reduce built-in SBD on the performance of SiC-TMOS device.
In order to solve the above technical problems, the application provides a kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure.
According in a first aspect, providing a kind of SiC-TMOS device of built-in SBD protection structure in a kind of embodiment comprising
The N+ substrate that is arranged from bottom to top, N- drift layer, further include AOD layers and the first metal layer；Described AOD layers is set to the N- and drifts about
The upper surface of layer, contacts to form SBD with the first metal layer, and AOD layers of the side is equipped with symmetrical protection structure,
The protection structure is used to carry out the SBD pressure-resistant protection.
The protection structure includes the first protective layer, the second protective layer and the third protective layer of sequence setting；
First protective layer includes p type island region domain, is used to form Charged Couple and reduces electric leakage when exhausting, is described
SBD provides the pressure resistance protection of first layer；
Second protective layer includes trench-gate region, is used to form Charged Couple and is reducing electric leakage when exhausting,
The pressure resistance protection of the second layer is provided for the SBD；
The third protective layer includes P+ shielded layer, is used to form Charged Couple and reduces electric leakage when exhausting, is described
SBD provides the pressure resistance protection of third layer.
The p type island region domain includes N+ doped region, the P+ doped region that the ecto-entad on P base and P base is arranged side by side,
The P base provides pressure-resistant protection for the SBD.
Trench-gate region in second protective layer extends to the top of the SiC-TMOS device, the p type island region
Domain is set to the outside in the trench-gate region, the P base and the N+ doped region and the trench gate in the p type island region domain
Polar region domain contacts, and the P+ shielded layer in the third protective layer is set to the lower surface in the trench-gate region；
The first metal layer is set to the top of the SiC-TMOS device, and described AOD layers by described symmetrical
The intermediate region of protection structure extends to the first metal layer, described AOD layers respectively with the P+ shielded layer, the trench gate
Polar region domain, the p type island region domain one or more sides be in contact.
The first metal layer covers the upper surface in the p type island region domain, connects with the N+ doped region, the P+ doped region
Touching, for the N+ doped region and described AOD layers to be isolated, the N+ doped region is used to form described the P+ doped region
The source electrode of SiC-TMOS device；
The lower surface of the N+ substrate is equipped with second metal layer, and the second metal layer contacts to form Europe with the N+ substrate
Nurse contact, the second metal layer are used to form the drain electrode of the SiC-TMOS device；
The side wall in the trench-gate region is equipped with oxide layer, is equipped with polysilicon layer, the polysilicon layer within side wall
It is used to form the grid of the SiC-TMOS device.
According to second aspect, a kind of production method of SiC-TMOS device is provided in a kind of embodiment, comprising the following steps:
N+ substrate is set, N- drift layer is made in the N+ upper surface of substrate using epitaxy technique；
AOD layers are epitaxially formed on the N- drift layer；
Using doping process, etch process, oxidation technology and depositing operation, symmetrical point of building in AOD layers of the side
The protection structure of cloth, the protection structure are used to carry out the SiC-TMOS device pressure-resistant protection.
It is described to use doping process, etch process, oxidation technology and depositing operation, in AOD layers of side building pair
Claim the protection structure of distribution, comprising:
The material that injecting p-type is adulterated on AOD layers of the side forms the P base of predetermined width and thickness；
It is etched downwards from described AOD layers of top edge, forms groove, so that the width of the groove is less than the P
The width of base, and the thickness for making the depth of the groove be greater than the P base；
It adulterates to form P+ shielded layer in the bottom of the groove, and the P+ shielded layer is avoided to connect with the N- drift layer
Touching；
The P base is doped and annealing forms p type island region domain, the lower layer in the p type island region domain is P base, and upper layer is by outer
Inwardly N+ doped region, P+ doped region side by side；
Oxidation growth and polysilicon deposition are carried out to the groove, form trench-gate region, the trench-gate region
Including the oxide layer on side wall and the polysilicon layer within side wall.
The intermediate region by the symmetrical protection structure described AOD layers extends to the SiC-TMOS device
Top is in contact with one or more sides in the P+ shielded layer, the trench-gate region, the p type island region domain respectively.
Above-mentioned production method further include:
The first metal layer is accumulated on the top of the SiC-TMOS device, the first metal layer covers the p type island region domain
In N+ doped region and P+ doped region, and covering extend to the SiC-TMOS device top AOD layer, first gold medal
Belong to layer to be contacted with described AOD layer to form SBD, the P+ doped region for the N+ doped region and the AOD layers of progress every
From the N+ doped region is used to form the source electrode of the SiC-TMOS device；
The N+ substrate lower surface accumulate second metal layer, the second metal layer be in contact with the N+ substrate with
Ohmic contact is formed, the second metal layer is used to form the drain electrode of the SiC-TMOS device；
The polysilicon layer in the trench-gate region is used to form the grid of the SiC-TMOS device.
The p type island region domain constitutes the first protective layer of the protection structure, is used to form Charged Couple and subtracts when exhausting
Few electric leakage provides the pressure resistance protection of first layer for the SBD；
The trench-gate region constitutes the second protective layer of the protection structure, is used to form Charged Couple and is consuming
Electric leakage is reduced when to the greatest extent, provides the pressure resistance protection of the second layer for the SBD；
The P+ shielded layer constitutes the third protective layer of the protection structure, is used to form Charged Couple and subtracts when exhausting
Few electric leakage provides the pressure resistance protection of third layer for the protection structure.
The beneficial effect of the application is:
A kind of SiC-TMOS device and preparation method thereof of built-in SBD protection structure according to above-described embodiment, the SiC-
TMOS device includes the N+ substrate being arranged from bottom to top, N- drift layer, further includes AOD layers and the first metal layer, and the AOD layers is set to
The upper surface of N- drift layer contacts to form SBD with the first metal layer, and AOD layers of side is equipped with symmetrical protection structure, should
Structure is protected to be used to carry out pressure-resistant protection to the SBD of formation；The production method includes: setting N+ substrate, is existed using epitaxy technique
N- drift layer is made in the N+ upper surface of substrate, and AOD layers are epitaxially formed on N- drift layer, using doping process, etch process,
Oxidation technology and depositing operation construct symmetrical protection structure AOD layers of side.In a first aspect, AOD layers of side
Symmetrical protection structure is set, so that the SiC-TMOS device of the application has the turn-on effect of double channel, can effectively be dropped
Low on-resistance and the stability for enhancing conducting；Second aspect, due to being equipped with p type island region domain, trench-gate region in protection structure
With P+ shielded layer, so that protection structure has three layers of pressure-resistant protection feature, each protective layer can form Charged Couple simultaneously
Electric leakage is reduced when exhausting, further promote the blocking voltage ability of device and reduces electric leakage, makes claimed SiC-TMOS
The blocking voltage ability and levels of leakage of device are better than traditional TMOS device；The SBD protection structure of the third aspect, setting passes through
The electron screening of the AOD layer that trench-gate region is connected with source electrode acts on, reduce MOS device gate-drain capacitance and gate-drain with
The ratio of gate-source capacitance substantially increases Performance And Reliability of the device in application；Fourth aspect protects the construction of structure
Influence suffered by basic property of the SiC-TMOS device in built-in SBD is reduced, but also the pressure-resistant performance of device is mentioned
It rises, has certain performance advantage, there is preferable application prospect in terms of power electronic；5th aspect, the SiC-TMOS device
Production method use tradition TMOS device doping, etching, oxidation, depositing operation, enable to the manufacture of the device
Journey is mutually compatible with conventional fabrication processes, does not need additional exposure mask, and process complexity is low, strong operability, coordinates well
Contradiction between device performance and process complexity brings market application value to reduce the manufacturing cost of device.
Detailed description of the invention
Fig. 1 is the structure chart of the SiC-TMOS device of the application protection；
Fig. 2 is the structure chart for protecting structure；
Fig. 3 is the flow chart of the production method of the SiC-TMOS device of the application protection；
Fig. 4 is the flow chart for protecting construction manufacturing method；
Fig. 5 is the effect diagram for protecting structure fabrication；
Fig. 6 is the effect diagram that doping forms P base on AOD layer；
Fig. 7 is the effect diagram that etching forms groove on AOD layer；
Fig. 8 is the effect diagram that doping forms P+ shielded layer on AOD layer；
Fig. 9 is the effect diagram that doping forms p type island region domain on P base；
Figure 10 is the effect diagram that the growth of groove internal oxidition and polysilicon deposition form trench-gate region.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.Wherein different embodiments
Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to
The application is better understood.However, those skilled in the art can recognize without lifting an eyebrow, part of feature
It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen
Please it is relevant it is some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake
More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they
Relevant operation can be completely understood according to the general technology knowledge of description and this field in specification.
It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way
Kind embodiment.Meanwhile each step in method description or movement can also can be aobvious and easy according to those skilled in the art institute
The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain
A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.
It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object,
Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and
It is indirectly connected with (connection).
For the technical solution for clearly and accurately understanding the application, some terms will be illustrated here.
SiC, i.e. silicon carbide, a kind of wide bandgap semiconductor compound, are very suitable to the production of power device.
SiC-TMOS device is power mainly using NMOS N-channel MOS N made of SiC semiconductor material
One kind of MOSFET element, main application have switch, driver etc..Conventional MOSFET device is transverse conductance structure, device
Usually it is made in the front of chip.
SBD, i.e. Schottky barrier diode are contacted special according to Schottky barrier principle and using metal-semiconductor (M-S)
Property made of device, since the electric current transport of Metals-semiconductor contacts mainly relies on majority carrier (electronics), electronics moved
Shifting rate is high, the region with rectified action formed on boundary, the rectification characteristic with general-purpose diode.
AOD layers, that is, excessive depletion layer is prevented, is usually made of n type material, uses N-type SiC material for AOD layers in the present embodiment
Material.
Schottky contacts when referring to that metal and semiconductor material are in contact, make the band curvature of interface semiconductor
Schottky barrier is formed, the presence of potential barrier results in big interface resistance, thus the schottky junction generated.Constitute schottky junction
Metal and the interface of semiconductor are similar to PN junction, there is similar unilateral conduction, however compared with PN junction, the electricity of schottky junction
Hold very small.
Ohmic contact refers to the pure resistance that metal and semiconductor are formed in contact position, and the resistance is the smaller the better, so that
When component operates, most voltage drop is in behaviour area without in contact surface.The formation condition of Ohmic contact is that semiconductor has height
The impurity of concentration mixes, and so may make it not generate apparent additional impedance, and the balance inside semiconductor will not be made to carry
It flows sub- concentration and significant change occurs.
SiC-TMOS device architecture below in conjunction with embodiment built-in SBD protection structure claimed to the application and
Production method is described in detail.
Embodiment one:
Referring to FIG. 1, the application discloses a kind of SiC-TMOS device 1 of built-in SBD protection structure comprising from bottom to top
The N+ substrate 11 of setting, N- drift layer 12, the SiC-TMOS device 1 further include AOD layer 13 and the first metal layer 16, and the AOD layers
13 are set to the upper surface of N- drift layer 12, contact to form SBD with the first metal layer 16, and the side of AOD layer 13 is equipped with symmetrical
Protection structure (14,15), protection structure (14,15) is used to carry out the SBD of formation pressure-resistant protection, illustrate separately below.
N+ substrate 11, N- drift layer 12 and AOD layer 13 are based on N-type SiC material and adulterate, since three is common
Semiconductor component part, so being no longer described in detail here.
For any one protection structure in protection structure (14,15), include sequence setting the first protective layer, the
Two protective layers and third protective layer.Here illustratively, its structure will be described in detail for protecting structure 14.
With reference to Fig. 2, the first protective layer includes p type island region domain 141, the p type island region domain 141 be primarily used to form Charged Couple and
Electric leakage is reduced when exhausting, and provides the pressure resistance protection of first layer for SBD.Second protective layer includes trench-gate region 143, the groove
Area of grid 143 is primarily used to form Charged Couple and is reducing electric leakage when exhausting, and protects for the SBD pressure resistance for providing the second layer
Shield.Third protective layer includes P+ shielded layer 145, which is mainly used for Charged Couple and reduces electric leakage when exhausting,
The pressure resistance protection of third layer is provided for SBD, so that protection structure 14 can provide pressure-resistant protection for SiC-TMOS device, with
The less leakage current for flowing through AOD layer 13.
Further, it is seen that Fig. 2, p type island region domain 141 include ecto-entad on P base 1411 and P base 1411 side by side
N+ doped region 1412, the P+ doped region 1413 of setting.It should be noted that wherein, P base 1411 is mainly used for carrying out Charged Couple
To provide pressure-resistant protection for SBD.
Further, it is seen that Fig. 2, the trench-gate region 143 in the second protective layer extend to the top of SiC-TMOS device
End, p type island region domain 141 are set to the outside in trench-gate region 143, the P base 1411 and N+ doped region 1412 in p type island region domain 141 with
Trench-gate region 143 contacts, and the P+ shielded layer 145 in third protective layer is set to the lower surface in trench-gate region 143.
It should be noted that the blind zone P+ 145 is avoided to extend to N- drift layer 12, i.e. P+ shielded layer 145 and N- drift layer
Between there are also AOD layers certain thickness.The depth in trench-gate region 143 should be greater than the thickness of P base 141, so that trench gate
Polar region domain 143 has side wall part that can want to contact with AOD layer 13.
Further, it is seen that Fig. 2, the side wall in trench-gate region 143 are equipped with oxide layer 1431, are equipped within side wall more
Crystal silicon layer 1432.In a specific implementation, oxide layer 1431 is by SiO2Material is constituted, and polysilicon layer 1432 is by p-type SiC material structure
At.
Further, it is seen that Fig. 1 and Fig. 2, the first metal layer 16 are set to the top of SiC-TMOS device 1, and AOD layer 13 passes through
The intermediate region of symmetrical protection structure (14,15) extends to the first metal layer 16, respectively with P+ shielded layer 145, groove
Area of grid 143, p type island region domain 141 one or more sides be in contact.
Further, it is seen that Fig. 1, the first metal layer 16 covers the upper surface in p type island region domain 141, with N+ doped region 1412, P+
Doped region 1413 is in contact, and P+ doped region 1413 is for being isolated N+ doped region 1412 and AOD layer 13, N+ doped region 1412
It is mainly used for the source electrode of SiC-TMOS device 1.
Further, it is seen that the lower surface of Fig. 1, N+ substrate 11 is equipped with the second metal, and 17, second metal layer 17 and N+ substrate
11 contacts form Ohmic contact, which is used to form the drain electrode of SiC-TMOS device 1.
Further, the side wall in protection structure 14 and the protection respective trench-gate region of structure 15 is equipped with oxide layer,
Polysilicon layer is equipped within side wall, the grid of SiC-TMOS device 1 is collectively formed in these polysilicon layers.
Embodiment two:
Referring to FIG. 3, for SiC-TMOS device 1 disclosed in above-described embodiment, a kind of SiC- is also disclosed in the application
The production method of TMOS device comprising step S210-S230 illustrates separately below.
Step S210, it is seen that N+ substrate 11 is arranged in Fig. 5, and N- drift is made in 11 upper surface of N+ substrate using epitaxy technique
Layer 12.
Step S220 is epitaxially formed AOD layer 13 on N- drift layer 12.
Step S220 is epitaxially formed AOD layer 13 on N- drift layer 12.
It should be noted that the N+ substrate 11, N- drift layer 12 and AOD layer 13 are based on N-type SiC material and adulterate.
Step S230 is constructed using doping process, etch process, oxidation technology and depositing operation in the side of AOD layer 13
Symmetrical protection structure (14,15), the protection structure of formation protect structure (14,15) to be mainly used for pair with specific reference to Fig. 5
SiC-TMOS device carries out pressure-resistant protection.
It should be noted that doping process, etch process, oxidation technology and depositing operation here is partly leading for maturation
Body manufacturing technology belongs to the prior art, therefore does not carry out expansion explanation to those techniques here.
In one embodiment, step S230 may include step S231-S236, be respectively described below.
Step S231, can refer to Fig. 5 and Fig. 6, the material that injecting p-type is adulterated on the side of AOD layer 13, form default width
The P base (1411,1511) of degree and thickness.
It should be noted that the width and thickness of P base (1411,1511) can be according to the reality of SiC-TMOS device in Fig. 6
Border size and set, should to retain AOD layers of extension channel between P base 1411 and P base 1511, should also make P base 1411
With P base 1511 close to the upside of AOD layer 13.
Step S232, can refer to Fig. 6 and Fig. 7, lose downwards from top (i.e. the top of P base in Fig. 6) edge of AOD layer 13
It carves, is formed groove (142,152), so that the width of groove (142,152) is less than the width of P base (1411,1511) in Fig. 6, with
And make the depth of groove (142,152) greater than the thickness of P base (1411,1511) in Fig. 6.
Step S233, can refer to Fig. 7 and Fig. 8, and the bottom of the groove (142,152) in Fig. 7 is adulterated to form P+ shielded layer
(145,155), and P+ shielded layer (145,155) is avoided to contact with N- drift layer 12.
Step S234, can refer to Fig. 8 and Fig. 9, is doped to the P base (1411,1511) in Fig. 8 and annealing forms p-type
Region (141,151).
In one embodiment, see Fig. 9, the lower layer in p type island region domain 141 is P base 1411, upper layer be ecto-entad side by side
N+ doped region 1412, P+ doped region 1413；The lower layer in p type island region domain 151 is P base 1511, and upper layer is that the N+ of ecto-entad side by side mixes
Miscellaneous area 1512, P+ doped region 1513.
Step S235, can refer to Fig. 9 and Figure 10, carries out oxidation growth to the groove (142,152) in Fig. 9 and polysilicon is heavy
Product forms the trench-gate region (143,153) in Figure 10, wherein trench-gate region 143 includes the oxide layer on side wall
1431 and side wall within polysilicon layer 1432, trench-gate region 153 include side wall on oxide layer 1531 and side wall within
Polysilicon layer 1532.
It should be noted that at this point, AOD layer 13 is extended through the intermediate region of symmetrical protection structure (14,15)
To the SiC-TMOS device 1 top, respectively with P+ shielded layer (145,155), trench-gate region (143,153), p type island region
One or more sides in domain (141,151) are in contact.
Step S236, can refer to Figure 10 and Fig. 1, accumulate the first metal layer 16, the first gold medal at the top of SiC-TMOS device 1
Belong to the N+ doped region and P+ doped region in the covering of layer 16 p type island region domain (143,153), and covering extends to SiC-TMOS device
The AOD layer 13 on top, the first metal layer 16 are contacted with AOD layer 13 to be formed SBD (i.e. Schottky contacts), and P+ doped region 1413 is used
It is isolated in N+ doped region 1412 and AOD layer 13, P+ doped region 1513 is used to carry out N+ doped region 1512 and AOD layer 13
Isolation, N+ doped region (1412,1512) are used to form the source electrode of SiC-TMOS device.
In addition, accumulating second metal layer 17 in the lower surface of N+ substrate 11, second metal layer 17 is in contact with N+ substrate 11
Ohmic contact is formed, second metal layer 17 forms the drain electrode of SiC-TMOS device 1.Also, trench-gate region (143,153)
Polysilicon layer shape (1432,1532) is at the grid of SiC-TMOS device 1.
Built-in the protection structure of SiC-TMOS device 1 (14,15) S231-S236 through the above steps.In a first aspect, P
Type region 141 constitutes the first protective layer of protection structure 14, and p type island region domain 151 constitutes the first protective layer of protection structure 15, those
First protective layer is used to form Charged Couple and reduces electric leakage when exhausting, and provides the pressure resistance guarantor of first layer for the SBD of formation
Shield.Second aspect, trench-gate region 143 constitute the second protective layer of protection structure 14, and trench-gate region 153 constitutes protection
Second protective layer of structure 15, those second protective layers are used to form Charged Couple and reduce electric leakage when exhausting, to be formed
SBD provide the second layer pressure resistance protection.The third aspect, P+ shielded layer 145 constitute the third protective layer of protection structure 14, P+ screen
The third protective layer that layer 155 constitutes protection structure 15 is covered, those third protective layers are used to form Charged Couple and when exhausting
Electric leakage is reduced, provides the pressure resistance protection of third layer for the SBD of formation.
According to the SiC-TMOS device 1 constructed in Fig. 1, when adding positive grid voltage on grid and source electrode, the working principle of device
As follows: the positive voltage of grid pushes the hole in P base open, and sub- electronics less is attracted to the surface of the blind zone P+ below grid；
When positive grid voltage is greater than threshold voltage, the blind zone P+ sheet electron concentration is more than hole concentration, and the blind zone P+ becomes N-type and partly leads
Body, forms N-type longitudinal direction communication channel, and electronics is flowed to through channel from source electrode and drained.
It will be understood by those skilled in the art that all or part of function of various methods can pass through in above embodiment
The mode of hardware is realized, can also be realized by way of computer program.When function all or part of in above embodiment
When being realized by way of computer program, which be can be stored in a computer readable storage medium, and storage medium can
To include: read-only memory, random access memory, disk, CD, hard disk etc., it is above-mentioned to realize which is executed by computer
Function.For example, program is stored in the memory of equipment, when executing program in memory by processor, can be realized
State all or part of function.In addition, when function all or part of in above embodiment is realized by way of computer program
When, which also can store in storage mediums such as server, another computer, disk, CD, flash disk or mobile hard disks
In, through downloading or copying and saving into the memory of local device, or version updating is carried out to the system of local device, when logical
When crossing the program in processor execution memory, all or part of function in above embodiment can be realized.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (10)
1. a kind of SiC-TMOS device of built-in SBD protection structure comprising the N+ substrate that is arranged from bottom to top, N- drift layer,
It is characterized in that, further including AOD layers and the first metal layer；
Described AOD layers is set to the upper surface of the N- drift layer, contacts to form SBD with the first metal layer, described AOD layers
Side is equipped with symmetrical protection structure, and the protection structure is used to carry out the SBD pressure-resistant protection.
2. SiC-TMOS device as described in claim 1, which is characterized in that the protection structure includes the first of sequence setting
Protective layer, the second protective layer and third protective layer；
First protective layer includes p type island region domain, is used to form Charged Couple and reduces electric leakage when exhausting, mentions for the SBD
For the pressure resistance protection of first layer；
Second protective layer includes trench-gate region, is used to form Charged Couple and is reducing electric leakage when exhausting, for institute
It states SBD and the pressure resistance protection of the second layer is provided；
The third protective layer includes P+ shielded layer, is used to form Charged Couple and reduces electric leakage when exhausting, mentions for the SBD
For the pressure resistance protection of third layer.
3. SiC-TMOS device as claimed in claim 2, which is characterized in that the p type island region domain includes on P base and P base
The arranged side by side N+ doped region of ecto-entad, P+ doped region, the P base is used to provide pressure-resistant protection for the SBD.
4. SiC-TMOS device as claimed in claim 3, which is characterized in that
Trench-gate region in second protective layer extends to the top of the SiC-TMOS device, and the p type island region domain is set
The P base and the N+ doped region and the trench gate polar region in the outside in the trench-gate region, the p type island region domain
Domain contacts, and the P+ shielded layer in the third protective layer is set to the lower surface in the trench-gate region；
The first metal layer is set to the top of the SiC-TMOS device, and described AOD layers passes through the symmetrical protection
The intermediate region of structure extends to the first metal layer, described AOD layers respectively with the P+ shielded layer, the trench gate polar region
Domain, the p type island region domain one or more sides be in contact.
5. SiC-TMOS device as claimed in claim 4, which is characterized in that
The first metal layer covers the upper surface in the p type island region domain, is in contact with the N+ doped region, the P+ doped region,
For the N+ doped region and described AOD layers to be isolated, the N+ doped region is used to form described the P+ doped region
The source electrode of SiC-TMOS device；
The lower surface of the N+ substrate is equipped with second metal layer, and the second metal layer is contacted with the N+ substrate to be formed ohm and connect
Touching, the second metal layer are used to form the drain electrode of the SiC-TMOS device；
The side wall in the trench-gate region is equipped with oxide layer, is equipped with polysilicon layer within side wall, the polysilicon layer is used for
Form the grid of the SiC-TMOS device.
6. a kind of production method of SiC-TMOS device, which comprises the following steps:
N+ substrate is set, N- drift layer is made in the N+ upper surface of substrate using epitaxy technique；
AOD layers are epitaxially formed on the N- drift layer；
Using doping process, etch process, oxidation technology and depositing operation, constructed in AOD layers of the side symmetrical
Structure is protected, the protection structure is used to carry out the SiC-TMOS device pressure-resistant protection.
7. production method as claimed in claim 6, which is characterized in that described using doping process, etch process, oxidation work
Skill and depositing operation construct symmetrical protection structure in AOD layers of the side, comprising:
The material that injecting p-type is adulterated on AOD layers of the side forms the P base of predetermined width and thickness；
It is etched downwards from described AOD layers of top edge, forms groove, so that the width of the groove is less than the P base
Width, and the thickness for making the depth of the groove be greater than the P base；
It adulterates to form P+ shielded layer in the bottom of the groove, and the P+ shielded layer is avoided to contact with the N- drift layer；
The P base is doped and annealing forms p type island region domain, the lower layer in the p type island region domain is P base, and upper layer is ecto-entad
N+ doped region, P+ doped region side by side；
Oxidation growth and polysilicon deposition are carried out to the groove, form trench-gate region, the trench-gate region includes
The polysilicon layer within oxide layer and side wall on side wall.
8. production method as claimed in claim 7, which is characterized in that described AOD layers passes through the symmetrical protection
The intermediate region of structure extends to the top of the SiC-TMOS device, respectively with the P+ shielded layer, the trench gate polar region
Domain, the p type island region domain one or more sides be in contact.
9. production method as claimed in claim 8, which is characterized in that further comprising the steps of:
The first metal layer is accumulated on the top of the SiC-TMOS device, the first metal layer covers the N in the p type island region domain
+ doped region and P+ doped region, and covering extend to the AOD layer on the top of the SiC-TMOS device, the first metal layer
It is contacted with described AOD layers to form SBD, the P+ doped region is for being isolated the N+ doped region and described AOD layers, institute
State the source electrode that N+ doped region is used to form the SiC-TMOS device；
Second metal layer is accumulated in the lower surface of the N+ substrate, the second metal layer is in contact to be formed with the N+ substrate
Ohmic contact, the second metal layer are used to form the drain electrode of the SiC-TMOS device；
The polysilicon layer in the trench-gate region is used to form the grid of the SiC-TMOS device.
10. production method as claimed in claim 9, which is characterized in that
The p type island region domain constitutes the first protective layer of the protection structure, is used to form Charged Couple and reduces leakage when exhausting
Electricity provides the pressure resistance protection of first layer for the SBD；
The trench-gate region constitutes the second protective layer of the protection structure, is used to form Charged Couple and when exhausting
Electric leakage is reduced, provides the pressure resistance protection of the second layer for the SBD；
The P+ shielded layer constitutes the third protective layer of the protection structure, is used to form Charged Couple and reduces leakage when exhausting
Electricity provides the pressure resistance protection of third layer for the protection structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110350035A (en) * | 2019-05-30 | 2019-10-18 | 上海功成半导体科技有限公司 | SiC MOSFET power device and preparation method thereof |
| CN113921400A (en) * | 2021-12-09 | 2022-01-11 | 南京华瑞微集成电路有限公司 | Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205881911U (en) * | 2016-07-21 | 2017-01-11 | 北京世纪金光半导体有限公司 | Ditch cell type siC primitive unit cell for MOSFET |
| CN106876485A (en) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof |
-
2018
- 2018-12-07 CN CN201811496829.XA patent/CN109728075A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205881911U (en) * | 2016-07-21 | 2017-01-11 | 北京世纪金光半导体有限公司 | Ditch cell type siC primitive unit cell for MOSFET |
| CN106876485A (en) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| LI, X, ET AL.: "SiC Trench MOSFET With Integrated Self-Assembled Three-Level Protection Schottky Barrier Diode", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110350035A (en) * | 2019-05-30 | 2019-10-18 | 上海功成半导体科技有限公司 | SiC MOSFET power device and preparation method thereof |
| CN113921400A (en) * | 2021-12-09 | 2022-01-11 | 南京华瑞微集成电路有限公司 | Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof |
| CN113921400B (en) * | 2021-12-09 | 2022-03-25 | 南京华瑞微集成电路有限公司 | Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof |
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