CN114335148A

CN114335148A - Preparation method of gallium nitride power transistor with longitudinal structure

Info

Publication number: CN114335148A
Application number: CN202111675551.4A
Authority: CN
Inventors: 刘扬; 黎城朗
Original assignee: Sun Yat Sen University
Current assignee: Sun Yat Sen University
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-12

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a gallium nitride power transistor with a longitudinal structure. By selecting the region epitaxy, the deep-groove p-well shielding layer and the groove structure are formed at the same time, the electric field of the gate oxide layer can be effectively reduced, the problem of device reliability caused by a high-oxide-layer electric field is solved, and the damage of the groove and the interface state defect caused by dry etching are avoided, so that the voltage resistance and the reliability of the device are improved.

Description

Preparation method of gallium nitride power transistor with longitudinal structure

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a gallium nitride power transistor with a longitudinal structure.

Background

Compared with a transverse structure transistor, the longitudinal structure power transistor is mainly subjected to pressure bearing by the drift layer, so that the breakdown voltage can be increased by increasing the thickness of the drift layer, meanwhile, the area of the device is kept unchanged, the wafer utilization rate is increased, and the power density of the device is improved. In addition, the peak electric field is moved from the surface to the interior of the device, so that the current collapse effect is weakened, and the reliability is improved.

In the GaN field effect transistor structure with various longitudinal structures, the groove MOSFET can reduce the leakage under the off-state withstand voltage through the p-type GaN current blocking layer, and reduce the grid leakage through the insulated oxide layer. However, in the conventional trench MOSFET structure, the current blocking layer is planar p-type GaN which is epitaxially grown together with the drift layer, as shown in fig. 1(a), the trench is usually formed by dry etching the epitaxial layer, and the structure and the related process still have some key problems which affect the electrical performance and reliability of the device:

(1) the reliability of the gate dielectric is reduced due to the overlarge electric field of the gate dielectric layer. GaN devices can operate at larger voltages due to the large forbidden bandwidth. When the groove MOSFET is in a larger off-state withstand voltage, a larger electric field exists in the gate dielectric layer. In addition, because the dry etching is difficult to control the etching depth, the bottom of the groove usually extends into the drift layer, and the electric field of the gate dielectric layer is further increased. On the other hand, grooves etched by dry etching may have sharper corners where the smaller radius of curvature causes electric field lines to be concentrated, as shown in fig. 2 (a). Under a larger gate dielectric layer electric field, a large number of interface state defects brought by etching can cause the insulation capability of the gate dielectric layer to be reduced, the grid leakage current is increased, the capture of electrons by defect states is intensified, and the reliability and the voltage resistance of a device are seriously reduced.

(2) The process of ion implantation to form pGaN presents difficulties. In a conventional Si, SiC based device, in order to reduce the large electric field intensity of the gate oxide, a deep pGaN well is usually formed on both sides of the trench by ion implantation to shield the electric field at the gate oxide, as shown in fig. 1(b) and fig. 2 (b). However, because the GaN material has the characteristics of high density, high hardness and the like, the conventional p-type ion implantation process cannot be directly grafted to the GaN longitudinal conduction device. On the other hand, activating the ion-implanted acceptor impurity Mg in GaN requires a high temperature of about 1300 ℃, which causes GaN to decompose at high temperature, resulting in nitrogen vacancies. In addition, the ion implantation also causes certain lattice damage, which degrades the device performance.

(3) The trench sidewall lattice damage introduced by dry etching further degrades channel electron mobility. When the groove MOSFET is started, a current channel is formed by inverting the heavily doped p-type GaN, ionized impurities of the heavily doped p-type GaN are scattered greatly, and the electron mobility of the channel of the groove MOSFET is smaller. The grooves of the conventional grooved MOSFET are usually formed by dry etching, which causes lattice damage on the surface of the groove, increases surface roughness scattering, further reduces the electron mobility of the channel, and further increases the on-resistance of the device.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides the preparation method of the gallium nitride power transistor with the longitudinal structure, which can effectively reduce the electric field of a gate oxide layer, reduce the etching damage and the defects of a groove and improve the pressure resistance and the reliability of a device.

In order to solve the technical problems, the invention adopts the technical scheme that: a method for preparing a gallium nitride power transistor with a longitudinal structure comprises the following steps:

s1, epitaxially growing a device drift region on an n-type conductive substrate through MOCVD;

s2, etching a table top on which a p well needs to grow through ICP;

s3, depositing a mask layer SiO on the drift region of the device through PECVD₂Removing SiO in the region of p-well layer and p-type channel layer₂A mask layer;

s4, growing a p-type GaN region and an N-type GaN region through MOCVD epitaxy, and removing SiO₂A mask layer;

s5, growing a gate dielectric layer on the device formed in the step S4;

s6, exposing the gate dielectric layer at the position of the source electrode area needing to be evaporated through a photoetching development technology, and removing the gate dielectric layer by using a buffer hydrofluoric acid solution;

s7, etching ohmic contact windows of the source electrode and the p-type GaN region through ICP;

s8, evaporating Ni/Au metal on a p-type GaN region of the device by adopting an electron beam evaporation method or a magnetron sputtering method, and forming short-circuit ohmic contact through annealing;

s9, evaporating Ti/Al/Ni/Au metal on an n-type GaN region of the device by adopting an electron beam evaporation method or a magnetron sputtering method, and forming ohmic contact as a source electrode by annealing;

s10, evaporating Ni/Au metal on a groove area of the device by adopting an electron beam evaporation method or a magnetron sputtering method, and forming a gate electrode by annealing;

s11, evaporating Ti/Al/Ni/Au metal on the n-type conductive substrate by adopting an electron beam evaporation method or a magnetron sputtering method, and forming an ohmic contact electrode serving as a drain electrode by annealing.

In one embodiment, the step S2 specifically includes:

s21, coating photoresist on the drift region of the device, and determining a p-well etching region through a photoetching development technology;

s22, etching the area uncovered by the photoresist by ICP with the depth of 0.5-5 μm.

In one embodiment, the step S3 specifically includes:

s31, depositing SiO with the thickness of 0.1-10 mu m on the drift region of the device through PECVD₂A mask layer;

s32, SiO in the position where the p-well region and the channel layer need to be formed₂Opening a window on the mask layer through photoetching;

s33, removing SiO uncovered by the photoresist through buffered hydrofluoric acid₂And the width of the mask layer 3 is 0.05-5 μm.

In one embodiment, the step S4 specifically includes:

s41, depositing p-type GaN with the thickness of 0.1-2 mu m on the drift region of the device through MOCVD;

s42, depositing n-type GaN with the thickness of 0.1-2 mu m on the p-type GaN of the device through MOCVD;

s43, removing SiO through buffered hydrofluoric acid₂A mask layer;

and S44, treating the groove-shaped structure formed by the epitaxy of the selected area in TMAH corrosive liquid at the temperature of 70-100 ℃ for more than 1 hour.

In one embodiment, the n-type conductive substrate is an n-type GaN self-supporting substrate, the resistivity ranges from 0.005 Ω -cm to 0.1 Ω -cm, and the thickness ranges from 100 μm to 500 μm.

In one embodiment, the device drift region is an unintentional doped GaN epitaxial layer, a Si doped epitaxial layer or an As doped epitaxial layer with low dislocation density; the thickness of the drift region of the device is 1-50 μm, and the carrier concentration is 1 × 10¹⁴cm^-3～5×10¹⁷cm^-3。

In one embodiment, the p-type GaN region has magnesium as a p-type dopant and a hole concentration of 1 × 10¹⁷cm^-3～1×10¹⁹cm^-3The thickness is 0.1-5 μm.

In one embodiment, the source region n-type GaN region has an electron concentration of 1 × 10¹⁸cm^-3～3×10¹⁹cm^-3The thickness is 0.1-5 μm.

In one embodiment, the gate dielectric layer is made of Al₂O₃、SiN、SiO₂Any of them, the thickness is 10nm to 100 nm.

In one embodiment, the shorting metal material is one of Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, or a stacked structure thereof.

In one embodiment, the source metal and the drain metal are made of any one of a Ti/Al/Ni/Au alloy, a Ti/Al/Ti/Au alloy, a Ti/Al/Mo/Au alloy, or a Ti/Al/Ti/TiN alloy.

In one embodiment, the material of the gate metal is one of metals Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN, NbN, or a stacked structure thereof.

Compared with the prior art, the beneficial effects are: according to the preparation method of the gallium nitride power transistor with the longitudinal structure, after a deep well is formed through etching, p-type GaN is epitaxially grown in a selective area, and a p-well electric field shielding layer and a p-channel layer are simultaneously prepared. The p-well can effectively reduce the electric field of the gate oxide under reverse bias and relieve the electric field concentration effect at the bottom corner of the oxide layer at the bottom of the groove of the device; the groove structure formed by selective area epitaxy avoids lattice damage and interface defects caused by dry etching, reduces surface roughness scattering, improves the electron mobility of a channel, and is beneficial to improving the voltage endurance and reliability of the GaN groove MOSFET device by reducing the interface state concentration.

Drawings

FIG. 1 is a schematic diagram of three trench MOSFET structures, (a) a conventional trench MOSFET structure; (b) is an ion-implanted double p-well grooved MOSFET; (c) the invention relates to a device structure, in particular to a double p-well groove MOSFET with secondary epitaxy.

FIG. 2 is a schematic diagram of simulated electric field distributions of three trench MOSFET structures, (a) a conventional trench MOSFET structure; (b) is an ion injection type double p-well groove MOSFET; (c) the invention relates to a device structure, in particular to a double p-well groove MOSFET with secondary epitaxy.

Fig. 3 to 10 are schematic views of device process flows of embodiment 2 of the present invention, wherein fig. 10 is a schematic view of an overall structure of the device prepared in embodiment 2.

Fig. 11 to 16 are process flow diagrams of a device of embodiment 3 of the present invention, wherein fig. 16 is a schematic view showing the overall structure of the device prepared in embodiment 3.

Reference numerals: 1. a substrate; 2. a device drift region; 3. a mask layer; 4. a p-type GaN region; 5. a source region n-type GaN region; 6. a gate dielectric layer; 7. short-circuit metal; 8. a source metal; 9. a gate metal; 10. A drain metal; 11. and a passivation layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The invention is described below in one of its embodiments with reference to specific embodiments. Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

In the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", etc. based on the orientation or positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms may be understood by those skilled in the art according to specific circumstances. In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout is to include three juxtapositions, exemplified by "A and/or B" including either scheme A, or scheme B, or a scheme in which both A and B are satisfied.

Example 1:

the present embodiment provides a vertical structure gan power transistor, as shown in fig. 10, which is a schematic structural diagram of the device of the present embodiment, and the structure thereof sequentially includes, from bottom to top: a drain metal 10 overlying the device; a GaN free-standing substrate 1; n-type low carrier concentration region-device drift region 2; a p-type GaN region 4; a source region heavily doped n-type GaN region 5; a gate dielectric layer 6; a source metal 7 forming an ohmic contact with the p-type GaN; a source electrode 8 forming ohmic contact with the source region n-type GaN; a gate metal 9 overlying the recessed gate dielectric.

Example 2

As shown in fig. 3 to 10, a method for manufacturing a vertical structure gan power transistor includes the following steps:

step 1.1 formation of epitaxial Structure

The n-type conductive device drift region 2 is epitaxially grown on an n-type conductive GaN free-standing substrate 1 by MOCVD, and the epitaxial structure of the material after completion of this step is shown in fig. 3.

Step 1.2 etch to form deep well

S21, coating photoresist on the drift region 2 of the n-type conductive device, and exposing a region to be etched after exposure and development;

s22, etching the area which is not covered by the photoresist through ICP;

s23, removing the photoresist by using acetone, wherein the structure of the finished device is shown in FIG. 4.

Step 1.3 preparation of mask layer 3

S31, depositing SiO on the drift region 2 of the device₂As a mask layer 3;

s32, in SiO₂Coating photoresist on the mask layer 3, exposing and developing to expose the position of the p-type GaN region 4 needing epitaxial growth;

and S33, selectively etching the mask layer 3 which is not covered by the photoresist by using a buffer hydrofluoric acid solution, wherein the structure of the finished device is shown in FIG. 5.

Step 1.4 selective area epitaxial growth of p-type GaN region 4 and source region n-type GaN region 5

S41, placing the device prepared in the step 1.3 into an MOCVD chamber to epitaxially grow a p-type GaN region 4 and a source region n-type GaN region 5 to form the p-type GaN region 4 and the source region n-type GaN region 5;

s42, removing SiO by using buffer hydrofluoric acid solution₂ A mask layer 3;

s43, using TMAH hot solution to process the device, and activating an acceptor impurity Mg in a high-temperature annealing mode, wherein the structure of the completed device is shown in FIG. 6.

Step 1.5, depositing a gate dielectric layer 6;

s51, placing the device prepared in the step 1.4 into an ALD (atomic layer deposition) chamber to deposit a gate dielectric layer 6; the completed structure is shown in FIG. 7

Step 1.6, removing part of the gate dielectric layer 6;

s61, coating photoresist on the gate dielectric layer 6, exposing and developing to expose an area where the gate dielectric layer 6 needs to be removed;

s62, selectively etching the dielectric layer 6 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;

s63, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 8.

Step 1.7 etching out pGaN short-circuit window

S71, coating photoresist, exposing the p-type GaN region 4 to be removed after exposure and development;

s72, etching the area which is not covered by the photoresist through ICP;

s23, removing the photoresist by using acetone, and obtaining the finished device structure as shown in FIG. 9.

Step 1.8 Evaporation of electrodes

S81, evaporating Ni/Au on the p-type GaN region 4 exposed by the device prepared in the step S1.7 to form ohmic contact, wherein the ohmic contact is used as pGaN short-circuit metal 7;

s82, evaporating Ti/Al/Ni/Au on the n-type GaN region 5 and the short-circuit metal 7 to form ohmic contact serving as a source electrode 8;

s83, evaporating Ni/Au on the gate dielectric layer 6 of the groove of the device to form a gate electrode 9;

s84, evaporating Ti/Al/Ni/Au on the back surface of the epitaxial wafer to form ohmic contact to be used as a drain electrode 10;

s85, the process flow of the embodiment 1 is completed, and the final device structure is shown in FIG. 10.

Example 3

The final device structure of this embodiment is as shown in fig. 16, and the difference is that in embodiment 2, the gate dielectric layer 6 is directly deposited after the p-type GaN region 4 and the source region n-type GaN region 5 are epitaxially grown in the selected region, while in this embodiment, part of the p-type GaN region 4 and the source region n-type GaN region 5 are etched after the selected region is epitaxially grown, so as to form a window of the source short pGaN, and then the passivation layer 11 is deposited to reduce punch-through leakage caused by the possibly low sidewall p-type GaN doping concentration. In this embodiment, after the selective area epitaxial growth of the p-type GaN region 4 and the source region n-type GaN region 5 is completed and the mask 3 is removed in embodiment 1, the following process flow is performed:

step 2.1 etching to form source electrode short circuit pGaN window

S11, coating photoresist on the device after the selective area epitaxial growth of the p-type GaN region 4 and the source area n-type GaN region 5 is completed in the embodiment 1, exposing the p-type GaN region 4 and the n-type GaN region 5 to be removed after exposure and development;

s12, etching the area which is not covered by the photoresist through ICP;

s13, removing the photoresist by using acetone;

s14, using TMAH hot solution to process the device, and activating an acceptor impurity Mg in a high-temperature annealing mode, wherein the structure of the completed device is shown in FIG. 11.

Step 2.2 passivation layer 11 deposition

S21, depositing SiO through PECVD₂Or Si₃N₄As a passivation layer 11, the completed device structure is shown in fig. 12.

Step 2.3 removing part of the passivation layer 11

S31, coating photoresist on the passivation layer 11, exposing and developing to expose an area where the passivation layer 11 needs to be removed;

s32, selectively etching the passivation layer 11 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;

and S33, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 13.

Step 2.4 deposition of Gate dielectric layer 6

S41, depositing a gate dielectric layer 6 through ALD, wherein the structure of the finished device is shown in FIG. 14.

Step 2.5, part of the passivation layer 11 and the gate dielectric layer 6 are removed

S51, coating photoresist on the gate dielectric layer 6, exposing and developing to expose the regions of the gate dielectric layer 6 and the passivation layer 11 to be removed;

s52, selectively etching the gate dielectric layer 6 and the passivation layer 11 which are not covered by the photoresist by using a buffer hydrofluoric acid solution;

and S53, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 15.

Step 2.6 Evaporation of electrodes

S61, evaporating Ni/Au on the exposed pGaN of the device prepared in the step S2.5 to form ohmic contact to serve as pGaN short-circuit metal 7;

s62, evaporating Ti/Al/Ni/Au on the n-type GaN region 5 and the short-circuit metal 7 to form ohmic contact serving as a source electrode 8;

s63, evaporating Ni/Au on the gate dielectric layer 6 of the groove of the device to form a gate electrode 9;

s64, evaporating Ti/Al/Ni/Au on the back surface of the epitaxial wafer to form ohmic contact to serve as a drain electrode 10;

s65, the process flow of the embodiment 2 is completed, and the final device structure is shown in FIG. 16.

It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A preparation method of a gallium nitride power transistor with a longitudinal structure is characterized by comprising the following steps:

s1, epitaxially growing a device drift region (2) on an n-type conductive substrate (1) through MOCVD;

s2, etching a table top on which a p well needs to grow through ICP;

s3, depositing a mask layer (3) SiO on the drift region (2) of the device through PECVD₂Removing SiO in the region of p-well layer and p-type channel layer₂A mask layer (3);

s4, growing a p-type GaN region (4) and an N-type GaN region (5) through MOCVD epitaxy, and removing SiO₂A mask layer (3);

s5, growing a gate dielectric layer (6) on the device formed in the step S4;

s6, exposing the gate dielectric layer (6) at the position of the source electrode area needing to be evaporated through a photoetching development technology, and removing the gate dielectric layer (6) by using a buffer hydrofluoric acid solution;

s7, etching ohmic contact windows of the source electrode and the p-type GaN region (4) through ICP;

s8, evaporating Ni/Au metal on the p-type GaN region (4) of the device by adopting an electron beam evaporation method or a magnetron sputtering method, and forming a short-circuit ohmic contact (7) by annealing;

s9, evaporating Ti/Al/Ni/Au metal on the n-type GaN region (5) of the device by adopting an electron beam evaporation method or a magnetron sputtering method, and forming ohmic contact as a source electrode (8) by annealing;

s10, evaporating Ni/Au metal on a groove region of the device by adopting an electron beam evaporation method or a magnetron sputtering method, and forming a gate electrode (9) by annealing;

s11, evaporating Ti/Al/Ni/Au metal on the n-type conductive substrate (1) by adopting an electron beam evaporation method or a magnetron sputtering method, and forming an ohmic contact electrode serving as a drain electrode (10) by annealing.

2. The method for manufacturing a vertical structure gan power transistor according to claim 1, wherein the step S2 specifically includes:

s21, coating photoresist on the drift region (2) of the device, and determining a p-well etching region through a photoetching development technology;

3. The method for manufacturing a vertical structure gan power transistor according to claim 1, wherein the step S3 specifically includes:

s31, depositing SiO with the thickness of 0.1-10 mu m on the drift region (2) of the device through PECVD₂A mask layer (3);

s32, SiO in the position where the p-well region and the channel layer need to be formed₂Opening a window on the mask layer (3) by photoetching;

s33, removing SiO uncovered by the photoresist through buffered hydrofluoric acid₂And the mask layer (3), wherein the width of the mask layer (3) is 0.05-5 μm.

4. The method for manufacturing a vertical structure gan power transistor according to claim 1, wherein the step S4 specifically includes:

s41, depositing 0.1-2 mu m p-type GaN (4) on the device drift region (2) through MOCVD;

s42, depositing n-type GaN (5) with the thickness of 0.1-2 microns on the p-type GaN (4) of the device through MOCVD;

s43, removing SiO through buffered hydrofluoric acid₂A mask layer (3);

5. The method for manufacturing a vertical structure GaN power transistor according to any of claims 1 to 4, wherein the n-type conductive substrate (1) is an n-type GaN self-supporting substrate, has a resistivity in the range of 0.005 Ω -cm to 0.1 Ω -cm, and has a thickness of 100 μm to 500 μm.

6. The method for manufacturing a vertical structure GaN power transistor according to any of claims 1 to 4, wherein the device drift region (2) is an unintentionally doped GaN epitaxial layer, a Si doped epitaxial layer or an As doped epitaxial layer with low dislocation density; the thickness of the drift region (2) of the device is 1-50 μm, and the carrier concentration is 1 x 10¹⁴cm^-3～5×10¹⁷cm^-3。

7. The method for fabricating a vertical structure GaN power transistor according to any of claims 1-4, wherein the p-type GaN region (4), the p-type dopant is magnesium, and the hole concentration is 1 x 10¹⁷cm^-3～1×10¹⁹cm^-3The thickness is 0.1-5 μm.

8. Method for fabricating a vertical structure GaN power transistor according to any of claims 1 to 4 wherein the source n-type GaN region (5) has an electron concentration of 1 x 10¹⁸cm^-3～3×10¹⁹cm^-3The thickness is 0.1-5 μm.

9. The method for preparing a vertical structure GaN power transistor according to any of claims 1-4, wherein the gate dielectric layer (6) is made of Al₂O₃、SiN、SiO₂Any of them, the thickness is 10nm to 100 nm.

10. The method for preparing a vertical structure GaN power transistor according to any of claims 1-4, wherein the shorting metal (7) is one of Ni, Au, Pt, Pd, Ir, Mo, Al, Ti or a stacked structure thereof; the source electrode metal (8) and the drain electrode metal (10) are made of any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the gate metal (9) is made of one of metal Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN and NbN or a stacked structure thereof.