CN116130523A - PIN junction vertical diode and preparation method thereof - Google Patents
PIN junction vertical diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000004381 surface treatment Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 229910002601 GaN Inorganic materials 0.000 description 82
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
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- 238000010586 diagram Methods 0.000 description 5
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- 229910052757 nitrogen Inorganic materials 0.000 description 3
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
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- 241001391944 Commicarpus scandens Species 0.000 description 1
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- 238000012360 testing method Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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Abstract
A PIN junction vertical diode and a preparation method thereof comprise a substrate, a GaN layer, an AlGaN layer, a cathode electrode, a P-GaN layer and an anode electrode; the PIN junction vertical diode includes 2 structures, one is that a cathode electrode is disposed inside and an anode electrode is disposed outside, and the other is that a cathode electrode is disposed outside and an anode electrode is disposed inside. The PIN junction vertical diode based on the P-GaN/AlGaN/GaN epitaxial structure has the advantages that the P-GaN layer is used as a P-type port, the two-weft electron gas generated at the interface of the AlGaN layer/GaN layer is used as an N-type port, the AlGaN layer is used as an i layer, then the cathode electrode is used for forming N-type ohmic contact with the two-weft electron gas on the heterojunction of the AlGaN layer/GaN layer by using a process, and the anode electrode is used for forming P-type ohmic contact on the P-GaN layer, so that the PIN junction vertical diode has higher reverse breakdown capability, is simple in preparation method and wide in application prospect.
Description
Technical Field
The invention belongs to the technical field of gallium nitride power devices, and particularly relates to a PIN junction vertical diode and a preparation method thereof.
Background
GaN materials have excellent electrical characteristics such as a large forbidden band width (3.4 eV), high breakdown field strength (3.3 MV/cm), and high electron mobility (600 cm 2/(V.s)). In future power systems, gaN diodes have great application prospects, and can be applied to power devices such as boost converters, half-bridge inverters, buck-boost converters, power factor correction circuits, and the like.
Conventional GaN diodes are usually fabricated with schottky junctions between metal/2 DEG, which, although having the advantage of simple fabrication and high current, remain planar devices, and the directional withstand voltage is mainly applied to the schottky junctions, resulting in the schottky junctions being easily broken down and having a relatively weak reverse withstand voltage capability, which is a great risk in applications.
For example, chinese patent application No. CN201510715065.9 discloses a longitudinally conducting GaN-based trench junction barrier schottky diode and a method for fabricating the same, comprising, in order from bottom to top, an ohmic contact metal cathode covering the bottom surface of a substrate; an n-type heavily doped GaN self-supporting substrate; a first epitaxial layer: an n-type lightly doped GaN layer-an electron drift layer; a second epitaxial layer: n-type lightly doped GaN table-n-type vertical channel layer (groove structure is formed between tables); third epitaxial layer: a p-type GaN layer in the trench; an ohmic contact anode alloy layer A covering the top of the p-GaN layer; a Schottky contact anode metal layer B covering the top of the n-GaN table; a device isolation layer; and a surface passivation layer.
Therefore, the invention aims to develop a PIN junction vertical diode and a preparation method thereof, and improve the reverse breakdown capability of the diode.
Disclosure of Invention
The invention aims to: in order to overcome the defects, the invention aims to provide a PIN junction vertical diode and a preparation method thereof, which are based on a P-GaN/AlGaN/GaN epitaxial structure, wherein a P-GaN layer is used as a P-type port, two-weft electron gas generated at an AlGaN layer/GaN layer interface is used as an N-type port, an AlGaN layer is used as an i layer, then a cathode electrode is used for forming N-type ohmic contact with the two-weft electron gas on an AlGaN layer/GaN layer heterojunction by using a process, and an anode electrode is used for forming P-type ohmic contact on the P-GaN layer, so that the PIN junction vertical diode has higher reverse breakdown capability, and is simple in preparation method and wide in application prospect.
The invention aims at realizing the following technical scheme:
a PIN junction vertical diode comprises a substrate, a GaN layer, an AlGaN layer, a cathode electrode, a P-GaN layer and an anode electrode; the PIN junction vertical diode comprises 2 structures, wherein one structure is that a cathode electrode is arranged inside and an anode electrode is arranged outside, and the other structure is that the cathode electrode is arranged outside and the anode electrode is arranged inside; two weft electron gases exist between the GaN layer and the AlGaN layer, the cathode electrode forms N-type ohmic contact with the two weft electron gases on the heterojunction of the AlGaN layer/the GaN layer, and the anode electrode forms P-type ohmic contact on the P-GaN layer.
The PIN junction vertical diode is based on a P-GaN/AlGaN/GaN epitaxial structure, a P-GaN layer is used as a P-type port, two-dimensional electron gas (two-dimensional electron gas which can generate high concentration and high electron mobility due to voltage polarization and spontaneous polarization effect in an AlGaN/GaN heterostructure) generated at the interface of the AlGaN layer/GaN layer is used as an N-type port, an AlGaN layer is used as an i-layer, then a cathode electrode is used for forming N-type ohmic contact with the two-dimensional electron gas on the AlGaN layer/GaN layer heterojunction, an anode electrode is used for forming P-type ohmic contact on the P-GaN, compared with the diode on GaN in the prior art, a Schottky junction generated between metal/two-dimensional electron gas is usually adopted for manufacturing, the Schottky junction is easy to break down and has weak reverse withstand voltage capability, the risk in application is high, and due to the fact that GaN belongs to a wide-band semiconductor and has a higher critical electric field, the PIN junction diode manufactured by the GaN has higher reverse breakdown capability, particularly has a drift region between the P-band semiconductor and the cathode (N-type ohmic contact) and the drift region can be further increased.
In addition, the turn-on voltage of the vertical diode of the PIN junction determines the turn-on voltage of the PIN junction, which is generally greater than 1V, when an electrode in ohmic contact with the P-GaN layer gives positive pressure, the potential barrier of the AlGaN layer is reduced, holes in the P-GaN layer diffuse into two-weft electron gas of the GaN layer/AlGaN interface, and electrons in the two-weft electron gas diffuse into the P-GaN layer to form channel current.
Further, the PIN junction vertical diode comprises a substrate, a GaN layer, an AlGaN layer, a P-GaN layer and an anode electrode from bottom to top, wherein the cathode electrode is arranged on the GaN layer and is positioned outside the GaN layer.
Further, the PIN junction vertical diode comprises a substrate, a GaN layer, an AlGaN layer and a cathode electrode from bottom to top, wherein the P-GaN layer is arranged on the AlGaN layer and is positioned on the outer side of the cathode electrode, and the anode electrode is arranged on the P-GaN layer.
Further, in the PIN junction vertical diode, the substrate is silicon or sapphire, and the thickness of the substrate is 0-1000 μm.
Furthermore, in the PIN junction vertical diode, the P-GaN layer is doped with magnesium ions, wherein the doping amount of the magnesium ions is larger than 1e 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the P-GaN layer is 50-100nm.
Furthermore, in the PIN junction vertical diode, the cathode electrode adopts low work function metal, and the thickness of the cathode electrode is 20-300nm; the anode electrode adopts high work function metal, and the thickness of the anode electrode is 20-200nm.
Preferably, the cathode electrode employs a low work function metal, such as Ti, al, etc.; the anode electrode employs a high work function metal, such as Ni, au, pt, pd, ir, W and the like.
The invention also relates to a preparation method of the PIN junction vertical diode, which comprises the following steps:
s1: etching all AlGaN layer/P-GaN layer areas except the active area;
s2: etching the cathode region of the P-GaN layer;
s3: carrying out surface treatment on the AlGaN layer/P-GaN layer etching area by adopting a surface treatment liquid; then adopting an electron beam evaporation or magnetron sputtering method to deposit low work function metal on the surface of the AlGaN layer to prepare a cathode electrode, and adopting rapid thermal annealing equipment to anneal for 10-60s in inert gas at 500-1000 ℃ so that the cathode electrode and the two-weft electron gas form N-type ohmic contact;
s4, carrying out surface treatment on the etching area of the P-GaN layer by adopting a surface treatment liquid; then adopting an electron beam evaporation or magnetron sputtering method to deposit high work function metal on the surface of the P-GaN layer to prepare an anode electrode, and adopting a rapid thermal annealing device to anneal for 10-600s in gas at 500-1000 ℃ so that the anode electrode and the P-GaN layer form P-type ohmic contact.
Preferably, the etching in S1 and S2 is performed by ICP or RIE, and the etching in S3 and S4 is performed byThe surface treatment liquid adopts TMAH solution, the inert gas of S3 adopts nitrogen or argon, the cathode electrode of S3 and the two-weft electron gas form N-type ohmic contact, and the gas of S4 adopts oxygen or BCl 3 、Cl 2 Ar mixture or BCl 3 、SF 6 Mixed gas or Cl 2 、BCl 3 、O 2 And (3) mixing the gases, and forming P-type ohmic contact between the anode electrode of the S4 and the P-GaN layer.
Further, in the above method for manufacturing a PIN junction vertical diode, the etching of S1 specifically includes the following steps:
(1) Photoetching a region needing etching of the AlGaN layer/P-GaN layer region by adopting a photoetching technology, and taking photoresist as a mask;
(2) By BCl 3 、Cl 2 Ar mixture or BCl 3 、SF 6 Mixed gas or Cl 2 、N 2 、O 2 Dry etching is carried out on the etching area by mixed gas, the adopted equipment is ICP or RIE, and the etching depth is more than 90 nm;
(3) And (5) removing the photoresist by adopting organic cleaning.
Further, in the above method for manufacturing a PIN junction vertical diode, the etching of S2 specifically includes the following steps:
(1) Photoetching a region needing etching of the P-GaN layer region by adopting a photoetching technology, and taking photoresist as a mask;
(2) By BCl 3 、Cl 2 Ar mixture or BCl 3 、SF 6 Mixed gas or Cl 2 、N 2 、O 2 Performing Cl-based dry etching on the etching area by mixed gas, wherein the adopted equipment is ICP or RIE, and the etching depth is 30-90nm or the P-GaN layer is completely removed;
(3) And (5) removing the photoresist by adopting organic cleaning.
Compared with the prior art, the invention has the following beneficial effects:
(1) The PIN junction vertical diode disclosed by the invention is a PIN junction vertical diode based on a P-GaN/AlGaN/GaN epitaxial structure, wherein a P-GaN layer is used as a P-type port, two weft electron gases generated at the interface of an AlGaN layer/GaN layer are used as N-type ports, an AlGaN layer is used as an i layer, then a cathode electrode is used for forming N-type ohmic contact with the two weft electron gases on an AlGaN layer/GaN layer heterojunction by using a process, and an anode electrode is used for forming P-type ohmic contact on the P-GaN, so that the diode is manufactured by adopting a Schottky junction generated between metal/the two weft electron gases compared with the diode on the GaN in the prior art, has higher reverse breakdown capability and reduces the risks in application;
(2) The preparation method of the PIN junction vertical diode disclosed by the invention is simple, reasonable in step arrangement, high in reverse breakdown capability and wide in application prospect.
Drawings
FIG. 1 is a schematic diagram of a PIN junction vertical diode according to embodiment 1 of the present invention;
FIG. 2 is a top view of embodiment 1 of the PIN junction vertical diode of the present invention;
FIG. 3 is a schematic diagram of the area to be etched in embodiment 1 of the PIN junction vertical diode according to the present invention;
FIG. 4 is a schematic diagram of a structure of a PIN junction vertical diode according to embodiment 2 of the present invention;
FIG. 5 is a top view of example 2 of the PIN junction vertical diode of the present invention;
FIG. 6 is a schematic diagram of the area to be etched in embodiment 2 of the PIN junction vertical diode according to the present invention;
FIG. 7 is a schematic diagram showing the reverse specific curves of the internal voltage and the total current of the PIN junction vertical diodes of example 1, example 2 and comparative example 1;
in the figure: substrate 1, gaN layer 2, alGaN layer 3, cathode electrode 4, P-GaN layer 5, anode electrode 6, region a to be etched.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be made clearly and completely by referring to fig. 1 to 3, fig. 4 to 6, examples 1 and 2, and comparative example 1 in conjunction with specific experimental data and fig. 7, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The PIN junction vertical diode comprises a substrate 1, a GaN layer 2, an AlGaN layer 3, a cathode electrode 4, a P-GaN layer 5 and an anode electrode 6 as shown in figures 1-6; the PIN junction vertical diode comprises 2 structures, wherein one structure is that a cathode electrode 4 is arranged on the inner side and an anode electrode 6 is arranged on the outer side, and the other structure is that the cathode electrode 4 is arranged on the outer side and the anode electrode 6 is arranged on the inner side; two weft electron gases exist between the GaN layer 2 and the AlGaN layer 3, the cathode electrode 4 forms N-type ohmic contact with the two weft electron gases on the heterojunction of the GaN layer 2/AlGaN layer 3, and the anode electrode 6 forms P-type ohmic contact on the P-GaN layer 5.
The following embodiments 1, 2 provide a structure of a PIN junction vertical diode and a method of manufacturing the same.
Example 1
The example 1, as shown in fig. 1 and 2, has a cathode electrode 4 disposed inside and an anode electrode 6 disposed outside, the PIN junction vertical diode includes (silicon, 1000 μm), a GaN layer 2 (3.8 μm), an AlGaN layer 3 (23 nm), a P-GaN layer 5 (100 nm), and an anode electrode 6 (Ni/Au, 20 nm/20 nm) in this order from bottom to top, and the cathode electrode 4 (Ti/Al, 20 nm/120 nm) is disposed on the GaN layer 2 and outside the GaN layer 2.
The area a to be etched is shown in fig. 3, and the preparation method specifically comprises the following steps:
s1: etching all AlGaN layer 3/P-GaN layer 5 regions except the active region by photoetching technology, performing Cl-based dry etching on the etched region by taking photoresist as a mask, wherein the adopted equipment is ICP, and the etching gas is Cl 2 /BCl 3 Ar (25 sccm/10 sccm/5 sccm), etching to a depth greater than 90nm, and then removing the photoresist by organic cleaning;
s2: etching the cathode region of the P-GaN layer 5 by photoetching technology, performing Cl-based dry etching on the etched region by taking photoresist as a mask, wherein the adopted equipment is ICP, and the etching gas is Cl 2 /BCl 3 /Ar (25 sccm /10 sccm /5 sccm), etching to a depth of completely removing the P-GaN layer 5, and then removing the photoresist by adopting organic cleaning;
s3: soaking the etched area of the AlGaN layer 3/P-GaN layer 5 by adopting surface treatment liquid TMAH for surface treatment so as to reduce the surface roughness; then depositing a Ti/Al (20 nm/120 nm) cathode electrode 4 on the surface of the AlGaN layer 3, and adopting a rapid thermal annealing device to anneal for 30s in nitrogen, wherein the temperature is set to 860 ℃ so that the Ti/Al cathode electrode 4 and the two-weft electron gas form N-type ohmic contact;
s4: soaking the etched area of the P-GaN layer 5 by adopting surface treatment liquid TMAH for surface treatment so as to reduce the surface roughness; then depositing Ni/Au (20 nm/20 nm) anode electrode 6 on the surface of the P-GaN layer 5, and annealing in oxygen for 5min by adopting a rapid thermal annealing device, wherein the temperature is set to 500 ℃, so that the Ni/Au anode electrode 6 and the P-GaN layer 5 form P-type ohmic contact.
Example 2
In example 2, as shown in fig. 4 and 5, a cathode electrode 4 is disposed outside and an anode electrode 6 is disposed inside, the PIN junction vertical diode includes a substrate 1 (silicon, 1000 μm), a GaN layer 2 (3.8 μm), an AlGaN layer 3 (23 nm), a cathode electrode 4 (Ti/Al, 20 nm/120 nm), a P-GaN layer (100 nm) 5 is disposed on the AlGaN layer 3 and outside the cathode electrode 4, and the anode electrode 6 (Ni/Au, 20 nm/20 nm) is disposed on the P-GaN layer 5 from bottom to top.
As shown in fig. 6, the region a to be etched is different from the region a to be etched in the structure and the method of preparation in example 2, which is the same as that in example 1.
Comparative example 1
Comparative example 1 is a conventional GaN-on-a-diode, the process conditions of which are as follows:
1. AlGaN/GaN on Si epitaxial wafer is used, the thickness of AlGaN layer is 23nm, gaN thickness is 3.8 um, and Si thickness is 1000um.
2. Using an N-type ohmic contact process: metal (Ti/Al (20 nm/120 nm)) was deposited as the cathode electrode and annealed at 850 degrees celsius for 30s in nitrogen.
3. Using a schottky contact process: metal (Ni/Au (20 nm/20 nm)) was deposited as an anode electrode.
And (3) effect verification:
the diodes of example 1, example 2 and comparative example 1 (the same device size) were subjected to the reverse breakdown capability performance test, and the test results are shown in fig. 7.
As can be seen from fig. 7, the PIN junction vertical diode of example 1 and example 2 has better reverse breakdown capability than the schottky junction diode of comparative example 1.
The invention has many specific application routes, and the above description is only a preferred embodiment of the invention. It should be noted that the above examples are only for illustrating the present invention and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that modifications may be made without departing from the principles of the invention, and such modifications are intended to be within the scope of the invention.
Claims (10)
1. The PIN junction vertical diode is characterized by comprising a substrate (1), a GaN layer (2), an AlGaN layer (3), a cathode electrode (4), a P-GaN layer (5) and an anode electrode (6); the PIN junction vertical diode comprises 2 structures, wherein one structure is that a cathode electrode (4) is arranged inside and an anode electrode (6) is arranged outside, and the other structure is that the cathode electrode (4) is arranged outside and the anode electrode (6) is arranged inside; two-weft electron gas exists between the GaN layer (2) and the AlGaN layer (3), the cathode electrode (4) forms N-type ohmic contact with the two-weft electron gas on the hetero-junction of the AlGaN layer (3)/the GaN layer (2), and the anode electrode (6) forms P-type ohmic contact on the P-GaN layer (5).
2. The PIN junction vertical diode according to claim 1, comprising, in order from bottom to top, a substrate (1), a GaN layer (2), an AlGaN layer (3), a P-GaN layer (5), an anode electrode (6), the cathode electrode (4) being arranged on the GaN layer (2) and outside the GaN layer (2).
3. The PIN junction vertical diode according to claim 1, comprising, in order from bottom to top, a substrate (1), a GaN layer (2), an AlGaN layer (3), a cathode electrode (4), the P-GaN layer (5) being arranged on the AlGaN layer (3) and outside the cathode electrode (4), the anode electrode (6) being arranged on the P-GaN layer (5).
4. A PIN junction vertical diode according to claim 1, characterized in that the substrate (1) is silicon or sapphire with a thickness of 0-1000 μm.
5. The PIN junction vertical diode according to claim 1, characterized in that the GaN layer (2) has a thickness of 1-5 μm and the AlGaN layer (3) has a thickness of 5-30 nm.
6. The PIN junction vertical diode according to claim 1, characterized in that the P-GaN layer (5) is doped with magnesium ions, wherein the amount of magnesium ion doping is greater than 1e 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the P-GaN layer (5) is 50-100nm.
7. The PIN junction vertical diode according to claim 1, characterized in that the cathode electrode (4) is made of a low work function metal, the thickness of which is 20-300nm; the anode electrode (6) adopts high work function metal, and the thickness of the anode electrode is 20-200nm.
8. The method for manufacturing a PIN junction vertical diode according to any one of claims 1 to 7, comprising the steps of:
s1: etching all AlGaN layer (3)/P-GaN layer (5) areas except the active area;
s2: etching the cathode region of the P-GaN layer (5);
s3: carrying out surface treatment on the etching area of the AlGaN layer (3)/P-GaN layer (5) by adopting a surface treatment liquid; then adopting an electron beam evaporation or magnetron sputtering method to deposit low work function metal on the surface of the AlGaN layer (3) to prepare a cathode electrode (4), and adopting rapid thermal annealing equipment to anneal for 10-60s in inert gas at 500-1000 ℃ so that the cathode electrode (4) and the two-weft electron gas form N-type ohmic contact;
s4, adopting surface treatment liquid to carry out surface treatment on the etched area of the P-GaN layer (5); then adopting an electron beam evaporation or magnetron sputtering method to deposit high work function metal on the surface of the P-GaN layer (5) to prepare an anode electrode (6), and adopting a rapid thermal annealing device to anneal for 10-600s in gas at the temperature of 500-1000 ℃ so that the anode electrode (6) and the P-GaN layer (5) form P-type ohmic contact.
9. The method for manufacturing the PIN junction vertical diode according to claim 8, wherein the etching of S1 specifically comprises the following steps:
(1) Photoetching a region needing etching in the AlGaN layer (3)/P-GaN layer (5) region by adopting a photoetching technology, and taking photoresist as a mask;
(2) By BCl 3 、Cl 2 Ar mixture or BCl 3 、SF 6 Mixed gas or Cl 2 、N 2 、O 2 Performing Cl-based dry etching on the etching area by using mixed gas, wherein the adopted equipment is ICP or RIE, and the etching depth is more than 90 nm;
(3) And (5) removing the photoresist by adopting organic cleaning.
10. The method for manufacturing the PIN junction vertical diode according to claim 8, wherein the etching of S2 specifically comprises the following steps:
(1) Photoetching a region needing etching of the region of the P-GaN layer (5) by adopting a photoetching technology, and taking photoresist as a mask;
(2) By BCl 3 、Cl 2 Ar mixture or BCl 3 、SF 6 Mixed gas or Cl 2 、N 2 、O 2 The mixed gas carries out dry etching on the etching area, the adopted equipment is ICP or RIE, the etching depth is 30-90nm or the P-GaN layer is completely removed5）；
(3) And (5) removing the photoresist by adopting organic cleaning.
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