CN115000154A - Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof - Google Patents
Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof Download PDFInfo
- Publication number
- CN115000154A CN115000154A CN202210642445.4A CN202210642445A CN115000154A CN 115000154 A CN115000154 A CN 115000154A CN 202210642445 A CN202210642445 A CN 202210642445A CN 115000154 A CN115000154 A CN 115000154A
- Authority
- CN
- China
- Prior art keywords
- type
- ion implantation
- source
- region
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 35
- 239000011810 insulating material Substances 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000005684 electric field Effects 0.000 description 10
- 238000000137 annealing Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 4
- 238000004220 aggregation Methods 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000012300 argon atmosphere Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a silicon carbide MOSFET device with an L-shaped vertical source electrode and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: the N-type substrate, the N-type epitaxial layer, the P-type well region and the N-type source region are arranged in sequence; the P-type ion implantation area is positioned in the N-type epitaxial layer and the P-type well region; grooves are arranged in the N-type epitaxial layer, the P-type well region, the N-type source region and the P-type ion implantation region; the gate oxide layer is positioned on the side wall of the groove far away from the P-type ion implantation area and the bottom of a part of the groove connected with the side wall; the source electrode is positioned on the side wall of the groove close to the P-type ion implantation area and the bottom of the other part of the groove connected with the side wall; the grid is positioned in the groove and connected with the gate oxide layer; the isolation region is positioned in the groove between the grid electrode and the source electrode; and the drain electrode is positioned on the N-type substrate and is far away from one surface of the N-type epitaxial layer. The scheme of the invention can improve the breakdown voltage of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a silicon carbide MOSFET device with an L-shaped vertical source electrode and a manufacturing method thereof.
Background
Due to the limitation of silicon-based materials, the performance of silicon-based Metal-Oxide-Semiconductor Field Effect transistors (MOSFET for short) devices is close to the theoretical limit and cannot meet the requirements of the existing applications. The silicon carbide material has the advantages of large forbidden band width, high breakdown field strength, high electron saturation drift rate, high thermal conductivity and the like, and when the silicon carbide material is used for preparing a power device, the silicon carbide material is not only favorable for reducing the on-resistance of the device, but also can greatly improve the switching time, the switching loss, the heat dissipation performance and the like compared with a silicon-based MOSFET. Therefore, the silicon carbide becomes a preferable material for developing high-power, high-temperature and high-frequency power devices, and has a very wide application prospect.
However, in the conventional trench-gated silicon carbide MOSFET, electric field concentration is easily generated at the bottom corner of the trench gate, so that the device is broken down in advance under a rated breakdown voltage, and the forward blocking characteristic of the device is seriously affected.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an L-shaped vertical source silicon carbide MOSFET device and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a silicon carbide MOSFET device with an L-shaped vertical source electrode, which comprises:
the N-type substrate, the N-type epitaxial layer, the P-type well region and the N-type source region are arranged in sequence;
the P-type ion implantation region is positioned in the N-type epitaxial layer and the P-type well region; grooves are formed in the N-type epitaxial layer, the P-type well region, the N-type source region and the P-type ion implantation region;
the gate oxide layer is positioned on the side wall of the groove far away from the P-type ion implantation area and the bottom of a part of the groove connected with the side wall;
the source electrode is positioned on the side wall of the groove close to the P-type ion implantation area and the bottom of the other part of the groove connected with the side wall; wherein, at the bottom of the trench, the P-type ion implantation region completely surrounds the source electrode;
the grid electrode is positioned in the groove and is connected with the grid oxide layer;
an isolation region located in the trench between the gate and the source;
and the drain electrode is positioned on the N-type substrate and is far away from one surface of the N-type epitaxial layer.
Optionally, the source and the N-type source region, the P-type ion implantation region interface is ohmic contact.
Optionally, the thickness of the N-type substrate is 200 μm to 500 μm, and the doping concentration is 1 × 10 18 cm -3 ～1×10 19 cm -3 。
Optionally, the thickness of the N-type epitaxial layer is 10 μm to 12 μm, and the doping concentration is 1 × 10 15 cm -3 ～1×10 16 cm -3 。
Optionally, the thickness of the P-type well region is 0.5 μm to 0.8 μm, and the doping concentration is 5 × 10 16 cm -3 ～5×10 17 cm -3 (ii) a The thickness of the N-type source region is 0.2-0.5 μm, and the doping concentration is 1 × 10 19 cm -3 ～1×10 20 cm -3 。
Optionally, the doping concentration of the P-type ion implantation region is 1 × 10 19 cm -3 ～1×10 20 cm -3 And the P-type ion implantation region is Gaussian doped and has a surface doping concentration of 1 × 10 18 cm -3 Peak doping concentration of 1X 10 20 cm -3 (ii) a The distance between the side surface of the P-type ion implantation region and the side surface of the source electrode is 0.5-0.8 μm, and the distance between the bottom surface of the P-type ion implantation region and the bottom surface of the source electrode is 0.5-0.8 μm.
Optionally, the material of the gate oxide layer comprises silicon dioxide; the material of the source electrode comprises titanium, nickel, molybdenum or tungsten; the material of the grid electrode comprises polycrystalline silicon; the material of the drain electrode comprises titanium, nickel or silver.
Optionally, the depth of the groove is 1 μm to 2 μm, and the width of the groove is 2 μm to 3 μm.
Optionally, the width of the gate is 0.5 μm to 0.8 μm.
The second embodiment of the present invention further provides a method for manufacturing an L-shaped vertical source silicon carbide MOSFET device, including:
providing an N-type substrate, and growing an N-type epitaxial layer on the N-type substrate;
forming a P-type well region on the N-type epitaxial layer by utilizing an ion implantation process;
forming a P-type ion implantation area in the N-type epitaxial layer and the P-type well area by using an ion implantation process;
etching the N-type epitaxial layer, the P-type well region and the P-type ion implantation region to form a groove;
forming an N-type source region on the P-type well region by using an ion implantation process;
growing a gate oxide layer on the side wall and the bottom of the groove;
growing a grid on the side wall of the groove far away from the P-type ion implantation area and the bottom of a part of the groove connected with the side wall;
filling a first insulating material in the groove;
etching the first insulating material close to the P-type ion implantation area in the groove to form a groove filled with source metal;
growing a source electrode in an L-shaped structure on the side wall of the groove filled with the source electrode metal, which is close to the P-type ion implantation area, and the bottom of the groove filled with the source electrode metal, which is connected with the side wall by adopting a physical vapor deposition process;
filling a second insulating material in the groove filled with the source metal; wherein the first insulating material and the second insulating material together form the isolation region;
and depositing a drain on one surface of the N-type substrate, which is far away from the N-type epitaxial layer, so as to finish the preparation of the silicon carbide MOSFET device with the L-shaped vertical source.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the invention provides a silicon carbide MOSFET device with an L-shaped vertical source electrode, which comprises an N-type substrate, an N-type epitaxial layer and a P-type well region, wherein the N-type epitaxial layer is arranged on the N-type substrate; the P-type ion implantation region is positioned in the N-type epitaxial layer and the P-type well region; the N-type source region is positioned on one side of the P-type well region and covers the P-type well region and the P-type ion implantation region; the gate oxide layer is positioned at the bottom of the groove and on the side wall far away from the P-type ion implantation area; a gate electrode on a sidewall of the gate oxide layer; the source electrode is positioned at the bottom of the groove and is distributed on the side wall close to the P-type ion implantation area in an L-shaped structure, and the P-type ion implantation area surrounds the source electrode; isolation regions for gate and source isolation; and the drain electrode is positioned on the N-type substrate and is far away from one surface of the N-type epitaxial layer. According to the scheme, on one hand, the corner of the source electrode is surrounded by the P-type ion implantation area, so that the electric field can be effectively prevented from being gathered at the corner of the source electrode, and the device is prevented from being directly broken down at the source electrode. On the other hand, the source electrode and the grid electrode are integrated in the same groove, the grid electrode is in a vertical strip shape, the isolation region is used for insulation, the width of each cell can be effectively reduced, the P-type ion injection regions of two adjacent cells form a shielding layer structure, the electric field aggregation at the corner of the gate oxide layer is effectively relieved, the device is prevented from being broken down at the corner of the gate oxide layer in advance, and the breakdown voltage of the device is improved.
In addition, the source electrode and the P-type ion implantation area which are distributed in the L-shaped structure can form good ohmic contact, so that the P-type trap area is set to be zero, the uniformity of ohmic contact can be improved, and the problem that the threshold voltage of the device is too high due to too large local ohmic contact is solved. By short-circuiting the N-type source region and the P-type ion injection region by the source electrode, hole current directly flows to the source electrode through the P-type ion injection region, so that parasitic NPN transistor effect in a blocking state is avoided, and reverse breakdown voltage equivalent PiN diode is realized.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of an L-shaped vertical source silicon carbide MOSFET device according to a first embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing an L-shaped vertical source silicon carbide MOSFET device according to a second embodiment of the present invention;
fig. 3(a) to fig. 3(L) are schematic structural diagrams corresponding to steps of a method for manufacturing an L-shaped vertical source silicon carbide MOSFET device according to a second embodiment of the present invention.
Description of reference numerals:
101-source; 102-a gate; 103-a drain electrode; a 110-N type substrate; a 120-N type epitaxial layer; 130-P type well region; 140-N type source region; 150-P type ion implantation region; 160-gate oxide layer; 170-an isolation region; 151-trenches; 152-trenches filled with source metal; 171-a first insulating material; 172-second insulating material.
Detailed Description
In order to avoid premature breakdown of the device below a rated breakdown voltage due to an electric field generated at the corner of the trench gate, embodiments of the present invention provide an L-type vertical source silicon carbide MOSFET device and a method for manufacturing the same, and a scheme provided by the present embodiment will be described in detail below with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
A first embodiment of the present invention provides an L-shaped vertical source silicon carbide MOSFET device, and referring to fig. 1, fig. 1 is a schematic structural diagram of an L-shaped vertical source silicon carbide MOSFET device provided in the first embodiment of the present invention, including:
an N-type substrate 110, an N-type epitaxial layer 120, a P-type well region 130 and an N-type source region 140 are sequentially disposed.
The material of the N-type substrate 110 may include silicon carbide, among others.
The P-type ion implantation region 150 is located in the N-type epitaxial layer 120 and the P-type well region 130.
Wherein, the upper surface of the P-type ion implantation region 150 is flush with the upper surface of the P-type well region 130. Trenches (not shown) are disposed in the N-type epitaxial layer 120, the P-type well region 130, the N-type source region 140 and the P-type ion implantation region 150. The depth of the trench is greater than the depth of the P-well region 130.
And a gate oxide layer 160 on the sidewall of the trench away from the P-type ion implantation region 150 and a portion of the bottom of the trench connected to the sidewall. Wherein, the gate oxide layer 160 is in an L-shaped structure.
The source electrode 101 is positioned on the side wall of the groove close to the P-type ion implantation area 150 and the bottom of the other part of the groove connected with the side wall; wherein, at the bottom of the trench, the P-type ion implantation region 150 completely surrounds the source 101.
The source 101 is in an L-shaped structure, and a corner of the source 101 is completely surrounded by the P-type ion implantation region 150; the thickness of the source 101 laterally distributed at the bottom of the trench is higher than the thickness of the gate oxide 160 laterally distributed at the bottom of the trench.
Further, the source 101 is completely in contact with the P-type ion implantation region 150 except for a portion in contact with the N-type source region 140, i.e., surrounded by the P-type ion implantation region 150.
And the grid electrode 102 is positioned in the groove and is connected with the grid oxide layer 160.
And an isolation region 170 is located in the trench of the gate 102 and the source 101 for isolating the source 101 and the gate 102.
And a drain 103 located on a side of the N-type substrate 110 away from the N-type epitaxial layer 120.
The silicon carbide MOSFET device with the L-shaped vertical source provided by the embodiment of the invention comprises an N-type substrate 110, an N-type epitaxial layer 120 and a P-type well region 130; a P-type ion implantation region 150 located in the N-type epitaxial layer 120 and the P-type well region 130; an N-type source region 140 located at one side of the P-well 130 and covering the P-well 130 and the P-type ion implantation region 150; a gate oxide layer 160 on the bottom of the trench and on the sidewall away from the P-type ion implantation region 150; a gate 102 located in the trench and connected to the sidewall of the gate oxide layer 160; a source 101 in an L-shaped structure on the bottom of the trench and on the sidewall near the P-type ion implantation region 150, and the P-type ion implantation region 150 surrounds the source 101; isolation regions 170 for gate 102 and source 101 isolation; and the drain electrode 103 is positioned on the N-type substrate 110 and is far away from one side of the N-type epitaxial layer 120. Therefore, according to the scheme provided by the embodiment of the invention, on one hand, the corner of the source 101 is completely surrounded by the P-type ion implantation region 150, so that the electric field can be effectively prevented from being gathered at the corner of the source 101, and the device is prevented from being directly broken down at the source 101. On the other hand, the source electrode 101 and the grid electrode 102 are integrated in the same groove, the grid electrode 102 is in a vertical strip shape, the isolation region 170 is used for insulation, the width of each cell can be effectively reduced, the width of each cell can be reduced to 3.5 microns at minimum, and then the P-type ion injection regions 150 of two adjacent cells form a shielding layer structure, so that electric field aggregation at the corners of the gate oxide layer 160 is effectively relieved, the device is prevented from being broken down at the corners of the gate oxide layer 160 in advance, and the breakdown voltage of the device is improved.
In addition, the source 101 and the P-type ion implantation region 150 can form a good ohmic contact, so that the P-type well region 130 is set to be zero, the uniformity of the ohmic contact can be improved, and the problem that the threshold voltage of the device is too high due to too large local ohmic contact is solved. By shorting the source 101 to the N-type source region 140 and the P-type ion implantation region 150, a hole current can directly flow to the source 101 through the P-type ion implantation region 150, thereby avoiding a parasitic NPN transistor effect in a blocking state and realizing a reverse breakdown voltage equivalent PiN (formed between the P-type well region 130 and the N-type epitaxial layer 120) diode.
In the embodiment of the invention, the interfaces of the source 101, the N-type source region 140 and the P-type ion implantation region 150 are all ohmic contacts.
In the embodiment of the invention, the thickness of the N-type substrate 110 is 200 μm-500 μm, and the doping concentration is 1 × 10 18 cm -3 ～1×10 19 cm -3 。
In the embodiment of the invention, the thickness of the N-type epitaxial layer 120 is 10 μm to 12 μm, and the doping concentration is 1 × 10 15 cm -3 ～1×10 16 cm -3 。
In the embodiment of the present invention, the thickness of the P-well 130 is 0.5 μm to 0.8 μm, the total width is 1 μm to 1.5 μm, and the doping concentration is 5 × 10 16 cm -3 ～5×10 17 cm -3 (ii) a The N-type source region 140 has a thickness of 0.2-0.5 μm, a total width of 1.5-2 μm, and a doping concentration of 1 × 10 19 cm -3 ～1×10 20 cm -3 。
In the embodiment of the present invention, the doping concentration of the P-type ion implantation region 150 is 1 × 10 19 cm -3 ～1×10 20 cm -3 The P-type ion implantation region 150 is Gaussian doped with a surface doping concentration of 1 × 10 18 cm -3 Peak doping concentration of 1X 10 20 cm -3 。
It is understood that the doping concentration of the P-type ion implantation region 150 after the ion implantation is 1 × 10 19 cm -3 ～1×10 20 cm -3 。
Further, the side surface of the P-type ion implantation region 150 (the surface contacting the P-type well region 130) is spaced from the side surface of the source 101 (the surface contacting the N-type source region 140 and the P-type ion implantation region 150) by 0.5 μm to 0.8 μm, and the bottom surface of the P-type ion implantation region 150 is spaced from the bottom surface of the source 101 by 0.5 μm to 0.8 μm.
In the embodiment of the invention, the thickness of the gate oxide layer 160 distributed on the side wall and the bottom of the trench is 0.05-0.08 μm; the material of the gate oxide layer 160 may include silicon dioxide, but is not limited to silicon dioxide.
In the embodiment of the invention, the depth of the groove is 1-2 μm, and the width of the groove is 2-3 μm.
In the embodiment of the invention, the width of the grid electrode 102 is 0.5-0.8 μm; the material of the gate 102 may comprise polysilicon.
In the embodiment of the invention, the thickness of the source electrode 101 distributed on the side wall and the bottom of the groove is 0.2-0.3 μm; in order to prevent the short circuit of the grid source, the width of the source electrode 101 at the bottom of the groove is 0.4-0.6 μm; the material of the source electrode 101 may include titanium, nickel, molybdenum, or tungsten.
In the embodiment of the invention, the thickness of the drain electrode 103 is 1 μm to 10 μm; the material of the drain electrode 103 may include titanium, nickel, or silver.
The inventor researches and discovers that electric field concentration is easily generated at the bottom corner of the silicon carbide MOSFET trench gate of the traditional trench gate, so that the device is broken down in advance under the condition of lower than rated breakdown voltage, and the forward blocking characteristic of the device is seriously influenced. Therefore, in order to solve the above problem, the embodiment of the present invention proposes a new trench gate structure, in which the source 101 and the gate 102 are integrated in the same trench 151, and in order to prevent the gate-source short circuit, and in order to increase the contact area between the source 101 and the P-type ion implantation region 150 in the trench, the source 101 is set to be in an L-type structure, so as to ensure the contact area between the source 101 and the P-type ion implantation region 150 at the bottom of the trench, and increase the width of the isolation region 170 between the gate and the source to prevent the risk of the gate-source short circuit.
It can be understood that the source 101 and the gate 102 are integrated in the same trench, and the gate 101 is a vertical strip, which can effectively reduce the width of the cell, so that the P-type ion implantation region 150 of two adjacent cells forms a shielding layer structure, thereby effectively relieving the electric field aggregation at the corner of the gate oxide layer 160, preventing the device from being broken down at the corner of the gate oxide layer 160 in advance, and improving the breakdown voltage of the device. If the width of the gate 102 is too wide, the width of the device cell will be increased, so that the shielding effect formed by the P-type ion implantation region 150 between adjacent cells will be reduced, and the inventors have found that the shielding effect is best when the width of the gate 102 in the groove is 0.5 μm to 0.8 μm.
A method for manufacturing a silicon carbide MOSFET device with an L-shaped vertical source according to a second embodiment of the present invention is described in detail below with reference to the accompanying drawings, and the same or corresponding parts as those in the previous embodiment can be referred to the description of the previous embodiment, and will not be described again below. Referring to fig. 2, and fig. 3(a) to fig. 3(L) are schematic structural diagrams corresponding to steps of a method for manufacturing an L-shaped vertical source silicon carbide MOSFET device according to a second embodiment of the present invention.
S10, see fig. 3(a), an N-type substrate 110 is provided, and an N-type epitaxial layer 120 is grown on the N-type substrate 110.
Specifically, the embodiment of the invention firstly carries out the doping treatment on the silicon wafer with the thickness of 200-500 μm and the doping concentration of 1 × 10 18 cm -3 ～1×10 19 cm -3 The SiC substrate of (1), but not limited to, is subjected to RCA standard cleaning as the N-type substrate 110; then epitaxially growing a film with a thickness of 10-12 μm and a doping concentration of 1 × 10 on the N-type substrate 110 15 cm -3 ～1×10 16 cm -3 An N-type epitaxial layer 120.
S20, referring to fig. 3(b), a P-well 130 is formed on the N-epi layer 120 by an ion implantation process.
Specifically, the embodiment of the invention forms the P-well 130 by ion implantation with a doping concentration of 5 × 10 16 cm -3 ～5×10 17 cm -3 。
S30, referring to fig. 3(c), a P-type ion implantation region 150 is formed in the N-type epitaxial layer 120 and the P-type well region 130 by an ion implantation process.
Specifically, a mask layer is deposited on the upper surface of the P-type well region 130, a mask pattern is formed by a photolithography and etching process, ion implantation is performed on the P-type well region 130 and a part of the N-type epitaxial layer 120, and the implanted ions are Al ions, so that a P-type ion implantation region 150 is formed.
Wherein the P-type ion implantation region 150Is Gaussian doped and has a surface doping concentration of 1 × 10 18 cm -3 Peak doping concentration of 1X 10 20 cm -3 The doping concentration of the P-type ion implantation region 150 after ion implantation is 1 × 10 19 cm -3 ～1×10 20 cm -3 . The P-type ion implantation region 150 is implanted into the N-type epitaxial layer 120 to a depth of 2.5 μm to 3.5 μm, where the depth of the implantation depends on the depth of the trench 151 required subsequently, and the distance between the bottom of the trench 151 and the bottom of the P-type ion implantation region 150 is required to be 0.5 μm to 0.8 μm.
S40, referring to fig. 3(d), the N-type epitaxial layer 120, the P-type well 130 and the P-type ion implantation region 150 are etched to form a trench 151.
Specifically, firstly, a mask layer is deposited and formed on the upper surfaces of the P-type well region 130 and the P-type ion implantation region 150, and a mask pattern is formed through a photoetching process; then, the trench 151 is etched by an Inductively Coupled Plasma (ICP) etching method. Wherein, the depth of the trench 151 is 1 μm to 2 μm, the width is 2 μm to 3 μm, the trench 151 is located in the N-type epitaxial layer 120, the P-type well region 130 and the P-type ion implantation region 150, the bottom surface of the trench 151 is located on the bottom surface of the P-type ion implantation region 150, the distance between the bottom surface of the trench 151 and the bottom surface of the P-type ion implantation region 150 is 0.5 μm to 0.8 μm, and the distance between the sidewall of the trench 151 close to the P-type ion implantation region 150 and the sidewall of the P-type ion implantation region 150 far away from the trench 151 is 0.5 μm to 0.8 μm.
S50, referring to fig. 3(e), an N-type source region 140 is formed on the P-type well region 130 by an ion implantation process.
Specifically, firstly, a mask layer is deposited on the bottom of the trench 151, the upper surfaces of the P-type well region 130 and the P-type ion implantation region 150, and a mask pattern is formed through a photoetching process; then, an N-type source region 140 is formed in the P-type well region 130 by ion implantation with a doping concentration of 1 × 10 19 cm -3 ～1×10 20 cm -3 。
S60, see fig. 3(f), a gate oxide layer 160 is grown on the sidewalls and bottom of the trench.
Specifically, sacrificial oxidation is performed on the surface of the trench 151 using a surface sacrificial layer technique. Firstly, a sacrificial oxide layer is deposited, then partial sacrificial oxide layer is etched, and then a layer of silicon dioxide is grown by adopting a thermal oxidation method to be used as a gate oxide layer 160, wherein the thickness of the gate oxide layer 160 is 0.05-0.08 mu m. Annealing in the atmosphere of nitric oxide, wherein the annealing temperature is 1200 ℃, and the annealing time is 1 h. Then, a mask layer is deposited on the gate oxide layer, a mask pattern is formed through a photoetching process, the redundant gate oxide layer 160 is etched, and only the gate oxide layer 160 on the side wall and the bottom of the groove is reserved.
S70, see fig. 3(g), the gate electrode 102 is grown on the sidewall of the trench 151 away from the P-type ion implantation region 150 and a portion of the bottom of the trench 151 connected to the sidewall.
Specifically, polysilicon is deposited on the bottom of the trench 151 and on the N-type source implant region 140, and then the polysilicon is polished by a chemical mechanical polishing process, and the N-type source implant region 140 serves as a stop layer for the chemical mechanical polishing. Then, a mask layer is deposited, a mask pattern is formed by a photolithography etching process, and the excess polysilicon in the trench 151 is etched away to form the gate 102. Wherein, the width of the grid electrode 102 is 0.5-0.8 μm.
S80, referring to fig. 3(h), the trench 151 is filled with the first insulating material 171.
Specifically, a first insulating material 171 is deposited in the trench 151 by chemical vapor deposition to serve as an isolation layer 170 between the gate electrode 102 and the source electrode 101 to be subsequently fabricated. The first insulating material 171 may be, but is not limited to, silicon dioxide. Then, annealing is carried out under the atmosphere of nitric oxide, the annealing temperature can be 1200 ℃, and the annealing time can be 1 h.
S90, referring to fig. 3(i), the first insulating material 171 near the P-type ion implantation region 150 in the trench 151 is etched to form a trench 152 filled with source metal.
Specifically, a mask layer is deposited on the first insulating material 171, a mask pattern is formed by a photolithography and etching process, a portion of the first insulating material 171 and the gate oxide layer 160 are etched, and a trench 152 filled with a source metal is etched for subsequent source fabrication.
S100, referring to fig. 3(j), a physical vapor deposition process is used to grow the source 101 in an L-shaped structure on the sidewall of the source metal-filled trench 152 near the P-type ion implantation region 150 and the bottom of the source metal-filled trench 152 connected to the sidewall.
Specifically, a source metal is first deposited in the trench 152 by physical vapor deposition. Wherein, the source metal can be titanium, nickel, molybdenum or tungsten. Then, a mask layer is deposited on the upper surfaces of the first insulating layer material 171 and the source metal, and a part of the source metal in the trench 152 is etched away by a photoetching process to form the L-shaped source 101, wherein the thickness of the source 101 on the sidewall and the bottom of the trench is 0.2 μm to 0.3 μm, and the width of the source 101 on the bottom of the trench is 0.4 μm to 0.6 μm. And then carrying out a rapid thermal annealing process under the argon atmosphere. The annealing temperature may be 1000 ℃ for 3 min.
It is understood that the source 101 forms an ohmic contact with the N-type source region 140 and the P-type ion implantation region 150.
S110, referring to fig. 3(k), the trench 152 filled with the source metal is filled with a second insulating material 172.
Specifically, a second insulating material 172 is grown in the source metal-filled trench 152 by chemical vapor deposition. The second insulating material 172 is then polished to be flush with the upper surface of the first insulating material 171 by chemical mechanical polishing. The second insulating material 172 may be, but is not limited to, silicon dioxide. The first insulating material 171 and the second insulating material 172 may be made of the same material or different materials. In the embodiment of the present invention, it is preferable that the first insulating material 171 and the second insulating material 172 are made of the same material, and the isolation region 170 shown in fig. 1 is formed by the first insulating material 171 and the second insulating material 172.
S120, referring to fig. 3(l), the drain electrode 103 is deposited on the N-type substrate 110 and a side away from the N-type epitaxial layer 120.
Specifically, drain metal is deposited on the surface of the N-type substrate 110 far away from the N-type epitaxial layer 120 to serve as the drain 103, and the thickness of the drain 103 is 1-10 μm. The deposited drain metal may include titanium, nickel, or silver, among others.
According to the manufacturing method of the silicon carbide MOSFET device with the L-shaped vertical source electrode, provided by the embodiment of the invention, on one hand, the corner of the source electrode 101 is surrounded by the P-type ion implantation area 150, so that the electric field can be effectively prevented from being gathered at the corner of the source electrode 101, and the device is prevented from being directly broken down at the source electrode 101. On the other hand, the source 101 and the gate 102 which are distributed in an L-shaped structure are integrated in the same groove 151, the gate 102 is in a vertical strip shape, the isolation region 170 is used for insulation, the width of each cell can be effectively reduced, the P-type ion injection regions 150 of two adjacent cells form a shielding layer structure, the electric field aggregation at the corners of the gate oxide layer 160 is effectively relieved, the device is prevented from being broken down at the corners of the gate oxide layer 160 in advance, and the breakdown voltage of the device is improved.
In addition, the source 101 and the P-type ion implantation region 150 distributed in the L-shaped structure can form a good ohmic contact, so that the P-type well region 130 is set to zero, the uniformity of the ohmic contact can be improved, and the problem of too high threshold voltage of the device due to too large local ohmic contact is solved. By shorting the source 101 to the N-type source region 140 and the P-type ion implantation region 150, hole current directly flows to the source 101 through the P-type ion implantation region 150, thereby avoiding parasitic NPN transistor effect in the blocking state and realizing reverse breakdown voltage equivalent PiN diode.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (10)
1. An L-shaped vertical source silicon carbide MOSFET device, comprising:
the N-type substrate, the N-type epitaxial layer, the P-type well region and the N-type source region are arranged in sequence;
the P-type ion implantation region is positioned in the N-type epitaxial layer and the P-type well region; grooves are formed in the N-type epitaxial layer, the P-type well region, the N-type source region and the P-type ion implantation region;
the gate oxide layer is positioned on the side wall of the groove far away from the P-type ion implantation area and the bottom of a part of the groove connected with the side wall;
the source electrode is of an L-shaped structure and is positioned on the side wall of the groove close to the P-shaped ion implantation area and the bottom of the other part of the groove connected with the side wall; wherein, at the bottom of the trench, the P-type ion implantation region completely surrounds the source electrode;
the grid electrode is positioned in the groove and is connected with the grid oxide layer;
an isolation region located in the trench between the gate and the source;
and the drain electrode is positioned on the N-type substrate and is far away from one surface of the N-type epitaxial layer.
2. The L-type vertical source silicon carbide MOSFET device of claim 1, wherein the interface of the source with the N-type source region and the P-type ion implantation region is an ohmic contact.
3. The L-type vertical source silicon carbide MOSFET device as claimed in claim 1, wherein the N-type substrate has a thickness of 200 μm to 500 μm and a doping concentration of 1 x 10 18 cm -3 ～1×10 19 cm -3 。
4. The L-type vertical source SiC MOSFET device of claim 1, wherein the N-type epitaxial layer has a thickness of 10 μm to 12 μm and a doping concentration of 1 x 10 15 cm -3 ～1×10 16 cm -3 。
5. The L-type vertical source SiC MOSFET device according to claim 1, wherein the thickness of the P-type well region is 0.5-0.8 μm, and the doping concentration is 5 x 10 16 cm -3 ～5×10 17 cm -3 (ii) a The thickness of the N-type source region is 0.2-0.5 μm, and the doping concentration is 1 × 10 19 cm -3 ～1×10 20 cm -3 。
6. The L-type vertical source SiC MOSFET device of claim 1, wherein the P-type ion implantation region has a doping concentration of 1 x 10 19 cm -3 ～1×10 20 cm -3 And the P-type ion implantation region is Gaussian doped and has a surface doping concentration of 1 × 10 18 cm -3 Peak doping concentration of 1X 10 20 cm -3 (ii) a The distance between the side surface of the P-type ion implantation region and the side surface of the source electrode is 0.5-0.8 μm, and the distance between the bottom surface of the P-type ion implantation region and the bottom surface of the source electrode is 0.5-0.8 μm.
7. An L-type vertical source silicon carbide MOSFET device as claimed in claim 1 wherein the material of the gate oxide layer comprises silicon dioxide; the material of the source electrode comprises titanium, nickel, molybdenum or tungsten; the material of the grid electrode comprises polysilicon; the material of the drain electrode comprises titanium, nickel or silver.
8. The L-type vertical source silicon carbide MOSFET device of claim 1 wherein said trench has a depth of 1 to 2 μm and a width of 2 to 3 μm.
9. An L-type vertical source silicon carbide MOSFET device as claimed in claim 1 wherein the width of the gate is between 0.5 μm and 0.8 μm.
10. A manufacturing method of an L-shaped vertical source silicon carbide MOSFET device is characterized by comprising the following steps:
providing an N-type substrate, and growing an N-type epitaxial layer on the N-type substrate;
forming a P-type well region on the N-type epitaxial layer by utilizing an ion implantation process;
forming a P-type ion implantation area in the N-type epitaxial layer and the P-type well area by using an ion implantation process;
etching the N-type epitaxial layer, the P-type well region and the P-type ion implantation region to form a groove;
forming an N-type source region on the P-type well region by using an ion implantation process;
growing a gate oxide layer on the side wall and the bottom of the groove;
growing a grid on the side wall of the groove far away from the P-type ion implantation area and the bottom of a part of the groove connected with the side wall;
filling a first insulating material in the groove;
etching the first insulating material close to the P-type ion implantation area in the groove to form a groove filled with source metal;
growing a source electrode in an L-shaped structure on the side wall of the groove filled with the source electrode metal, which is close to the P-type ion implantation area, and the bottom of the groove filled with the source electrode metal, which is connected with the side wall by adopting a physical vapor deposition process;
filling a second insulating material in the groove filled with the source metal; wherein the first insulating material and the second insulating material together form the isolation region;
and depositing a drain on one surface of the N-type substrate, which is far away from the N-type epitaxial layer, so as to finish the preparation of the silicon carbide MOSFET device with the L-shaped vertical source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210642445.4A CN115000154A (en) | 2022-06-08 | 2022-06-08 | Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210642445.4A CN115000154A (en) | 2022-06-08 | 2022-06-08 | Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115000154A true CN115000154A (en) | 2022-09-02 |
Family
ID=83033313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210642445.4A Pending CN115000154A (en) | 2022-06-08 | 2022-06-08 | Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115000154A (en) |
-
2022
- 2022-06-08 CN CN202210642445.4A patent/CN115000154A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11342433B2 (en) | Silicon carbide devices, semiconductor devices and methods for forming silicon carbide devices and semiconductor devices | |
| JP2008016747A (en) | Trench-mos silicon carbide semiconductor device and method for manufacturing the same | |
| CN114420761B (en) | High-pressure-resistant silicon carbide device and preparation method thereof | |
| JP7476947B2 (en) | Method for manufacturing silicon carbide semiconductor device | |
| CN115642088A (en) | Groove type SiC MOSFET device structure and manufacturing method thereof | |
| CN111755521A (en) | Silicon carbide UMOSFET device integrated with TJBS | |
| CN114792734A (en) | Double-groove silicon carbide MOSFET and preparation method thereof | |
| CN113972261A (en) | Silicon carbide semiconductor device and preparation method | |
| CN116525683B (en) | Deep-well type SiC Mosfet device and preparation method thereof | |
| CN112838126A (en) | Asymmetric silicon carbide UMOSFET device with shielding region and preparation method | |
| JP6648852B1 (en) | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device | |
| TW202407808A (en) | Power semiconductor device and manufacturing method thereof | |
| CN111509034A (en) | Field effect transistor with same gate source doping, cell structure and preparation method | |
| CN111081778A (en) | Silicon carbide groove type MOSFET device and manufacturing method thereof | |
| CN116364778A (en) | HJD integrated SiC VDMOSFET device and preparation method thereof | |
| JP2012238887A (en) | Manufacturing method of trench mos type silicon carbide semiconductor device | |
| CN213242560U (en) | Schottky diode | |
| CN112820777A (en) | SBD-integrated silicon carbide UMOSFET device and preparation method thereof | |
| CN115000154A (en) | Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof | |
| CN111509037A (en) | Silicon carbide MOS device with groove type JFET and preparation process thereof | |
| CN111755520B (en) | JBS (junction-junction | |
| CN111755522B (en) | Silicon carbide UMOSFET device integrated with TJBS | |
| CN117497488B (en) | Preparation method of MOS device integrated with JFET and MOS device | |
| CN214378459U (en) | Silicon carbide UMOSFET device integrated with SBD | |
| CN111969036B (en) | VDMOSFET device for improving UIS tolerance and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |