JPS63132481A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To reduce remarkably base resistance, by determining the position of an aperture for implanting impurity to form a high concentration P-type region in the manner of self align to the position of a first polycrystalline silicon region on a gate oxide film being a gate electrode. CONSTITUTION:A gate oxide film 5 and a polycrystalline silicon film are formed on a main surface of an N-type semiconductor substrate 3, and the polycrystalline silicon film is divided by etching into first and second polycrystalline silicon regions 6 and 6a. Mask material 12 is buried, resist 12a is again spread, and the second polycrystalline region 6a only is selectively eliminated to make an aperture. Impurity is doped from the aperture, and a high impurity concentration region 2a of one conductivity type is formed in the semiconductor substrate 3. By applying the first polycrystalline silicon region to a mask, impurity is doped, and a base region 9 of one conductivity type and a source region 10 of the opposite conductivity type are formed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing an insulated gate field effect transistor, and in particular to a manufacturing method for suppressing parasitic transistor operation and improving breakdown resistance. It is related to the method.

(Prior Art) A conventional method for manufacturing an insulated gate field effect transistor (DMOSFEJ) having a double diffusion structure will be described below with reference to FIG.

As shown in FIG. 3(a), an oxide film 1 is formed by oxidizing an N-type semiconductor substrate 3. As shown in FIG. Next P E P
(Photo engraving process
ss) technique, the oxide film is opened, and impurities are implanted through the opening to form a heavily doped P-type base region 2. Next, after oxidizing the substrate 3 again, the oxide film 4 is left and the oxide film 1 is removed using PEP technology. Next, gate oxidation is performed to form an oxide film 5, and then a polycrystalline silicon film that will become a gate electrode is deposited.The unnecessary polycrystalline silicon film is removed using PEP technology, and a gate electrode is formed on the gate oxide film 5. A polycrystalline silicon region 6 is formed (see FIG. 3(b)). Next, using the polycrystalline silicon region 6 as a mask, ion implantation technology is used to sequentially diffuse, for example, boron (B) and phosphorus (P) to form a low-concentration P-type base region 9 that will become a channel, and inside the P-type base region 9. N-type source regions 10 are formed in (
(See Figure 3(c)). Thereafter, an insulating layer is deposited, and a source electrode in ohmic contact with the N-type source region 10 is formed on the upper surface of the substrate, and a drain electrode is formed in contact with the drain region 3 on the lower surface of the substrate, respectively, thereby completing the DMOS FET.

In the DMOS FET on the side street, J3 is the third
As can be seen from Figure (c), the N-type source region 10, the low 1
It has a structure in which an N P N odd transistor 11 consisting of a 101112P type base region 9 and drain region 3 exists. The emitter of this NPN parasitic transistor 11 corresponds to the N type source region 10, the base corresponds to the lightly doped P type base region 9, and the collector corresponds to the N type drain region 3, respectively. When this element is used in load operation, when the element is switched off from the on state, a large induced electromotive force is applied between the drain and source, with the drain positive and the source negative, resulting in an unnatural transistor. 11 operates and is destroyed due to thermal runaway, which has the disadvantage that the element is likely to be destroyed.Therefore, a method to prevent such influence of the parasitic transistors 1 to 11 is desired.

(Problems to be Solved by the Invention) In order to prevent the parasitic transistor 11 from operating due to a large induced electromotive force when the parasitic transistor 11 is turned off, impurities in the P-type base region 9 corresponding to the base of the parasitic transistor 11 must be removed. It is necessary to increase the density and reduce the base resistance of the parasitic transistor 11. For this purpose, see Figure 3 (
In c), it is desirable to minimize the distance m between the high i11 degree P-type base region side surface 8 and the N-type source region side surface 13.

In this case, it is higher than the side surface 13 of the N-type source region! When the side surface 8 of the fP type base region is on the outside (on the right side of the drawing),
Directly below the N-type source region becomes a highly doped P-type base region, which can reduce the base resistance and prevent an anomalous transistor from turning on, but it affects the threshold voltage of this MOS FET, which poses a problem. Therefore, it is desirable to control the distance m to a minimum.

However, in the prior art, as described above, the highly doped P-type base region 1Ii12 and the polycrystalline silicon film 6 that will become the gate electrode are formed individually using the PEP technique.
The distance IIjlil between the side surface 8 of the highly doped P-type base region 2 and the side surface 7 of the polycrystalline silicon film 6 shown in FIG. It will be done.

Therefore, as shown in FIG. 3(c), it is desirable to minimize the distance m, but as mentioned above, due to constraints on mask alignment accuracy and lateral diffusion accuracy of the high-concentration P-type base region 2, the distance m
It was difficult to minimize the distance to 4m.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to solve the above-mentioned problems, suppress parasitic transistor operation,
An object of the present invention is to provide a method for manufacturing an MO8 type field effect transistor with improved breakdown resistance.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes (a) a step of depositing a polycrystalline silicon film on a semiconductor substrate via a gate insulating film; By using PEP technology, a first polycrystalline silicon region on an oxide model that will become a gate electrode, and a second polycrystalline silicon region spaced a predetermined distance from the first polycrystalline silicon region (in a later process, a high concentration of one conductivity type) are formed. a step of simultaneously forming the base region separately (which will become an opening region for impurity implantation in the base region);
(c) A step of applying a mask material, such as a resist, having an etching selectivity to polycrystalline silicon, removing the mask material on the polycrystalline silicon, and embedding the mask material only between the first and second polycrystalline silicon regions. , (d) After applying the mask material again, selectively removing and opening only the second polycrystalline silicon region, and (e) implanting impurities from this removed region to form a highly concentrated base region of one conductivity type. and (f) doping impurities using the first polycrystalline silicon region that will become the gate electrode as a mask to form a low concentration base region of one conductive bar 1 that will become the channel, and then doping the first polycrystalline silicon region that will become the gate electrode. forming a source region of an opposite conductivity type in the low-temperature base region of one conductivity type using the method as a mask.

(Function) In the following description, one conductivity type will be referred to as P type, and the opposite conductivity type will be referred to as N type. Even if the P type is replaced with the N type, or the N type is replaced with the P type, the effect is the same.

According to the manufacturing method disclosed in Book 5, the gate electrode and the N
A first polycrystalline silicon region that will serve as a mask for forming a type source region and a second polycrystalline silicon region that will serve as an impurity implantation opening region for forming a high KI Ig, P type base region are simultaneously r-'F: Pilfaline (
self-aligned).

Thereafter, a mask material is buried only between the cylinder 1 and the second polycrystalline silicon region, and a mask material having a sufficiently large opening that masks the first polycrystalline silicon region but does not mask the second polycrystalline silicon region is placed on the substrate. After stacking, only the second polycrystalline silicon region is removed to form an impurity implantation opening for the highly doped P-type base region. a high temperature P-type base region;
Compared to the conventional method in which the first polycrystalline silicon region, which will become the gate electrode, is formed individually by mask alignment, the method of the present invention eliminates the need for mask alignment, and the side surfaces of the N-type source region and the high concentration P The distance from the side surface of the type base region (for example, 1Il in FIG. 3(c)) is mainly determined by the lateral diffusion accuracy of the highly doped P-type base region. As is well known, the lateral diffusion accuracy of impurities is determined by the impurity Sufficiently high accuracy can be achieved by controlling factors such as concentration.

This increases the height of 1313I just below the source region up to the boundary between the channel region and source region in the lightly doped P-type base region.
It can be a P-type base region.

Therefore, the base resistance of the parasitic transistor can be significantly reduced without affecting the threshold voltage of the MOS FET, making it difficult for the parasitic transistor to operate and preventing destruction when the switch is turned off.

(Example) With reference to the drawings, an example of the present invention will be described below with reference to the drawings.
The OS FET will be explained.

In FIG. 1(a), a gate oxide film 5 is formed by gate oxidation on one main surface of an N-type semiconductor substrate 3. A polycrystalline silicon film is deposited thereon by LP CVD or the like. A first polycrystalline silicon region 6 on the gate oxide film, which will become a gate electrode, and a frontage spaced apart from the first polycrystalline silicon region by a predetermined distance n and for injecting impurities into a high concentration P-type base region in a later process. By selectively removing the second polycrystalline silicon region 6a and the polycrystalline silicon pattern between the two regions using PEP technology, fi=
At 1:00, it is formed in a self-aligned manner.

In the figure (b), at J3, a mask material having an etching selectivity with polycrystalline silicon, such as a resist, is applied to the entire surface, and then etching is performed, for example, by RIE (reactive ion etching), and the first polycrystalline silicon region is etched. (gate electrode)
The resist 12 is left (embedded) only between 6 and the second polycrystalline silicon region IQ (3a). It is also a desirable embodiment to use an oxide for the mask material d'3.

In <C> of the same figure, a resist 12a is applied again, and only the upper part of the second polycrystalline silicon region 6a on the semiconductor substrate, which will become a high concentration P type base region, is opened. resist 12
a masks the first polycrystalline silicon region 1 or 6, and the surface of the opening area of the resist 12a is made sufficiently large so that the upper surface of the second polycrystalline silicon region 6a is always exposed.

In the same figure (d), only the second polycrystalline silicon region 6a on the substrate, which will become the highly doped P-type base region, is heated using, for example, RfE.
By removing the opening. Next, a heavily doped P-type base region 2a is formed in the N-type semiconductor substrate 3 in the opening using ion implantation technology.

In (e) and (f) of the same figure, the remaining register t-
12 and 12a are all removed, and using the polycrystalline silicon film 6, which will become the gate electrode, as a mask, ion implantation technology is used to sequentially diffuse, for example, boron (B) and phosphorus (P) to form a low concentration P-type base, which will become the channel. A region 9 and an N-type source region 10 located within this P-type base region are formed. At this time, an N-type source region 10 is formed so that a portion of the heavily doped P-type base region 2a is exposed on the substrate surface. The highly doped P-type base region 2a is diffused and spread laterally during the formation of the lightly doped P-type base region, and the region directly below the source region up to the boundary 13 between the base region and the source region, which becomes a channel, is made up of highly doped P-type base regions. Use as base area.

Note that 1. in FIG. 1(a). The distance in between the second polycrystalline silicon regions is determined in advance in consideration of the lateral diffusion accuracy of the highly doped P-type base region and the like.

Thereafter, drain and source electrodes are formed by a known method to form a DMOS FET (11).

iii) M OS obtained by the above method
In FET-, the region immediately below the source region where the transistor action mainly takes place in the base region of the NPN parasitic transistor is heated to a high temperature I'l! This reduces the base resistance along the emitter junction of the parasitic transistor, suppresses the rise of the emitter junction bias voltage at switch-off, and reduces the current amplification factor of the parasitic transistor, reducing thermal runaway of the parasitic transistor. is prevented.

Next, a further embodiment of the present invention will be described with reference to FIG.

First, as shown in Figure 3(a), N! l! ! 4' conductor table board 3
is oxidized to form an oxide film 1, the oxide film is opened by PEP technology, and impurities are implanted to form a heavily doped P-type base region 2. Next, after diffusing impurities, the oxide film is removed, gate oxidation is performed to form a gate oxide film 5, a polycrystalline silicon film is deposited on it, and a high concentration P-type base region is formed using PEP technology. A second polycrystalline silicon region [5a] on the semiconductor substrate and a first polycrystalline silicon region 6 on the gate oxide film, which will become the gate electrode, are simultaneously formed in a self-aligned manner. After that, the same steps as those shown in FIGS. 1(b) to 1(f) are carried out, resulting in the product shown in FIG. 2.

In the embodiment shown in FIG. 2, the first formed highly doped P-type base region 2 is formed separately from the first polycrystalline silicon region 6 which will become the gate electrode.

Therefore, the distance between the side surface 7 of the first polycrystalline silicon region and the side surface 8 of the high concentration P type base region is determined by the mask alignment viscosity and the lateral diffusion viscosity of the high m concentration P type base region 2. However, the ^concentration P type base region M2a formed after that
Since the impurity implantation opening (indicated by the broken line) is formed in self-alignment with the first polycrystalline silicon region, the size of the opening is determined by considering only the lateral diffusion accuracy.
By diffusion, the area immediately below the source region up to the boundary 13 between the channel region and the source region can be made into a highly doped P-type base region.

Although the above embodiments have been described with respect to N-channel type elements, the same applies to P-channel type elements.

[Effects of the Invention] As detailed above, in the conventional technology, the highly doped P-type base region and the first polycrystalline silicon region that becomes the gate electrode are
Since they were formed individually using EP technology, the distance between the high concentration P type base region and the side surface of the source region (for example, the distance between the high concentration P type base region and the side surface of the source region) is determined by the mask alignment accuracy of the PEP technology and the lateral diffusion accuracy of the high concentration P type base region. The distance fi1m) in (c) was determined, and it was difficult to shorten this distance. However, according to the manufacturing method of the present invention, the position of the impurity injection opening for forming the highly doped P-type region is determined in a self-aligned manner with the position of the first polycrystalline silicon region on the gate oxide ridge, which becomes the gate electrode. Therefore, the distance (for example, m) between the side surface of the highly doped P-type base region and the side surface of the source region can be determined only by the lateral diffusion accuracy of the highly doped P-type base region, and the distance can be significantly shortened compared to the conventional method. Therefore, the base resistance in the region directly under the source electrode, where the parasitic transistor action mainly takes place, can be significantly reduced compared to the conventional structure. It is possible to provide a method for manufacturing a field effect transistor that can suppress and prevent thermal runaway and has a high breakdown resistance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the field effect 1 to transistor manufacturing process of the present invention, FIG. 2 is a cross-sectional view showing another embodiment of the field effect 1 to transistor manufacturing process of the present invention, and FIG. The figure shows the conventional 1.6 field effect i~ transistor! 8! FIG. 3 is a cross-sectional view showing the manufacturing process. DESCRIPTION OF SYMBOLS 1... Oxide film, 2, 2a... One conductivity type high impurity temperature region (high concentration P type base region), 3... Semiconductor substrate (N type drain region), 4... Oxide film, 5
... Goo 1 - Insulating film (gate M film), 6... First polycrystalline silicon region (gate electrode), 6a... Second polycrystalline silicon region, 7... First polycrystalline silicon region Silicon region side surface, 8...High concentration P type base region side surface, 9.
...One conductivity type base region (low temperature P type base region), 1
0... Opposite conductivity type source region (N type source region), 1
1...NPN type parasitic transistor, 12°128
. . . Mask material (for example, resist) with etching selectivity to polycrystalline silicon, 13 . . . Side surface of N-type source region. Figure 1 (1) (d)
Ion implantation Figure 1 (2) Figure 2 Figure 3 (1) Figure 3 (2)

Claims (1)

[Claims] 1 (a) a step of depositing a polycrystalline silicon film on a semiconductor substrate via a gate insulating film; (b) selectively etching the polycrystalline silicon film,
(c) dividing the first polycrystalline silicon region into a first polycrystalline silicon region that will become a gate electrode and a second polycrystalline silicon region spaced apart from the first polycrystalline silicon region by a predetermined distance; embedding a mask material between the polycrystalline silicon region; (d) selectively removing and opening only the second polycrystalline silicon region; and (e) doping impurities from the opening to remove the semiconductor. (f) forming a base region of one conductivity type in the semiconductor substrate by doping impurities using the first polycrystalline silicon region as a mask; and (f) forming a base region of one conductivity type in the semiconductor substrate. forming source regions of opposite conductivity type located within the respective regions. 2. The method of manufacturing a field effect transistor according to claim 1, wherein the mask material buried between the first polycrystalline silicon region and the second polycrystalline silicon region is a resist. 3. The method of manufacturing a field effect transistor according to claim 1, wherein the mask material buried between the first polycrystalline silicon region and the second polycrystalline silicon region is an oxide.