CN110400834B - non-Snapback effect reverse-conducting IGBT and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000000694 effects Effects 0.000 title abstract description 10
- 230000002441 reversible effect Effects 0.000 claims abstract description 120
- 230000015556 catabolic process Effects 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- -1 phosphorus ion Chemical class 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 11
- 238000011084 recovery Methods 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 7
- 238000005265 energy consumption Methods 0.000 description 4
- YBJHBAHKTGYVGT-ZKWXMUAHSA-N (+)-Biotin Chemical compound N1C(=O)N[C@@H]2[C@H](CCCCC(=O)O)SC[C@@H]21 YBJHBAHKTGYVGT-ZKWXMUAHSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- FEPMHVLSLDOMQC-UHFFFAOYSA-N virginiamycin-S1 Natural products CC1OC(=O)C(C=2C=CC=CC=2)NC(=O)C2CC(=O)CCN2C(=O)C(CC=2C=CC=CC=2)N(C)C(=O)C2CCCN2C(=O)C(CC)NC(=O)C1NC(=O)C1=NC=CC=C1O FEPMHVLSLDOMQC-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
Abstract
The invention relates to a semiconductor technology, in particular to a reverse conducting IGBT without snapback effect and a manufacturing method thereof. The main scheme of the invention is to improve the collector structure on the back of the IGBT, reduce the reverse blocking voltage of the device as much as possible by optimizing the doping concentration and thickness of the P + + collector region and the N + + layer, and realize reverse conduction by utilizing the avalanche breakdown effect and the tunnel breakdown effect in a reverse blocking mode. Compared with the conventional reverse conducting IGBT, the novel reverse conducting IGBT provided by the invention does not generate snapback phenomenon during forward conducting because the N + short circuit area does not exist and the conversion from the MOSFET conducting mode to the IGBT conducting mode does not exist during forward conducting. The novel reverse conducting IGBT provided by the invention has larger reverse conducting threshold voltage than the conventional reverse conducting IGBT, so that the novel reverse conducting IGBT is suitable for the condition that the forward conducting time is most and the reverse conducting time is shorter, such as a quasi-resonant circuit. In addition, the novel reverse conducting IGBT provided by the invention also has the advantages of small forward conducting voltage drop, good soft recovery characteristic and the like.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a Snapback effect-free reverse conducting IGBT and a manufacturing method thereof.
Background
Insulated Gate Bipolar Transistors (IGBTs) are composite devices developed in the 80 s, and the MOSFET is used for driving the bipolar transistors, so that the bipolar transistors have the advantages of high input impedance and low conduction voltage drop which are common to the MOSFET and the BJT, and are widely applied to medium-frequency and medium-power electricity. However, since the IGBT does not have the reverse conduction capability, in the application of the inductive load, a Fast Recovery Diode (FRD) needs to be connected in parallel in the reverse direction to provide the follow current protection.
Because parasitic inductance is easily introduced into the IGBT and the FRD during welding, the practical IGBT is high in application cost and poor in reliability, people integrate the IGBT and the FRD on the same chip to develop a Reverse Conducting insulated gate bipolar transistor (Reverse Conducting-IGBT for short), a collector short circuit structure is adopted, and an N + region and a P + region which are arranged in parallel and alternately are formed through back photoetching. When the emitter is applied with positive bias and the collector is applied with zero bias, a PN junction formed by the P-type base region-N-drift region-N + short circuit region is in a forward bias state, so that the device is conducted reversely. However, the inherent structure causes the device to have a transition from the MOSFET conduction mode to the IGBT conduction mode when conducting in the forward direction, which is expressed as a snapback phenomenon (i.e., a voltage rebound phenomenon) that aggravates current concentration and directly affects the reliability of the device. In addition, since the FRD is only integrated in a partial region, current distribution is easily uneven when conducting in a reverse direction, which also affects reliability of the device.
The reverse conduction function can be realized by introducing a tunnel diode into the back of a conventional IGBT, a positive bias voltage is applied to an emitter, when a zero bias voltage is applied to a collector, the tunnel diode formed by a P + + collector/N + + region is in a reverse bias state, the energy band of a potential barrier region is more inclined along with the increase of the voltage of the emitter, and when the built-in electric field is increased to a certain degree, a large number of electrons can directly pass through a forbidden band from a valence band and enter a conduction band, so that the reverse conduction is realized. However, the doping concentration of the P + +/N + + region constituting the tunnel diode is very high, reaching 1 × 1020cm-3～1×1021cm-3The difficulty of the process is very high, and when the IGBT is conducted in the forward direction, the tunnel diode conduction mode is changed into the IGBT conduction mode, so that the snapback phenomenon also occurs.
In the conventional field stop type IGBT, due to the presence of the N + field stop layer, in the forward blocking mode, the electric field rapidly drops to 0 in the N + field stop layer, the electric field exhibits a trapezoidal distribution, and thus the thickness of the drift region can be reduced to achieve the same level of withstand voltage. The doping concentration of the N + field stop layer is typically 1X 1015cm-3～1×1016cm-3Since the reverse blocking voltage is usually several tens to several hundreds of volts, the field stop type IGBT does not have reverse conductionThe ability of the cell to perform.
Disclosure of Invention
The invention aims to provide a novel reverse conducting IGBT without snapback effect and a manufacturing method thereof aiming at the problems of snapback phenomenon existing in the forward conducting process of the traditional RC-IGBT and the situation that the requirement on the reverse conducting characteristic of the device is not strict due to the asymmetric forward and reverse conducting time of the device.
In order to achieve the purpose, the invention adopts the following technical scheme:
a novel snapback effect-free reverse conducting IGBT is shown in figure 1 and comprises a collector structure, a drift region structure, a grid structure and an emitter structure;
the collector structure comprises a P + + collector region 10 and a metalized collector 10 positioned on the lower surface of the P + + collector region 10;
the drift region structure comprises an N + + layer 9, an N + field stop layer 8 and an N-drift region layer 1, wherein the N + + layer 9 and the N + field stop layer 8 are arranged in parallel, and the N-drift region layer 1 is positioned on the upper surfaces of the N + + layer 9 and the N + field stop layer 8;
the grid structure is a trench grid and is embedded into two ends of the upper surface of the N-drift region layer 1, and the grid structure comprises a grid oxide layer 7 and a polycrystalline silicon grid electrode 6 positioned in the grid oxide layer 7;
the emitter structure is positioned between two trench gates and comprises an N + emitter region 5, a P-type base region 3, a P + contact region 2 and a metalized emitter 4, wherein the P-type base region 3 is embedded in the upper surface of the N-drift region layer 1, the N + emitter region 5 is positioned on the upper layer of the P-type base region 3 and is contacted with the trench gates, the P + contact region 2 is positioned in the P-type base region 3 and is positioned between the N + emitter regions 5 on two sides, and two ends of the P + contact region 2 also extend to the lower surface of the N + emitter region 5; the junction depth of the P + contact region 2 is greater than that of the N + emission region 5; a metalized emitter 4 is located on the upper surface of the N + emitter region 5 and the P + contact region 2, the metalized emitter 4 only covering a portion of the N + emitter region 5.
The main scheme of the invention mainly relates to a back collector structure of the IGBT, and reverse conduction is realized by utilizing avalanche breakdown of a P + + collector region and an N + + layer by optimizing the doping concentrations of the P + + collector region and the N + + layer.
In the conventional reverse conducting IGBT, the structural schematic diagram is as shown in fig. 2, and the doping concentration of the N + field stop layer 8 is about 1 × 1015cm-3～1×1016cm-3This is because when the doping concentration of the N + field stop layer 8 is too high, the rebound voltage V of the devicesnapbackLarge enough to adversely affect the reliability of the device. When the conventional reverse-conducting IGBT is conducted in the forward direction, due to the existence of the N + short-circuit area, the device firstly enters the MOSFET working mode, the device gradually enters the IGBT conducting mode along with the increase of forward-conducting current, the N-drift area 1 generates conductance modulation, and voltage rebound (snapback) occurs.
An IGBT structure in which a tunnel diode is introduced at the back side to realize reverse conduction is shown in fig. 3, and in this structure, the doping concentration of a P + + collector 10 and an N + + layer 9 is 1 × 1020cm-3～1×1021cm-3Further, due to the characteristics of the tunnel diode, the IGBT is shifted from the tunnel diode conduction mode to the IGBT conduction mode when conducting in the forward direction, and thus the snapback phenomenon also occurs.
The structure of the conventional FS-IGBT is shown in FIG. 4, wherein the doping concentration of the N + field stop layer is usually 1 × 1015cm-3～1×1016cm-3Therefore, the reverse blocking voltage of the device is usually several tens volts to several hundreds volts, and thus the FS-IGBT does not have the capability of reverse conduction.
The novel reverse conducting IGBT provided by the invention has the structure as shown in figure 1, reverse conduction is realized by utilizing avalanche breakdown of a P + + collector region and an N + + field stop layer, and the doping concentrations of the P + + collector region 9 and the N + + layer 9 are 1 multiplied by 1017cm-3～1×1019cm-3The doping concentration of the N + field stop layer 8 is 1 × 1015cm-3～1×1016cm-3The forward conduction characteristic is similar to that of the conventional FS-IGBT, and the conduction mode does not change, so that the snapback phenomenon cannot occur when the novel reverse-conducting IGBT provided by the invention is in forward conduction.
The specific embodiment of the invention is explained by taking the design of a trench gate reverse conducting type IGBT half cell with the voltage resistance of 1200V as an example, and the method comprises two manufacturing methods, wherein the first manufacturing method is to form an N + field stop layer and an N + + layer by two times of ion implantation, and comprises the following steps:
the first step is as follows: the doping concentration was selected to be 5e13cm-3The N-type silicon wafer is used as a substrate silicon wafer, namely an N-type semiconductor drift region 1 in the structure, and an N + field stop layer 8 is formed on the back surface of an N-drift region layer 1 through phosphorus ion injection and junction pushing;
the second step is that: then, forming an N + + layer 9 by one-time phosphorus ion implantation and knot pushing;
the third step: and growing gate oxide of 100nm, namely a gate oxide layer 7 on the upper surface of the N-drift region layer 1, and then depositing polycrystalline silicon to form a polycrystalline silicon gate electrode 6.
The fourth step: injecting P-type impurities into the N-drift region layer 1 and performing junction pushing to form a P-type base region 3;
the fourth step: injecting N-type impurities into the P-type base region 3 to form an N + emitter region 5;
and a sixth step: injecting a P-type impurity into the P-type base region 3 and performing junction pushing to form a P + contact region 2;
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;
eighth step: depositing metal on the upper surface of the N + emission region 5 to form cathode metal 4, wherein the cathode metal 4 only covers part of the N + emission region 5, and the cathode metal 4 simultaneously covers the P + contact region 2;
the ninth step: depositing a passivation layer;
the tenth step: injecting P-type impurities into the back surface and carrying out ion activation to form a P + + collector region 10;
the eleventh step: and back metallization, and forming a metallized collector 10 on the lower surface of the P + + collector region 10.
The second manufacturing method is to implant boron ions into part of the N + + layer and push the junction, and perform impurity compensation to form an N + field stop layer, and the steps are as follows:
the first step is as follows: the doping concentration was selected to be 5e13cm-3The N-type silicon wafer is used as a substrate silicon wafer, namely an N-type semiconductor drift region 1 in the structure, and an N + + layer 9 is formed on the back surface of an N-drift region layer 1 through phosphorus ion implantation and knot pushing;
the second step is that: performing impurity compensation on the N + + layer to form an N + layer 8 by injecting boron ions once and pushing the junction;
the third step: and growing gate oxide of 100nm, namely a gate oxide layer 7 on the upper surface of the N-drift region layer 1, and then depositing polycrystalline silicon to form a polycrystalline silicon gate electrode 6.
The fourth step: injecting P-type impurities into the N-drift region layer 1 and performing junction pushing to form a P-type base region 3;
the fourth step: injecting N-type impurities into the P-type base region 3 to form an N + emitter region 5;
and a sixth step: injecting a P-type impurity into the P-type base region 3 and performing junction pushing to form a P + contact region 2;
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;
eighth step: depositing metal on the upper surface of the N + emission region 5 to form cathode metal 4, wherein the cathode metal 4 only covers part of the N + emission region 5, and the cathode metal 4 simultaneously covers the P + contact region 2;
the ninth step: depositing a passivation layer;
the tenth step: injecting P-type impurities into the back surface and carrying out ion activation to form a P + + collector region 10;
the eleventh step: and back metallization, and forming a metallized collector 10 on the lower surface of the P + + collector region 10.
The invention has the beneficial effects that aiming at the condition that the forward and reverse conduction time is asymmetric, so that the requirement on the reverse conduction characteristic of a device is not strict, the novel reverse conducting IGBT without snapback effect is provided, and has the advantages of low cost, simple process, good forward conduction characteristic, good soft recovery characteristic and the like.
Drawings
Fig. 1 is a schematic structural diagram of a novel trench gate type reverse conducting IGBT cell according to the present invention.
Fig. 2 is a schematic structural diagram of a conventional trench gate type reverse conducting IGBT cell.
Fig. 3 is a schematic diagram of an IGBT cell structure in which reverse conduction is achieved by introducing a tunnel diode at the back side.
FIG. 4 is a schematic diagram of a cell structure of a conventional FS-IGBT.
Fig. 5 shows the doping profile near the collector of the novel trench gate type reverse conducting IGBT of the present invention, the conventional FS-IGBT, and the IGBT realizing reverse conduction using a tunnel diode.
Fig. 6 is a forward conduction characteristic curve of the novel reverse conducting IGBT of the present invention, the conventional reverse conducting IGBT, and the IGBT which achieves reverse conduction by introducing a tunnel diode.
Fig. 7 is reverse conduction characteristic curves of the novel reverse conducting IGBT, the conventional reverse conducting IGBT, the IGBT which introduces the tunnel diode to realize reverse conduction, and the conventional FS-IGBT according to the present invention.
Fig. 8 is a graph illustrating the electric field, impact ionization rate and tunnel generation rate at the P + +/N + + junction when the novel reverse conducting IGBT and the IGBT introducing the tunnel diode according to the present invention realize reverse conduction.
Fig. 9 is a graph of reverse blocking voltage of the novel reverse conducting IGBT of the present invention as a function of N + layer concentration.
FIG. 10 is a double pulse circuit for reflecting the reverse recovery characteristics of the device
Fig. 11 is a reverse recovery characteristic curve of the conventional reverse conducting IGBT and the novel reverse conducting IGBT of the present invention.
Fig. 12 is a single-ended quasi-resonant circuit for use in an induction cooker.
Fig. 13 is a comparison graph of current and voltage for a single-ended quasi-resonant circuit using a conventional reverse conducting IGBT and a novel reverse conducting IGBT of the present invention, respectively.
Fig. 14 is a comparison graph of currents flowing through the resonant capacitor and the resonant inductor when the conventional reverse conducting IGBT and the novel reverse conducting IGBT of the present invention are applied to the quasi-resonant circuit, respectively.
Fig. 15 is a process flow diagram of a first method of manufacture.
Fig. 16 is a process flow diagram of a second manufacturing method.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
the structure of the novel snapback effect-free reverse conducting IGBT is shown in figure 1 and comprises a collector electrode structure, a drift region structure, an emitter electrode structure and a grid electrode structure; the collector structure comprises a P + + collector region 10 and a metalized collector 10 positioned on the lower surface of the P + + collector region 10; the drift region structure comprises an N + + layer 9, an N + field stop layer 8 and an N-drift region layer 1 positioned on the upper surfaces of the N + + layer 9 and the N + field stop layer 8, wherein the N + + layer 8 and the N + field stop layer 8 are arranged on the upper surface of a P + + collector region 10 in parallel; the grid structure is a trench grid and is embedded in the upper surface of the N-drift region layer 1, and the grid structure comprises a grid oxide layer 7 and a polycrystalline silicon grid electrode 6 positioned in the grid oxide layer 7; the emitter structure is positioned between two trench gates and comprises an N + emitter region 5, a P-type base region 3, a P + contact region 2 and a metalized emitter 4, wherein the P-type base region 3 is embedded in the upper surface of the N-drift region layer 1, the N + emitter region 5 is positioned on the upper layer of the P-type base region 3, and the P + contact region 2 is positioned in the P-type base region 3 and is arranged in parallel with the N + emitter region 5; the junction depth of the P + contact region 2 is greater than that of the N + emission region 5; a metalized emitter 4 is located on the upper surface of the N + emitter region 5 and the P + contact region 2, the metalized emitter 4 only covering a portion of the N + emitter region 5.
The novel snapback effect-free reverse conducting IGBT provided by the invention has the following working principle:
when forward conduction is performed, a forward bias is applied to the polysilicon gate electrode 6 in the cell shown in fig. 1, electrons in the P-type base region 3 are accumulated on the gate oxide layer side, inversion occurs in the channel, and an N-type electron channel connecting the N + emitter region 5 and the N-drift region layer 1 is formed. A positive voltage is applied to the metallized collector 10 and zero potential is applied to the metallized emitter 4. An electron current flows into the N-drift region layer 1 from the N + emitter region 5 through an N-type electron channel to provide base driving current for a PNP transistor formed by the P-type base region 3, the N-drift region layer 1 and the P + + collector region 10, and after the PNP transistor is started, a large number of holes are injected into the N-drift region layer 1 by the P + + collector region 10 to form conductance modulation, so that the IGBT is conducted in the forward direction. Compared with the conventional reverse-conducting IGBT (the structure is shown in figure 2), the novel reverse-conducting IGBT does not have an N + short circuit area, so that when the device is conducted in the forward direction, the device does not have the conversion from the MOSFET conduction mode to the IGBT conduction mode, so that the novel reverse-conducting IGBT does not generate the snapback phenomenon, and the forward conduction characteristic curves of the conventional reverse-conducting IGBT, the novel reverse-conducting IGBT and the IGBT utilizing the tunnel diode to realize reverse conduction are shown in figure 6.
When the device is conducted reversely, a zero potential is applied to the polycrystalline silicon gate electrode 6, a positive voltage is applied to the metalized emitter 4, a zero potential is applied to the metalized collector 10, the device is in a reverse blocking mode, the emitter voltage is supported by a PN junction formed by the P + + collector region 10 and the N + + layer 9, along with the increase of the emitter-collector voltage, a depletion region at the PN junction formed by the P + + collector region 10 and the N + + layer 9 is expanded, and an electric field is enhanced. When the emitter-collector voltage is increased to the breakdown voltage of the PN junction, the PN junction breaks down to generate a large number of electron-hole pairs in the space charge region to realize reverse conduction, and the reverse conduction characteristic curves of the conventional reverse conducting IGBT, the novel reverse conducting IGBT of the present invention, and the IGBT and FS-IGBT which realize reverse conduction by using the tunnel diode are shown in fig. 7.
The specific embodiment of the invention is explained by taking the design of a trench gate reverse conducting type IGBT half cell with the voltage resistance of 1200V as an example, and the method comprises two manufacturing methods, wherein the first manufacturing method is to form an N + field stop layer and an N + + layer by two times of ion implantation, and comprises the following steps:
the first step is as follows: the doping concentration was selected to be 5e13cm-3The N-type silicon wafer is used as a substrate silicon wafer, namely an N-type semiconductor drift region 1 in the structure, and an N + field stop layer 8 is formed on the back surface of an N-drift region layer 1 through phosphorus ion injection and junction pushing;
the second step is that: then, forming an N + + layer 9 by one-time phosphorus ion implantation and knot pushing;
the third step: and growing gate oxide of 100nm, namely a gate oxide layer 7 on the upper surface of the N-drift region layer 1, and then depositing polycrystalline silicon to form a polycrystalline silicon gate electrode 6.
The fourth step: injecting P-type impurities into the N-drift region layer 1 and performing junction pushing to form a P-type base region 3;
the fourth step: injecting N-type impurities into the P-type base region 3 to form an N + emitter region 5;
and a sixth step: injecting a P-type impurity into the P-type base region 3 and performing junction pushing to form a P + contact region 2;
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;
eighth step: depositing metal on the upper surface of the N + emission region 5 to form cathode metal 4, wherein the cathode metal 4 only covers part of the N + emission region 5, and the cathode metal 4 simultaneously covers the P + contact region 2;
the ninth step: depositing a passivation layer;
the tenth step: injecting P-type impurities into the back surface and carrying out ion activation to form a P + + collector region 10;
the eleventh step: and back metallization, and forming a metallized collector 10 on the lower surface of the P + + collector region 10.
The second manufacturing method is to form an N + field stop layer by performing impurity compensation on the N + + layer, and includes the steps of:
the first step is as follows: the doping concentration was selected to be 5e13cm-3The N-type silicon wafer is used as a substrate silicon wafer, namely an N-type semiconductor drift region 1 in the structure, and an N + + layer 9 is formed on the back surface of an N-drift region layer 1 through phosphorus ion implantation and knot pushing;
the second step is that: performing impurity compensation on the N + + layer to form an N + layer 8 by injecting boron ions once and pushing the junction;
the third step: and growing gate oxide of 100nm, namely a gate oxide layer 7 on the upper surface of the N-drift region layer 1, and then depositing polycrystalline silicon to form a polycrystalline silicon gate electrode 6.
The fourth step: injecting P-type impurities into the N-drift region layer 1 and performing junction pushing to form a P-type base region 3;
the fourth step: injecting N-type impurities into the P-type base region 3 to form an N + emitter region 5;
and a sixth step: injecting a P-type impurity into the P-type base region 3 and performing junction pushing to form a P + contact region 2;
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;
eighth step: depositing metal on the upper surface of the N + emission region 5 to form cathode metal 4, wherein the cathode metal 4 only covers part of the N + emission region 5, and the cathode metal 4 simultaneously covers the P + contact region 2;
the ninth step: depositing a passivation layer;
the tenth step: injecting P-type impurities into the back surface and carrying out ion activation to form a P + + collector region 10;
the eleventh step: and back metallization, and forming a metallized collector 10 on the lower surface of the P + + collector region 10.
The novel reverse conducting IGBT structure provided by the invention is compared with a conventional reverse conducting IGBT structure in a simulation mode, and the superiority of the structure is further verified. The conventional reverse conducting IGBT structure is shown in figure 2, the novel reverse conducting IGBT structure provided by the invention is shown in figure 1, the cell thickness of the device is 100um, and the ratio of an N + short circuit region 10 to a P + collector region 9 in the conventional reverse conducting IGBT structure is 1: 5.
As shown in FIG. 6, the forward conduction characteristic of the novel reverse conducting IGBT provided by the invention is superior to that of the conventional reverse conducting IGBT and the IGBT for realizing reverse conduction by utilizing a tunnel diode, the conventional reverse conducting IGBT has obvious snapback effect, and the rebound voltage V isSB8.8V; the IGBT which utilizes the tunnel diode to realize reverse conduction also shows obvious snapback phenomenon; the novel reverse conducting IGBT provided by the invention has no voltage rebound phenomenon. The forward conduction current density was 100A/cm2During the process, the forward conduction voltage drop of the conventional reverse conducting IGBT is about 1.19V, and the forward conduction voltage drop of the reverse conducting IGBT provided by the invention is about 1.05V, which is reduced by 11.8 percent, because the area of the effective current collection area is larger in the invention.
As shown in fig. 7, when Vce is-5V, the novel reverse conducting IGBT device according to the present invention realizes reverse conduction, that is, a PN junction formed by the P + + collector region 10 and the N + + layer 9 is broken down to generate a large number of electron-hole pairs, since the P + + collector region 10 and the N + + layer 9 are both heavily doped, a peak electric field Emax during breakdown is about 1.25e6V/cm, and as shown in fig. 8, the PN junction breakdown includes both avalanche breakdown and tunnel breakdown, but mainly avalanche breakdown. As can be seen from the mechanism of junction breakdown, reverse conduction can be achieved as long as Vce is maintained at-5V. In the IGBT which uses the tunnel diode to realize reverse conduction, tunnel breakdown is the main factor, and since the barrier region is thin, even if the electric field is strong, the carriers are accelerated in the barrier region to the kinetic energy which is not necessary for generating the multiplication effect, and avalanche breakdown cannot be generated. For the conventional FS-IGBT, the reverse blocking voltage reaches about 300V, so that the conventional FS-IGBT does not have the reverse conduction capability.
Fig. 9 shows a variation curve of reverse blocking voltage along with the doping concentration of the N + field stop layer in the novel reverse conducting IGBT according to the present invention, where the doping concentration of the N + field stop layer should be increased to reduce the reverse blocking voltage of the device, so that the device undergoes avalanche breakdown at a lower emitter voltage. Therefore, in the novel reverse conducting IGBT provided by the invention, the doping concentration of the P + + collector region 10 and the N + + layer 9 should reach 1 × 1017cm-3～1×1019cm-3The reverse conduction is realized mainly by means of the avalanche breakdown effect.
The double pulse circuit shown in fig. 10 can be used to reflect the reverse recovery characteristic of the IGBT1, that is, the process of extracting excess carriers in the drift region when the IGBT1 is switched from the reverse conducting mode to the forward blocking mode. Rate of reverse current decline [ dJ/dt ]]RA large potential is generated in the circuit inductance which is superimposed on the supply voltage, causing a voltage overshoot. This phenomenon can be measured by the softness factor S, the larger S, the lower the reverse current rate [ dJ/dt ]]RThe smaller, S>0.8 can judge that the device has the characteristic of soft recovery. As can be seen from fig. 11, the softness factor S of the novel reverse conducting IGBT proposed by the present invention is about 10, and has good soft recovery characteristics.
Fig. 12 is a single-ended quasi-resonant circuit commonly used in electromagnetic ovens, where a periodic current flows through an inductor by controlling the turn-on and turn-off of an IGBT in the circuit, creating an alternating magnetic field. Fig. 13 is a change curve of the collector current Ic and the collector-emitter voltage Vce of the IGBT obtained by applying the conventional reverse conducting IGBT and the novel reverse conducting IGBT proposed by the present invention to the quasi-resonant circuit shown in fig. 12, respectively, and it can be known from comparison that the novel reverse conducting IGBT proposed by the present invention can replace the application of the conventional reverse conducting IGBT to the quasi-resonant circuit, and can generate a periodically changing current on the resonant inductor Lr. As can be seen from fig. 14, the forward conduction time in one period is 46.5%, and the reverse conduction time is only about 13%, so that the energy consumption of the device in one period is mainly determined by the two processes of forward conduction and turn-off, and the energy consumption generated in the reverse conduction process is very small, so that although the threshold voltage of the reverse conduction of the novel reverse conduction IGBT provided by the present invention is relatively large, the reverse conduction time is short, and the reverse conduction current is small, so that too much energy consumption is not caused.
In summary, compared with the conventional reverse conducting IGBT, the novel reverse conducting IGBT provided by the invention does not generate Snapback phenomenon when conducting in the forward direction, and has better forward conducting characteristic, and although the threshold voltage of reverse conducting is larger, in applications such as quasi-resonant circuits, in which the forward conducting time is the most, too much extra energy consumption is not brought. In addition, the novel reverse conducting IGBT provided by the invention has the characteristic of better soft recovery characteristic.
Claims (4)
1. A Snapback effect-free reverse conducting IGBT comprises a collector electrode structure, a drift region structure, a grid electrode structure and an emitter electrode structure;
the collector structure comprises a P + + collector region (10) and a metalized collector (11) positioned on the lower surface of the P + + collector region (10);
the drift region structure comprises an N + + layer (9), an N + field stop layer (8) and an N-drift region layer (1), wherein the N + + layer and the N + field stop layer (8) are arranged in parallel, the N-drift region layer (1) is positioned on the upper surfaces of the N + + layer (9) and the N + field stop layer (8), and the N + + layer (9) and the N + field stop layer (8) are positioned on the upper surface of a P + + collector region (10);
the gate structure is a trench gate and is embedded at two ends of the upper surface of the N-drift region layer (1), and the structure comprises a gate oxide layer (7) and a polysilicon gate electrode (6) positioned in the gate oxide layer (7);
the emitter structure is positioned between two trench gates and comprises an N + emitter region (5), a P-type base region (3), a P + contact region (2) and a metalized emitter (4), wherein the P-type base region (3) is embedded in the upper surface of the N-drift region layer (1), the N + emitter region (5) is positioned on the upper layer of the P-type base region (3) and is contacted with the trench gates, the P + contact region (2) is positioned in the P-type base region (3) and is positioned between the N + emitter regions (5) at two sides, and two ends of the P + contact region (2) also extend to the lower surface of the N + emitter region (5); the junction depth of the P + contact region (2) is greater than that of the N + emission region (5); the metalized emitter (4) is positioned on the upper surfaces of the N + emitting region (5) and the P + contact region (2), and the metalized emitter (4) only covers a part of the N + emitting region (5).
2. The Snapback-effect-free reverse conducting IGBT according to claim 1, characterized in that reverse conduction is realized by avalanche breakdown of the P + + collector region (10) and the N + + layer (9), the concentration of the P + + collector region (10) being 1 x 1017cm-3～1×1019cm-3The junction depth is 0.5-1 um; the doping concentration of the N + field stop layer (8) is 1 multiplied by 1015cm-3～1×1016cm-3The junction depth is 2-5 um; the doping concentration of the N + + layer (9) is 1 x 1017cm-3～1×1019cm-3Deep and connected withThe N + field stop layers (8) are the same and are 2-5 um.
3. The manufacturing method of the Snapback effect-free reverse conducting IGBT according to claim 1, characterized by comprising the following steps:
the first step is as follows: the doping concentration was selected to be 5e13cm-3The N-type silicon wafer is used as a substrate silicon wafer, namely an N-drift region layer (1) in the structure, and an N + field stop layer (8) is formed on the back surface of the N-drift region layer (1) through phosphorus ion injection and junction pushing;
the second step is that: then, a phosphorus ion implantation is carried out once and junction pushing is carried out to form an N + + layer (9);
the third step: growing gate oxide of 100nm, namely a gate oxide layer (7), on the upper surface of the N-drift region layer (1), and then depositing polycrystalline silicon to form a polycrystalline silicon gate electrode (6);
the fourth step: injecting P-type impurities into the N-drift region layer (1) and performing junction pushing to form a P-type base region (3);
the fourth step: injecting N-type impurities into the P-type base region (3) to form an N + emitter region (5);
and a sixth step: injecting a P-type impurity into the P-type base region (3) and performing junction pushing to form a P + contact region (2);
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;
eighth step: depositing metal on the upper surface of the N + emitting region (5) to form a metalized emitter (4), covering part of the N + emitting region (5) only, and simultaneously covering the metalized emitter (4) on the P + contact region (2);
the ninth step: depositing a passivation layer;
the tenth step: injecting P-type impurities into the back surface and carrying out ion activation to form a P + + collector region (10);
the eleventh step: and back metallization is carried out, and a metallized collector (11) is formed on the lower surface of the P + + collector region (10).
4. The manufacturing method of the Snapback effect-free reverse conducting IGBT according to claim 1, characterized by comprising the following steps:
the first step is as follows: the doping concentration was selected to be 5e13cm-3As an N-type silicon waferA substrate silicon wafer, namely an N-drift region layer (1) in the structure, firstly, injecting phosphorus ions on the back of the N-drift region layer (1) and performing junction pushing to form an N + + layer (9);
the second step is that: performing impurity compensation on the N + + layer by injecting boron ions once and pushing the junction to form an N + field stop layer (8);
the third step: growing gate oxide of 100nm, namely a gate oxide layer (7), on the upper surface of the N-drift region layer (1), and then depositing polycrystalline silicon to form a polycrystalline silicon gate electrode (6);
the fourth step: injecting P-type impurities into the N-drift region layer (1) and performing junction pushing to form a P-type base region (3);
the fourth step: injecting N-type impurities into the P-type base region (3) to form an N + emitter region (5);
and a sixth step: injecting a P-type impurity into the P-type base region (3) and performing junction pushing to form a P + contact region (2);
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;
eighth step: depositing metal on the upper surface of the N + emitting region (5) to form a metalized emitter (4), covering part of the N + emitting region (5) only, and simultaneously covering the metalized emitter (4) on the P + contact region (2);
the ninth step: depositing a passivation layer;
the tenth step: injecting P-type impurities into the back surface and carrying out ion activation to form a P + + collector region (10);
the eleventh step: and back metallization is carried out, and a metallized collector (11) is formed on the lower surface of the P + + collector region (10).
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| US5981981A (en) * | 1993-10-13 | 1999-11-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a bipolar structure |
| JP2008181975A (en) * | 2007-01-23 | 2008-08-07 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| CN101378073A (en) * | 2007-08-30 | 2009-03-04 | 东部高科股份有限公司 | Insulated gate bipolar transistor and method for manufacturing the same |
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