KR100671614B1 - High voltage transistor in flash memory device - Google Patents

Abstract

The present invention relates to a high voltage transistor of a flash memory device, wherein the active width of the junction is narrower than the channel width, or the junction is bent to increase the junction resistance, thereby increasing the snapback knee voltage, and thereby the junction is bent. The space can be efficiently used, and metal contacts can be formed at different positions from the gate, and the junction resistance can be freely adjusted through the metal wiring, thereby implementing a variety of high voltage transistors.

NAND Flash, High Voltage Transistor, Snapback Knee Voltage, Junction Resistance

Description

High voltage transistor in flash memory device             

1 is a graph showing snapback characteristics of a high voltage NMOS transistor with a change in drain current with respect to a drain voltage;

2 is a cross-sectional view of a typical bipolar junction transistor;

3 is an equivalent circuit diagram of FIG. 2;

4 is a graph showing the snapback characteristics of a high voltage NMOS transistor against a change in the snapback knee voltage with respect to the space between the contact and the gate;

FIG. 5 is a plan view of a high voltage NMOS transistor of concern for snapback due to area penalty; FIG.

6 is a graph showing the change in active junction resistance with respect to active width;

7 is a plan view of a high voltage transistor of a flash memory device according to the first embodiment of the present invention;

8 is a plan view of a high voltage transistor of a flash memory device according to a second embodiment of the present invention;

9 is a plan view of a high voltage transistor of a flash memory device according to a third embodiment of the present invention;

10 is a plan view of a high voltage transistor of a flash memory device according to the fourth embodiment of the present invention;

11 is a plan view of a high voltage transistor of a flash memory device according to the fifth embodiment of the present invention;

12 is a plan view of a high voltage transistor of a flash memory device according to the sixth embodiment of the present invention;

13 is a plan view of a high voltage transistor of a flash memory device according to the seventh embodiment of the present invention; And

14 is a plan view of a high voltage transistor of a flash memory device according to an eighth embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

71, 81, 91, 101, 111, 121, 131, 141: gate

72, 82, 92, 102, 112, 122, 132, 142: first junction

73, 83, 93, 103, 113, 123, 133, 143: second junction

74, 84, 94, 104, 114, 124, 134, 144: first metal contact

75, 85, 95, 105, 115, 125, 135, 145: second metal contact

76, 86, 96, 106, 116, 126, 136, 146: third metal contact

77, 87, 97, 107, 117, 127, 137, 147: first metal wiring                 

78, 88, 98, 108, 118, 128, 138, 148: second metal wiring

79, 89, 99, 109, 119, 129, 139, 149: third metal wiring

The present invention relates to a high voltage transistor of a flash memory device, and more particularly, to a high voltage transistor of a flash memory device capable of improving snapback knee voltage that may occur under operating conditions of a NAND flash memory device. It is about.

High-voltage NMOS transistors used in NAND flash cannot be made in TP / P-wells, such as in NOR flash, because high voltages above 20V must be carried to the cell area during programming and erasing. P-Well's BVDSS cannot be used in NAND flash, which uses more than 20V, about 18V. For this purpose, a gate oxide film having an effective oxide thickness (Tox) of about 350 kW is used, and buffering between the high voltage NMOS transistor region and the external well is introduced. It also requires the distance between the metal contacts and the gate to be greater than that used at conventional Vcc levels to have BVDSS and DJBV above 20V. In NAND flash, the distance between a metal contact and a gate is about 0.6 mu m in the case of a high voltage NMOS transistor. If it is closer than this, DJBV and BVDSS occur as shown in FIG. 1 during the operation of the high voltage NMOS transistor. This is called a snapback phenomenon or a bipolar action, which can cause damage to high voltage NMOS transistors or peripheral circuits. FIG. 1 is a graph illustrating HVN snapback characteristics of a high voltage NMOS transistor with respect to a change in the drain current ID with respect to the drain voltage VD.

In order for a snapback phenomenon to occur in a high voltage NMOS transistor of a NAND flash memory device, first, a high voltage NMOS transistor must be turned on, and several currents must flow, and second, there must be an infinite source source.

With these prerequisites in place, holes created by gate induced drain leakage (GIDL) between the gate and drain accumulate in the substrate, resulting in a bipolar action. Once a bipolar action occurs, the transistor loses its function as a transistor. High voltage NMOS transistors are configured on the P-substrate, which further increases the possibility of hole traps.

The snapback phenomenon can be explained with reference to the equivalent circuit of FIG. 2 and FIG. 2 showing a cross section of a general bipolar junction transistor (BJT). The bipolar junction transistor has a structure in which a gate 22 is formed on a P-substrate 21, and a source junction 23 and a drain junction 24 on both sides of the gate 22 are formed, and holes 25 formed by GIDL are formed. The substrate voltage is locally raised while being trapped by the P-substrate 21. At this time, the holes 25 accumulated in the P-substrate 21 have a positive charge. When the hole trap voltage higher than the built-in potential in the PN diode is formed, the P-substrate ( 21) and a source junction 23 is a forward bias (forward bias) to the current flows. This is equivalent to the amplification condition of BJT. In other words, Vbe is in the forward direction, and Vce is in the reverse direction.

High-voltage NMOS transistors, once subjected to a bipolar action, cause rapid electrical degradation and are damaged and can no longer be used. Therefore, high voltage NMOS transistors that use voltages above 20V must avoid bipolar action in any way. The current method is to increase the distance between the metal contact and the gate to minimize the voltage caused by the holes accumulated in the substrate by using the resistance between the emitter and the base. do. This can be seen in a graph showing the HVN snapback characteristics of the high voltage NMOS transistor with respect to the change of the snapback knee voltage with respect to the space between the contact and the gate (CT to Gate Spacing) of FIG. 4. In other words, the distance between the metal contact and the gate is secured as much as possible, and the method of suppressing the maximum by dispersing the voltage using junction resistance is used. However, this method requires that the distance between the metal contact and the gate be maintained at least about 2 μm to completely suppress snapback, which is an area penalty in NAND flash chip design.

Only high-voltage NMOS transistors that are concerned about snapback due to area penalty maintain a distance of more than 2µm between metal contacts and gates, while other high-voltage NMOS transistors use approximately 0.6µm. FIG. 5 is a plan view of a high voltage NMOS transistor in which a snapback phenomenon is a concern due to an area penalty, and includes a gate 51, a source junction 52, and a drain junction 53, and a source junction 52 and a drain junction 53. The metal contacts 54 formed in each of them are 2 占 퐉 away from the gate 51. As shown in the drawing, it is difficult to construct a dense layout because a box-type active is conventionally used.

Accordingly, an object of the present invention is to provide a high voltage transistor of a flash memory device capable of improving a snapback knee voltage that may occur under operating conditions of a NAND flash memory device.

A high voltage transistor of a flash memory device according to the first aspect of the present invention for achieving this object comprises a gate; A first junction formed at one side of the gate in a vertical shape or a bent shape with an active width narrower than a width of a channel region at the bottom of the gate; A second junction formed on the other side of the gate in a vertical shape or a curved shape with an active width narrower than the width of the channel region under the gate; A first metal contact connected to the first junction and spaced apart from the gate by a predetermined distance; A second metal contact connected to the second junction and spaced apart from the gate by a predetermined distance; A first metal wire connected to the first metal contact; And a second metal wire connected to the second metal contact.

Any one of the first junction and the second junction is a source, and the other junction is a drain.

The active width of each of the first junction and the second junction is 0.1-1.0 μm.

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The first junction and the second junction are symmetrical with each other.

Bonding resistance of each of the first junction portion and the second junction portion is controlled by the first metal wiring and the second metal wiring, respectively.

Each of the first metal contact and the second metal contact is formed at least one at a different distance from the gate, and is formed in the range of 0.5 to 10.0 μm from the gate.

A high voltage transistor of a flash memory device according to a second aspect of the present invention for achieving the object of the present invention comprises a gate; A first junction formed at one side of the gate with an active width equal to a width of a channel region under the gate; A second junction formed on the other side of the gate in a vertical shape or a curved shape with an active width narrower than the width of the channel region under the gate; A first metal contact connected to the first junction and spaced apart from the gate by a predetermined distance; A second metal contact connected to the second junction and spaced apart from the gate by a predetermined distance; A first metal wire connected to the first metal contact; And a second metal wire connected to the second metal contact.

Any one of the first junction and the second junction is a source, and the other junction is a drain.

The active width of the second junction is 0.1 to 1.0 mu m.

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The first junction and the second junction are asymmetrical with each other.

The junction resistance of the first junction is fixed, and the junction resistance of the second junction is controlled by the second metal wiring.

The first metal contact is formed at a distance of 0.6 μm from the gate.

At least one second metal contact is formed at a different distance from the gate, and is formed in a range of 0.5 to 10.0 μm from the gate.

A high voltage transistor of a flash memory device according to a third aspect of the present invention for achieving the above object is a gate; A first junction formed at one side of the gate in a vertical shape or a bent shape with an active width equal to a width of a channel region under the gate; A second junction formed in a bent shape at the other side of the gate with an active width equal to the width of the channel region under the gate; A first metal contact connected to the first junction and spaced apart from the gate by a predetermined distance; A second metal contact connected to the second junction and spaced apart from the gate by a predetermined distance; A first metal wire connected to the first metal contact; And a second metal wire connected to the second metal contact.

One of the junction portions of the first junction portion and the second junction portion is a source, and the other junction portion is a drain.

The first junction and the second junction are symmetrical with each other.

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delete

The first junction and the second junction are asymmetrical with each other.

Bonding resistance of each of the first junction portion and the second junction portion is controlled by the first metal wiring and the second metal wiring, respectively.

The junction resistance of the first junction is fixed, and the junction resistance of the second junction is controlled by the second metal wiring.

Each of the first metal contact and the second metal contact is formed at least one at a different distance from the gate, and is formed in the range of 0.6 to 10.0 μm from the gate.

The first metal contact is formed to be spaced apart from the gate by 0.6 μm, and the second metal contact is formed at least one at a different distance from the gate, and is formed in the range of 0.6 to 10.0 μm from the gate.

The first metal contact and the second metal contact are arranged asymmetrically.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. Like reference numerals in the drawings refer to like elements.

According to the present invention, in order to improve snapback knee voltage that may occur under operating conditions of a NAND flash memory device, a high voltage NMOS transistor should be formed at a far distance between a metal contact and a gate, and to achieve high integration. Space must be used efficiently. In addition, the present invention allows the junction resistance to be adjusted in consideration of the characteristics of the transistor, such as a high voltage NMOS transistor or other high voltage NMOS transistors in which a snapback phenomenon is concerned. Considering these points, a high voltage transistor of a NAND flash memory device according to an exemplary embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 6 is a graph showing a change in active junction resistance with respect to an active width. As the active width decreases based on an active width of 1.5 μm, the junction resistance rapidly increases. The first to fourth embodiments (FIGS. 7, 8, 9 and 10) of the embodiments described below relate to increasing the active junction resistance by reducing the active width based on the result of FIG.

7 is a plan view of a high voltage transistor of a flash memory device according to a first embodiment of the present invention. The high voltage transistor includes a gate 71, a first junction portion 72 having an active width narrower than a width of a channel region under the gate 71 at one side of the gate 71, and a gate 71 at the other side of the gate 71. The first metal contact 74 and the second junction 73 formed at an active width narrower than the width of the channel region at the bottom thereof, the first metal contact 74 and the second formed at a predetermined distance from the gate 71. The second metal contact 75 connected to the junction 73 and spaced apart from the gate 71 by a distance, the third metal contact 76 and the first metal contact 74 connected to one end of the gate 71. The first metal wiring 77 is connected to each other, the second metal wiring 78 is connected to the second metal contact 75, and the third metal wiring 79 is connected to the third metal contact 76.

In the above, the first and second junctions 72 and 73 are perpendicular from the gate 71 and have an active width of 1.0 μm or less, preferably 0.1 to 1.0 μm. If either of the first and second junctions 72 and 73 is a source, the other is a drain.

At least one first metal contact 74 is formed at a different distance from the gate 71, but is formed at a distance spaced at least 0.5 μm from the gate 71, preferably in a range of 0.5 to 10.0 μm. Similarly, at least one second metal contact 75 is formed at a different distance from the gate 71, but is formed at a distance spaced at least 0.5 μm from the gate 71, preferably in a range of 0.5 to 10.0 μm.                     

Meanwhile, in the high voltage transistor according to the first embodiment illustrated in FIG. 7, the first junction 72 and the second junction 73 are symmetrical with each other, and the first metal wire 77 has the first metal contacts. The second metal wire 78 is connected to the last of the second metal contacts 75 so that the junction resistance of the first junction portion 72 and the junction resistance of the second junction portion 73 are the same. It is a symmetrical structure. However, when the junction resistances of the first junction portion 72 and the second junction portion 73 are differently applied according to the characteristics of the high voltage transistor, for example, the first metal contacts 77 may be connected to the first metal wiring 77. One of them may be connected, and two or more of the second metal contacts 76 may be connected to the second metal wire 78 to adjust the bonding resistance to be asymmetric. As such, the high voltage transistor according to the first embodiment has a junction resistance depending on how each of the first and second metal wires 77 and 78 is connected to each of the first and second metal contacts 74 and 75. This can be symmetrical or asymmetrical.

8 is a plan view of a high voltage transistor of a flash memory device according to a second embodiment of the present invention. The high voltage transistor has a gate 81, a first junction 82 formed at an active width equal to a width of a channel region under the gate 81 at one side of the gate 81, and a gate 81 at the other side of the gate 81. The first metal contact 84 and the second junction 83 formed at an active width narrower than the width of the channel region at the bottom thereof, the first metal contact 84 formed at a predetermined distance from the gate 81, and the second junction 83. A second metal contact 85 connected to the junction 83 and spaced a predetermined distance from the gate 81, a third metal contact 86 connected to one end of the gate 81, and a first metal contact 84. The first metal wiring 87 is connected, the second metal wiring 88 is connected to the second metal contact 85 and the third metal wiring 89 is connected to the third metal contact 86.

In the above, the second junction 83 is vertical from the gate 81 and has an active width of 1.0 μm or less, preferably 0.1 to 1.0 μm. If either of the first and second junctions 82 and 83 is a source, the other is a drain.

The first metal contact 84 is formed at a distance of about 0.6 μm from the gate 81. At least one second metal contact 85 is formed at a different distance from the gate 81, but is formed at a distance spaced at least 0.5 μm from the gate 81, preferably in a range of 0.5 to 10.0 μm.

Meanwhile, in the high voltage transistor according to the second exemplary embodiment illustrated in FIG. 8, the first junction portion 82 and the second junction portion 83 have different asymmetric structures, and the junction resistances also have different asymmetric structures. In the high voltage transistor according to the second exemplary embodiment, the junction resistance of the first junction 82 is fixed, and the second junction 83 may vary depending on how the second metal wire 88 is connected to the second metal contacts 85. ) Can adjust the junction resistance.

9 is a plan view of a high voltage transistor of a flash memory device according to a third embodiment of the present invention. The high voltage transistor has a gate 91, a first junction 92 formed with an active width narrower than the width of the channel region below the gate 91 at one side of the gate 91, and a gate 91 at the other side of the gate 91. The first metal contact 94 and the second junction 93 formed at an active width narrower than the width of the channel region below the first junction 92 and the first junction 92 formed at a predetermined distance from the gate 91. The second metal contact 95 connected to the junction 93 and spaced apart from the gate 91 by a distance, the third metal contact 96 connected to one end of the gate 91, and the first metal contact 94. The first metal wiring 97 is connected to each other, the second metal wiring 98 is connected to the second metal contact 95, and the third metal wiring 99 is connected to the third metal contact 96.

In the above description, the first and second junctions 92 and 93 have a curved shape, for example, a 'd' shape, from the gate 91 and have an active width of 1.0 μm or less, preferably 0.1 to 1.0 μm. If either of the first and second junctions 92 and 93 is a source, the other is a drain.

At least one first metal contact 94 is formed at a different distance from the gate 91, but is formed at a distance spaced at least 0.5 μm from the gate 91, preferably in a range of 0.5 to 10.0 μm. Similarly, at least one second metal contact 95 is formed at different distances from the gate 91, but is formed at a distance spaced at least 0.5 μm from the gate 91, preferably in a range of 0.5 to 10.0 μm.

Meanwhile, in the high voltage transistor according to the third exemplary embodiment illustrated in FIG. 9, the first junction 92 and the second junction 93 have a symmetrical structure, and the first metal wire 97 has first metal contacts. And the second metal wire 98 is connected to the last of the second metal contacts 95 so that the junction resistance of the first junction 92 and the junction resistance of the second junction 93 are the same. It is a symmetrical structure. However, when the junction resistances of the first junction 92 and the second junction 93 are differently applied according to the characteristics of the high voltage transistor, for example, the first metal contacts 95 may be connected to the first metal wiring 97. One of them may be connected, and two or more of the second metal contacts 96 may be connected to the second metal wire 98 to adjust the bonding resistance to be asymmetric. As such, the high voltage transistor according to the third embodiment has a junction resistance depending on how each of the first and second metal wires 97 and 98 is connected to each of the first and second metal contacts 94 and 95. This can be symmetrical or asymmetrical.

10 is a plan view of a high voltage transistor of a flash memory device according to a fourth embodiment of the present invention. The high voltage transistor includes a gate 101, a first junction 102 formed at an active width equal to the width of a channel region under the gate 101 at one side of the gate 101, and a gate 101 at the other side of the gate 101. The first metal contact 104 and the second junction 103 formed at an active width narrower than the width of the channel region at the bottom thereof, the first metal contact 104 formed at a distance from the gate 101, and the second junction 103 formed at a predetermined distance from the gate 101. A second metal contact 105 connected to the junction 103 and spaced apart from the gate 101 by a distance, a third metal contact 106 connected to one end of the gate 101, and a first metal contact 104. The first metal wire 107 connected to the second metal wire 105 is connected to the second metal contact 105 and the third metal wire 109 connected to the third metal contact 106.

In the above, the second junction 103 has a curved shape, for example, a 'd' shape from the gate 101, and has an active width of 1.0 μm or less, preferably 0.1 to 1.0 μm. If either of the first and second junctions 102 and 103 is a source, the other is a drain.

The first metal contact 104 is formed at a distance of about 0.6 μm from the gate 101. At least one second metal contact 105 is formed at a different distance from the gate 101, but is formed at a distance spaced at least 0.5 μm from the gate 101, preferably in a range of 0.5 to 10.0 μm.

Meanwhile, in the high voltage transistor according to the fourth embodiment shown in FIG. 10, the first junction 102 and the second junction 103 have different asymmetric structures, and the junction resistances also have different asymmetric structures. In the high voltage transistor according to the fourth exemplary embodiment, the junction resistance of the first junction 102 is fixed, and the second junction 103 may vary depending on how the second metal wire 108 is connected to the second metal contacts 105. ) Can adjust the junction resistance.

As described above, when the high voltage transistor is configured according to the first, second, third and fourth embodiments of the present invention, the junction resistance is the resistance of the metal contact portion represented by the resistance between the channel region and the metal contact under the gate. The relatively high overall resistance results in resistance in the narrow active width portion. This means that even if a voltage of 20V is applied to the metal contact, the voltage reaching the channel region is dropped by the junction resistance, thereby reducing the generation of holes due to GIDL, thereby decreasing the substrate voltage increase caused by the hole trap, thereby reducing the bipolar polarity. No action is taken. In other words, since the well resistance and the metal contact resistance are determined by the process, the active junction resistance is maximized to lower the voltage due to the hole trap made in the well as much as possible. do. Therefore, the high voltage transistors according to the first, second, third and fourth embodiments of the present invention increase the active junction resistance as described above, thereby increasing the snapback knee voltage. In particular, the third and fourth embodiments are advantageous in terms of high integration since the joints can be formed in a curved form, for example, in the form of a letter 'd', to increase the space efficiency.

11 is a plan view of a high voltage transistor of a flash memory device according to a fifth embodiment of the present invention. The high voltage transistor includes a gate 111 and a first junction 112 formed at the same active width as the width of the channel region under the gate 111 at one side of the gate 111 and the gate 111 at the other side of the gate 111. The first metal contact 114 and the second junction 113 and the first junction 112 formed to have an active width equal to the width of the channel region at the bottom thereof and are spaced apart from the gate 111 by a predetermined distance. The second metal contact 115 connected to the junction 113 and spaced apart from the gate 111 by a predetermined distance, the third metal contact 116 and the first metal contact 114 connected to one end of the gate 111. The first metal wire 117 is connected, the second metal wire 118 is connected to the second metal contact 115, and the third metal wire 119 is connected to the third metal contact 116.

In the above, the first and second junctions 112 and 113 are bent from the gate 111, for example, a 'd' shape. If either of the first and second junctions 112 and 113 is a source, the other is a drain.

At least one first metal contact 114 is formed at a different distance from the gate 111, but is formed at a distance spaced at least 0.6 μm from the gate 111, preferably in a range of 0.6 to 10.0 μm. Similarly, at least one second metal contact 115 is formed at different distances from the gate 111, but is formed at a distance spaced at least 0.6 μm from the gate 111, preferably in a range of 0.6 to 10.0 μm.                     

Meanwhile, in the high voltage transistor according to the fifth embodiment illustrated in FIG. 11, the first junction 112 and the second junction 113 are symmetrical with each other, and the first metal wire 117 has the first metal contacts. The last one of the 114 and the second metal wire 118 is connected to the last of the second metal contacts 115 so that the junction resistance of the first junction 112 and the junction resistance of the second junction 113 are the same. It is a symmetrical structure. However, when the junction resistances of the first junction 112 and the second junction 113 are applied differently according to the characteristics of the high voltage transistor, for example, the first metal contacts 115 may be connected to the first metal wiring 117. One of them may be connected, and two or more of the second metal contacts 116 may be connected to the second metal wire 118 so that the bonding resistance may be asymmetric. As such, the high voltage transistor according to the fifth embodiment has a junction resistance depending on how the first and second metal wires 117 and 118 are respectively connected to the first and second metal contacts 114 and 115, respectively. This can be symmetrical or asymmetrical.

12 is a plan view of a high voltage transistor of a flash memory device according to a sixth embodiment of the present invention. The high voltage transistor includes a gate 121 and a first junction 122 formed at the same active width as the width of the channel region under the gate 121 at one side of the gate 121 and the gate 121 at the other side of the gate 121. The first metal contact 124 and the second contact portion 123 formed to have an active width equal to the width of the channel region at the bottom thereof, and connected to the first junction portion 122 and spaced apart from the gate 121 by a predetermined distance. The second metal contact 125 connected to the junction 123 and spaced apart from the gate 121 by a distance, the third metal contact 126 and the first metal contact 124 connected to one end of the gate 121. The first metal wire 127 is connected, the second metal wire 128 is connected to the second metal contact 125, and the third metal wire 129 is connected to the third metal contact 126.

In the above, the second junction 123 is bent from the gate 121. If either of the first and second junctions 122 and 123 is a source, the other is a drain.

The first metal contact 124 is formed at a distance of about 0.6 μm from the gate 121. At least one second metal contact 125 is formed at a different distance from the gate 121, but is formed at a distance spaced at least 0.6 μm from the gate 121, preferably in a range of 0.6 to 10.0 μm.

Meanwhile, in the high voltage transistor according to the sixth embodiment illustrated in FIG. 12, the first junction 122 and the second junction 123 have different asymmetric structures, and the junction resistances also have different asymmetric structures. In the high voltage transistor according to the sixth exemplary embodiment, the junction resistance of the first junction 122 is fixed, and the second junction 123 may vary depending on how the second metal wire 128 is connected to the second metal contacts 125. ) Can adjust the junction resistance.

As described above, when the high voltage transistors are configured according to the fifth and sixth embodiments of the present invention, the junction portion may be bent to increase the space efficiency while increasing the space efficiency, thereby increasing the junction resistance. Therefore, even if a voltage of 20V is applied to the metal contact, the voltage reaching the channel region is dropped by the junction resistance, thereby reducing the generation of holes due to GIDL, thereby increasing the substrate voltage due to the hole trap. Decreases so that no bipolar action takes place. Therefore, the high voltage transistors according to the fifth and sixth embodiments of the present invention increase the active junction resistance as described above, thereby increasing the snapback knee voltage, and increasing the space efficiency by forming the junction in a bent form. It is advantageous to

13 is a plan view of a high voltage transistor of a flash memory device according to a seventh embodiment of the present invention. The high voltage transistor includes a gate 131 and a first junction 132 formed at the same active width as the width of the channel region under the gate 131 on one side of the gate 131 and the gate 131 on the other side of the gate 131. The first metal contact 134 and the second contact portion 133 formed to have the same active width as the width of the channel region at the bottom thereof, the first metal contact 134 and the second contact portion formed to be spaced apart from the gate 131 by a predetermined distance. The second metal contact 135 connected to the junction 133 and spaced apart from the gate 131 by a predetermined distance, the third metal contact 136 connected to one end of the gate 131, and the first metal contact 134. The first metal interconnection 137 connected to the second metal contact 135 is connected to the second metal interconnection 138 and the third metal interconnection 139 connected to the third metal contact 136.

In the above, if either one of the first and second junctions 132 and 133 is a source, the other is a drain.

Each of the first and second metal contacts 134 and 135 may be formed at a distance of 0.6 μm or more from the gate 131, and the snapback may be arranged asymmetrically with the positions of the first and second metal contacts 134 and 135. The effect of raising the knee voltage is obtained.

14 is a plan view of a high voltage transistor of a flash memory device according to an eighth embodiment of the present invention. The high voltage transistor includes a gate 141 and a first junction portion 142 having the same active width as the width of the channel region under the gate 141 on one side of the gate 141 and the gate 141 on the other side of the gate 141. The first metal contact 144 and the second contact portion 143 and the first junction 143 formed to have an active width equal to the width of the channel region below the first junction 142 and spaced apart from the gate 141 by a predetermined distance. The second metal contact 145 connected to the junction 143 and spaced apart from the gate 141 by a predetermined distance, the third metal contact 146 connected to one end of the gate 141, and the first metal contact 144. The first metal wire 147 is connected to the second metal wire 148 and the third metal wire 149 is connected to the third metal contact 146.

In the above, if one of the first and second junctions 142 and 143 is a source, the other is a drain.

The second metal contact 145 is formed at a distance of 0.6 μm or more from the gate 141, and the first metal contact 144 is farther than a distance formed by the second metal contact 145 with the gate 141. Formed at a distance, the first and second metal contacts 144 and 145 are arranged asymmetrically, thereby increasing the snapback knee voltage.

As described above, the present invention can make the active width of the junction narrower than the channel width, or form the junction to bend to increase the junction resistance to improve the snapback knee voltage, and to make the junction bent to effectively use the space. In addition, metal contacts may be formed at different positions from the gate, and the junction resistance may be freely adjusted through the metal wiring, thereby implementing various high voltage transistors. Therefore, the present invention can not only improve the reliability and characteristics of the device, but also realize high integration.

Claims (26)

gate; A first junction formed at one side of the gate in a vertical shape or a bent shape with an active width narrower than a width of a channel region at the bottom of the gate; A second junction formed on the other side of the gate in a vertical shape or a curved shape with an active width narrower than the width of the channel region under the gate; A first metal contact connected to the first junction and spaced apart from the gate by a predetermined distance; A second metal contact connected to the second junction and spaced apart from the gate by a predetermined distance; A first metal wire connected to the first metal contact; And A high voltage transistor of a flash memory device comprising a second metal wire connected to the second metal contact. The method of claim 1, The junction of any one of the first junction and the second junction is a source, and the other junction is a drain. The method according to claim 1 or 2, The active voltage of each of the first junction and the second junction is 0.1-1.0 μm, the high voltage transistor of the flash memory device. The method according to claim 1 or 2, The first junction and the second junction are symmetrical with each other, the high voltage transistor of the flash memory device. The method according to claim 1 or 2, The junction resistance of each of the first junction and the second junction is controlled by each of the first metal interconnection and the second metal interconnection. The method of claim 1, At least one of the first metal contact and the second metal contact is formed at a different distance from the gate, and is formed in a range of 0.5 to 10.0 μm from the gate. gate; A first junction formed at one side of the gate with an active width equal to a width of a channel region under the gate; A second junction formed on the other side of the gate in a vertical shape or a curved shape with an active width narrower than the width of the channel region under the gate; A first metal contact connected to the first junction and spaced apart from the gate by a predetermined distance; A second metal contact connected to the second junction and spaced apart from the gate by a predetermined distance; A first metal wire connected to the first metal contact; And A high voltage transistor of a flash memory device comprising a second metal wire connected to the second metal contact. The method of claim 7, wherein The junction of any one of the first junction and the second junction is a source, and the other junction is a drain. The method according to claim 7 or 8, The active voltage of the second junction is 0.1 to 1.0㎛ high voltage transistor of the flash memory device. The method according to claim 7 or 8, The high voltage transistor of the flash memory device having the first junction and the second junction are asymmetric with each other. The method according to claim 7 or 8, The junction resistance of the first junction is fixed, and the junction resistance of the second junction is controlled by the second metal wiring. The method of claim 1, And the first metal contact is formed at a distance of 0.6 占 퐉 from the gate. The method of claim 1, The second metal contact is formed at least one at a different distance from the gate, the high voltage transistor of the flash memory device formed in the range of 0.5 to 10.0㎛ from the gate. gate; A first junction formed at one side of the gate in a vertical shape or a bent shape with an active width equal to a width of a channel region under the gate; A second junction formed on the other side of the gate in a vertical shape or a bent shape with an active width equal to the width of the channel region under the gate; A first metal contact connected to the first junction and spaced apart from the gate by a predetermined distance; A second metal contact connected to the second junction and spaced apart from the gate by a predetermined distance; A first metal wire connected to the first metal contact; And A high voltage transistor of a flash memory device comprising a second metal wire connected to the second metal contact. The method of claim 14, The junction of any one of the first junction and the second junction is a source, and the other junction is a drain. The method according to claim 14 or 15, The first junction and the second junction are symmetrical with each other, the high voltage transistor of the flash memory device. The method according to claim 14 or 15, The high voltage transistor of the flash memory device having the first junction and the second junction are asymmetric with each other. The method according to claim 14 or 15, The junction resistance of each of the first junction and the second junction is controlled by each of the first metal interconnection and the second metal interconnection. The method according to claim 14 or 15, The junction resistance of the first junction is fixed, and the junction resistance of the second junction is controlled by the second metal wiring. The method of claim 14, At least one of the first metal contact and the second metal contact is formed at a different distance from the gate, and is formed in a range of 0.6 to 10.0 μm from the gate. The method of claim 14, The first metal contact is formed to be spaced apart from the gate by 0.6 μm, and the second metal contact is formed at least one at a different distance from the gate, and is formed in a range of 0.6 to 10.0 μm from the gate. High voltage transistor. The method of claim 14, And the first metal contact and the second metal contact are arranged asymmetrically. delete delete delete delete

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