JPH0684941A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve an electrostatic damage resistance of a MIS type FET in which silicide is provided in impurity diffused layers of source.drain. CONSTITUTION:Impurity diffused layers 4 of source.drain of a MIS type FET having a silicide of high melting point metal are formed at parts, a necked region 7 reduced as compared with a width of a gate in a lateral size of a plane direction is provided at least part between a contact 6 and a gate 3, a layer resistance of the layer 4 is increased by the region 7, and noise to be invaded from the contact 6 is attenuated to prevent damage of the FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved resistance to electrostatic breakdown of a MIS type FET.

[0002]

2. Description of the Related Art Recent MIS-type FETs have been proposed in which the parasitic resistance of the source / drain is reduced. For example, as shown in FIG. 3, after a gate insulating film 2 and a gate 3 are formed on a semiconductor substrate 1 and an impurity diffusion layer 4 for a source / drain is formed, a high level is formed on the impurity diffusion layer 4 for a source / drain. A metal silicide having a melting point, for example, titanium silicide 5 is selectively formed. By forming the titanium silicide 5, the layer resistance of the impurity diffusion layer 4 of the source / drain is 100% when the silicide is not used.
It can be reduced by about 1 to 2 digits from about Ω / □ to several Ω / □ with silicide, and the parasitic resistance at the source and drain can be greatly reduced.

However, the parasitic resistance referred to here means a resistance on the plane rather than a diffusion resistance from the gate to the connection region (contact region) with the wiring. That is, as shown in FIG. 5, if the source / drain contacts 6 of the MIS-type FET are provided at one point and the wiring is routed through a vacant region after that, the integration degree of the entire semiconductor device is improved. When the channel width of the FET becomes large, the parasitic resistance of the source / drain becomes large only by providing the contact at one point. Therefore, in order to reduce the parasitic resistance, the refractory metal silicide is used.

[0004]

The MIS type FET provided with such a silicide has a problem that its electrostatic breakdown resistance is low. FIG. 4 shows a P-channel MOS type transistor PMOS and an N-channel MOS type transistor NM.
An example of a drive circuit of an output stage of a CMOS circuit configured with an OS is shown, but a signal from an internal circuit is connected to a gate G, and a drain D of each transistor PMOS and NMOS is provided.
Is connected to an external circuit. When pulsed high-voltage noise enters the drain D from the outside, the MIS type F without silicide in the impurity diffusion layer 4 of the source / drain.
In ET, noise is attenuated by the layer resistance of the impurity diffusion layer 4 and the junction capacitance between the impurity diffusion layer 4 and the substrate 1, and when the noise reaches the channel region, the pulse amplitude is also attenuated. However, when the silicide 5 is present as shown in FIG. 3, the resistance of the silicide 5 is low, so that the pulse is not attenuated so much, a high voltage is applied to the channel, and the MISFET is destroyed. An object of the present invention is to provide a semiconductor device capable of improving the electrostatic breakdown resistance of a MIS type FET.

[0005]

According to the present invention, an impurity diffusion layer of a source / drain of a MIS type FET having a part of a refractory metal silicide is formed in a plane direction at least a part between a contact and a gate. A constricted region having a width dimension smaller than the gate width is provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an embodiment of the MIS type FET of the present invention. A gate 3 is formed on a semiconductor substrate 1, and a source / drain impurity diffusion layer 4 is formed so as to sandwich the gate 3.
Is formed. A contact 6 having a silicide structure is formed in the impurity diffusion layer 4. This contact 6
The cross-sectional structure of the region including is the same as that shown in FIG. Further, the impurity diffusion layer 4 is provided between the contact 6 and the gate 3 with a constricted region 7 having a width dimension in the plane direction smaller than the gate width.

According to this structure, the contact 6 provided in the impurity diffusion layer 4 of the source / drain has a silicide structure to reduce the parasitic resistance of the source / drain, while the constricted region 7 is provided to reduce impurities. The layer resistance of the diffusion layer 4 is increased. As a result, even if pulsed noise enters through the contact 6, the noise is attenuated by the increased layer resistance, a high voltage is prevented from being applied to the channel, and the MISFET is prevented from being destroyed.

FIG. 2 is a plan view of the second embodiment of the present invention. Here, of the impurity diffusion layer 4 of the source / drain,
By forming a plurality of windows 8 between the contact 6 and the gate 3, a plurality of constricted regions 7 are formed therebetween. Even with this structure, it is possible to increase the layer resistance between the contact and the channel, attenuate the noise intruding from the contact, and prevent the MIS-type FET from being destroyed. In particular, in this configuration, since the high voltage is distributed to the plurality of constricted regions, the high voltage is not concentrated in one constricted region as in the first embodiment. According to the experiment by the present inventor, the MIS-type FET in which silicide is provided on the source / drain has an electrostatic breakdown resistance of 1 in terms of a defective rate as compared with the conventional one.
I was able to improve it by 00 times.

[0009]

As described above, according to the present invention, since a constricted region having a reduced dimension in the width direction is provided in a part of the impurity diffusion layer of the source / drain provided with the silicide, the impurity of the source / drain is not formed. To increase the layer resistance of the diffusion layer to attenuate noise, and to significantly improve the electrostatic breakdown resistance of the MIS-type FET in which silicide is provided in the source / drain, and to greatly improve the reliability of the semiconductor device. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a plan view of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional MIS type FET having a silicide structure.

FIG. 4 is a circuit diagram for explaining a problem in a MIS type FET.

FIG. 5 is a plan view of the MIS type FET as shown in FIG.

[Explanation of symbols]

 1 semiconductor substrate 3 gate 4 source / drain impurity diffusion layer 5 silicide 6 contact 7 constricted region

Claims (1)

[Claims] 1. A semiconductor device comprising a MISFET having a refractory metal silicide in a part of a source / drain impurity diffusion layer, wherein the source / drain impurity diffusion layer is at least between a contact and a gate. A semiconductor device, wherein a constricted region having a width dimension in a plane direction smaller than a gate width is provided in a part thereof.