JPH0817936A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a protective device of high noise resistance in a semiconduc tor device composed of CMOS having a source.drain region of salicide structure of LDD structure. CONSTITUTION:In an Nch MOS transistor TN2 constituting the final stage CMOS inverter of an output buffer, a multilayered insulating film spacer is formed on the side surface on the drain region side of a gate electrode 15. The spacer is composed of a silicon nitride film spacer 7 and silicon oxide film spacers 8b, 8ca, 8cb.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a transistor which constitutes a semiconductor device protection device which is an LDD structure and which has a salicide structure source / drain region.

[0002]

2. Description of the Related Art Miniaturization of semiconductor devices has been achieved by reducing the gate length of gate electrodes. With this,
First, in order to suppress the short channel effect, an insulating film spacer is provided on the side surface of the gate electrode, and a low-concentration diffusion layer provided in self alignment with the gate electrode and this insulating film spacer are provided in self alignment. LDD-structured source / drain regions having a high-concentration diffusion layer have appeared. Further, in order to reduce the parasitic resistance (layer resistance) of the source / drain regions that hinders the speedup of the semiconductor device, a refractory metal silicide film is provided in a self-aligned manner on the surface of the high concentration diffusion layer of the source / drain regions. Source / drain regions with a salicide structure have been adopted. Furthermore, these semiconductor devices are required to have high speed and low power consumption, and among semiconductor devices composed of MOS transistors, semiconductor devices composed of CMOS transistors have become mainstream.

In a semiconductor device composed of CMOS transistors, a protection device for preventing positive or negative noise charge from entering terminals such as an input terminal, an output terminal, or an input / output terminal into an internal circuit has an output terminal. The first protection device limited to, and the second that can be used for any terminal
There is a protective device.

In the first protection device, the CMOS inverter forming the final stage of the output buffer is used as the protection device. The positive noise charge that has entered from the output terminal is
It flows to the ground line (applied to 0 volt) through the N-channel MOS transistor of the OS inverter. The negative noise charge that has entered from the output terminal flows through the P-channel MOS transistor of this CMOS inverter to the power supply line (applied to V _DD volt). This C
Gate electrode of MOS inverter (N-channel MOS described above)
The voltage V _G applied to the transistor and the gate electrode of the P-channel MOS transistor is 0 <V _G <V
_{It's DD} .

The second protection device is provided between the input buffer and the input terminal, between the output buffer and the output terminal, or between the input buffer and the output buffer and the input / output terminal. Is connected to the ground line and the drain region is connected to any one of the above terminals, and the P channel is connected to the gate electrode and the source region to the power supply line and the drain region is connected to any of the above terminals. It is composed of a MOS transistor. The positive noise charge that has entered from the terminal flows to the ground line through this N-channel MOS transistor. Negative noise charges that have entered from the terminal flow into the power supply line via this P-channel MOS transistor.

[0006]

In the above-described semiconductor device composed of the CMOS transistor having the source / drain regions of the salicide structure in the LDD structure, the first or second protection device (protection circuit) is provided in the semiconductor device. N-channel MO transistor having the same structure as the N-channel MOS transistor and P-channel MOS transistor forming the internal circuit
If it is composed of S-transistors and P-channel MOS transistors, it becomes a protective device with weak noise resistance and easily destroyed.

In the above-mentioned first or second protection device, for example, when positive noise charge invades, the current flowing through the ground line via the N-channel MOS transistors constituting these protection devices causes these N-channel MOS transistors to flow. BV _DS (in the first protection device, the voltage V _G applied to the gate electrode is further related), after snapback, a value inversely proportional to the parasitic resistance of the source / drain regions of these N-channel MOS transistors. Becomes
Even when a negative noise charge invades, the same appearance (the signs are reversed) as if it flowed to the ground line through the P-channel MOS transistor and the N-channel MOS transistor which constitute these protection devices. As a result, a current flows through the power line. BV of each transistor
_DS is determined by device parameters mainly including the gate length of each transistor.

As described above, the parasitic resistance of the source / drain regions of the N-channel MOS transistor and the P-channel MOS transistor forming the semiconductor device protection device has a low value because of the salicide structure. In addition, the breakdown of the transistors including the N-channel MOS transistor and the P-channel MOS transistor of the protection device is defined (current limit) by the value of the (drain) current. From these facts, the first or second protection device in the semiconductor device is a protection device with weak noise resistance and easily destroyed.

Therefore, an object of the present invention is to provide a CMO having an LDD structure and a source / drain region having a salicide structure.
It is an object of the present invention to provide a protection device having high noise resistance, which is suitable for use in the above semiconductor device including an S transistor.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
The insulating film spacer provided on at least the side surface of the gate electrode on the drain region side is composed of a laminated insulating film spacer including a first insulating film spacer and a second insulating film spacer.
A first N-channel MOS transistor having a source / drain region of a salicide structure in a structure and an insulating film spacer provided on at least a side surface on the drain region side are formed of this laminated insulating film spacer, and a source / drain of a salicide structure in an LDD structure is formed. First P channel M having a region
It has a protection device composed of an OS transistor,
Furthermore, the insulating film spacer provided on the side surface of the gate electrode is formed of the second insulating film spacer described above, and the second N having the source / drain region of the salicide structure is formed in the LDD structure.
The channel MOS transistor and the insulating film spacer provided on the side surface of the gate electrode are formed of the second insulating film spacer, and include the second P-channel MOS transistor having the source / drain region of the salicide structure in the LDD structure. Has an internal circuit.

When the CMOS inverter at the final stage of the output buffer is composed of the first N-channel MOS transistor and the first P-channel MOS transistor, it is preferable that the first N-channel MOS transistor and the first N-channel MOS transistor be used. The insulating film spacers on the side surfaces of the gate electrode on the source region side of the first P-channel MOS transistor are respectively formed of the second insulating film spacers, and the gate length of the first N-channel MOS transistor is the second N-channel MOS transistor. The gate length of the first P-channel MOS transistor is longer than that of the channel MOS transistor, and the gate length of the first P-channel MOS transistor is longer than that of the second P-channel MOS transistor.

The gate electrode and the source region of the first N-channel MOS transistor are connected to the ground line, and the gate electrode and the source region of the first P-channel MOS transistor are connected to the power supply line. The drain region of the N-channel MOS transistor and the drain region of the first P-channel MOS transistor are input terminals,
When connected to the output terminal or the input / output terminal, it is preferable that the insulating film spacers on the side surfaces of the gate electrode on the source region side of the first N-channel MOS transistor and the first P-channel MOS transistor are the above-mentioned, respectively. It consists of a laminated insulating film spacer
The gate length of the channel MOS transistor is the second N
The gate length of the first P-channel MOS transistor is equal to the gate length of the channel MOS transistor, and the gate length of the second P-channel MOS transistor is equal to that of the second P-channel MOS transistor.

[0013]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a schematic circuit diagram and a schematic sectional view of a semiconductor device, a first embodiment of the present invention is as follows.
A transistor based on the 0.5 μm design rule is adopted,
It has the following configuration.

First, the gist of the circuit configuration of this embodiment will be described. A CMOS inverter, which is the final stage of the output buffer, also serves as a protection device that protects the internal circuit from noise charges that enter from the output terminal. This CMOS inverter is an N-channel MOS transistor T _N2
And T _P2 which is a P-channel MOS transistor. The source regions of T _N2 and T _P2 are connected to the ground line and the power line, respectively, the drain regions of T _N2 and T _P2 are connected to the output terminal, and the gate electrodes of T _N2 and T _P2 are, for example, V _G volt. The power supply line and the ground line are applied to V _DD volt (power supply voltage) and 0 volt, respectively. Note that V _G is 0 <V
_G <V _DD . The internal circuit is, for example, an N-channel MOS
It is composed of a transistor T _N1 and a P-channel MOS transistor T _P1 and includes a CMOS inverter and the like. The source region of the T _N1 and T _P1 are connected to the applied metal wires respectively, for example to the voltage V _L volts and V _H volts. Where 0 ≦ V _L <V _H ≦ V
There is a relationship of _DD [Fig. 1 (a)].

Next, the structure of the transistor of this embodiment will be described (mainly the structure of the N-channel MOS transistor).
explain. P is formed in a predetermined area on the surface of the N-type silicon substrate 1.
A well 2 (and an N well (not shown)) is provided, and a field oxide film 3 is provided in an element isolation region on the surface of the N-type silicon substrate 1 including the surface of the P well 2.
A gate oxide film 4 having a film thickness of about 10 nm is provided in the element formation region on the surface of the N-type silicon substrate 1 including the surface of the P well 2 (and the N well).

N channel M provided on the surface of P well 2
The gate oxide film 4 of the OS transistor T _N2 is
, A gate electrode 15 having a gate length L _N2 = 0.8 μm (and a gate width of about 800 μm), and an N ⁻ type diffusion layer 16 a
a, N ⁺ type diffusion layer 9 a and N type source region composed of titanium silicide film 10 and N ⁻ type diffusion layers 16 ba, N
It is composed of a ⁺ type diffusion layer 9b and an N type drain region made of a titanium silicide film 10. The gate electrode 15 is, for example, a gate electrode having a polycide structure in which tungsten silicide and a polycrystalline silicon film are laminated. On the side surface of the gate electrode 15 on the source region side of T _N2 , the width that directly covers the surface of the gate oxide film 4 is 0.2 μm.
A silicon oxide film spacer 8a of about m is provided. In addition, the side surface of T _{N2 on} the drain region side of the gate electrode 15 has a width of 0.6 covering the surface of the gate oxide film 4 directly.
A laminated insulating film spacer having a thickness of about μm is provided. This laminated insulating film spacer includes a silicon nitride film spacer 7 and
It is composed of silicon oxide film spacers 8b, 8ca, 8cb. The width of the N ⁻ type diffusion layer 16ba and the N
The difference between the width of the ⁻ type diffusion layer 16aa and the width of the laminated insulating film spacer 8a is equal to the difference between the width of the silicon oxide film spacer 8a. P channel MOS provided on N well surface
The transistor T _P2 includes a gate oxide film 4, a gate electrode (not shown) having a gate length L _P2 (≈L _N2 ), a P ⁻ type diffusion layer (not shown), and a P ⁺ type diffusion layer (see FIG. (Not shown) and source / drain regions made of the titanium silicide film 10. A silicon oxide film spacer 8a and the above-mentioned laminated insulating film spacer are provided on the side surface of the gate electrode of T _P2 on the source region side and the side surface on the drain region side, respectively.

N channel M provided on the surface of P well 2
The OS transistor T _N1 includes a gate oxide film 4, a gate electrode 5 having a gate length L _N1 = 0.5 μm (= minimum processing size), an N ⁻ type diffusion layer 6 a, an N ⁺ type diffusion layer 9 a, and titanium silicide. An N-type source region formed of the film 10, and N
^{It is} composed of a ⁻ type diffusion layer 6a, an N ⁺ type diffusion layer 9b, and an N type drain region made of a titanium silicide film 10. A silicon oxide film spacer 8a is provided on each of the side surface of the gate electrode 5 of T _{N1 on} the source region side and the side surface of the drain region side. The P channel MOS transistor T _P1 provided on the N well surface is
Gate oxide film 4, gate electrode (not shown) having a gate length L _P1 (≈L _N1 ), P ⁻ type diffusion layer (not shown), P ⁺ type diffusion layer (not shown) and titanium silicide film And a source / drain region of 10. The silicon oxide film spacers 8 are also formed on the side surface of the gate electrode of T _P1 on the source region side and the side surface on the drain region side, respectively.
a is provided [FIG. 1 (b)]. The transistors forming the internal circuit are not limited to T _N1 and T _P1 only, but N-channel MOS transistors having a gate electrode having a gate length longer than L _N1 and gate electrodes having a gate length longer than L _P1 are used. It may include a P-channel MOS transistor that it has.

The T _N1 , T _N2 , T _P1 and T _P2 etc. are covered with an interlayer insulating film 11. The interlayer insulating film 11 is provided with contact holes reaching the source region and drain region of each transistor, and metal wirings 12a and 12b connected to the source region and drain region through these contact holes. , 22
a, 22b, etc. are provided. By metal line 12a, the source region of T _N1 is connected to the metal line applied to V _L volts. The drain region of T _{N1 and} the drain region of T _P1 are connected by a metal wiring 12b.
The gate electrode 5 of T _{N1 and} the gate electrode of T _P1 are connected directly or via another metal wiring. The source region of T _N2 is connected to the ground line by the metal wiring 22a. The drain region of T _N2, the drain region of T _P2 , and the output terminal are connected by a metal wiring 22b. T _N2
Gate electrode 5 and the gate electrode of T _P2 are connected directly or via another metal wiring [FIG. 1 (a),
(B)].

Referring to FIG. 2, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, the N-channel M of the first embodiment is described.
The OS transistors T _N1 , T _N2, etc. are formed as follows.

First, a P well 2 is formed in a predetermined region on the surface of the N-type silicon substrate 1. A field oxide film 3 is formed in the element isolation region on the surface of the N-type silicon substrate 1 including the surface of the P well 2 and a gate oxide film 4 is formed in the element formation region on the surface of the N-type silicon substrate 1. For example, an N-type polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire surface, and these films are patterned to form the gate electrodes 5, 15 and the like. Gate electrode 5,
N ⁻ type diffusion layers 6, 16a, 16b are formed on the surface of the P well 2 by ion implantation of arsenic, for example, using 15 and the field oxide film 3 as a mask [FIG. 2 (a)].

Next, a silicon nitride film is formed on the entire surface,
This silicon nitride film is patterned to form a silicon nitride film spacer 7. The thickness of this silicon nitride film must be such that it functions as a mask for ion implantation during the formation of the N ⁺ type diffusion layer in a later step. The silicon nitride film spacer 7 covers the side surface of the gate electrode 15 on the side where the drain region is formed, and is provided on the side surface of the gate electrode 5 and the side surface of the gate electrode 15 on the side where the source region is formed. Absent. The silicon nitride film spacer 7 can be formed because the gate length of the gate electrode 15 is longer than the minimum processing dimension (0.5 μm).

Subsequently, a silicon oxide film is formed on the entire surface, and this silicon oxide film (and the gate oxide film 4) is etched back by anisotropic etching to form silicon oxide film spacers 8a, 8b, 8ca, 8cb. To be done. As a result, a laminated insulating film spacer including the silicon nitride film spacer 7, the silicon oxide film spacer 8b and the silicon oxide film spacer 8cb is formed on the side surface of the gate electrode 15 on the side where the drain region is formed. The silicon oxide film spacer 8a is formed on the side surface of the gate electrode 5 and the side surface of the gate electrode 15 on the side where the source region is formed. The silicon oxide film spacer 8b is
It is formed on the step portion of the silicon nitride film spacer 7. The (bottom) width of the silicon oxide film spacer 8a is equal to the (bottom) width of the silicon oxide film spacer 8b. The silicon oxide film spacers 8ca and 8cb are formed on the side surfaces of the silicon nitride film spacer 7, and the silicon oxide film spacers 8ca and 8ca
The bottom surface of 8cb is in direct contact with the top surface of the gate electrode 15 and the surface of the gate oxide film 4, respectively.

Next, by using, for example, arsenic ion implantation with the field oxide film 3, the gate electrodes 5 and 15, the silicon oxide film spacer 8a, and the above-mentioned laminated insulating film spacer as a mask, N ⁺ type is formed on the surface of the P well 2. Diffusion layers 9a and 9b are formed. At the same time, the N ⁻ type diffusion layers 6a and 16a
b and 16ba remain (FIG. 2 (b)). Although not shown, a P ⁺ type diffusion layer for well contact is also formed on the surface of the P well 2.

Next, a titanium film is formed on the entire surface. Further, heat treatment is performed to form titanium silicide film 10 on the surfaces of N ⁺ type diffusion layers 9a and 9b in a self-aligned manner. The unreacted titanium film is selectively removed by etching. Thus, N ^- and the source region of the T _N1 consisting -type diffusion layer 6a, N ⁺ -type diffusion layer 9a and the titanium silicide film 10, N ^-
The drain region of T _{N1 formed} of the type diffusion layer 6a, the N ⁺ type diffusion layer 9b and the titanium silicide film 10 and the source region of T _{N2 formed} of the N ⁻ type diffusion layer 16aa, the N ⁺ type diffusion layer 9a and the titanium silicide film 10. And the N ⁻ type diffusion layer 16b
The formation of the drain region of T _N2 composed of the a, N ⁺ type diffusion layer 9b and the titanium silicide film 10 is completed [FIG.
(C)]. After that, the interlayer insulating film 11 is formed, the contact holes are opened, and the metal wirings 12a, 12b, 22a,
22b and the like are formed to complete the semiconductor device having the structure shown in FIG.

T _N2 which is an N-channel MOS transistor
Referring to FIG. 3 and FIG. 1, which are graphs showing the IV characteristics of the above, the operation principle of T _{N2 and} the operation and effect of this embodiment are as follows.

When positive noise charge enters the output terminal, if the charge amount is a sufficiently large value, BV _DSN2 and _{TV of} T _N2 (depending on device parameters such as gate length etc.) Voltage V _G applied to the gate electrode of _N2
After the drain voltage rises to the value specified by and
The snapback causes the drain current to increase despite the decrease in drain voltage. The drain current flowing through T _N2 in this range (snapback region) becomes a curve formed by a solid line between the two curves shown by the dotted lines in FIG.

After passing through this range, this T _N2 can be regarded simply as a resistance element, and a drain current proportional to the increase in drain voltage can be obtained. The drain current at this time is inversely proportional to the sum of the parasitic resistances of the drain region and the source region. If the parasitic resistances of the drain and source regions of T _N2 are R _DN12 and R _DN11 , then R _DN12 and R _DN12
The value of _DN11 is generally N ^- type diffusion layer 16ba width (≒ a 0.6 micron
m) and the width of the N ⁻ type diffusion layer 16aa (≈0.2 μm)
Depends on. The parasitic resistance of this source / drain region in this embodiment is R _DN11 + R _{DN12 ≈4} × R _DN11 .
Therefore, the drain current flowing through T _N2 in this range (linear region) is a straight line formed by the solid line shown in FIG. 3 in this embodiment.

On the other hand, when the insulating film spacer provided on the side surface of the gate electrode 15 of T _N2 on the drain region side is composed of the silicon oxide film spacer 8a as in the conventional case, the parasitic resistance of the source / drain region is 2 × R _DN11 , which is about half that of the present embodiment. As a result, the drain current in the straight line region becomes a straight line formed by the alternate long and short dash line shown in FIG. 3, and a current about twice that of the present embodiment flows. From these things, according to the present embodiment, the voltage value reaching the current limit is doubled as compared with the conventional structure, and the noise resistance is enhanced. Further, in the present embodiment, when negative noise charge enters from the output terminal, T _P2 having the above-mentioned laminated insulating film spacer on the side surface of the gate electrode on the drain side has the same function, and therefore the same effect can be obtained. .

In this embodiment, since the parasitic resistance of the drain region is increased, the performance as the output inverter is slightly lowered. Contrary to the present embodiment, a method of increasing the parasitic resistance of the source region or a method of simultaneously increasing the parasitic resistance of the source region and the drain region is also effective in improving the noise resistance, but in this case, for example, the source region of T _N2 Then, the potential rises from 0 V and the back gate voltage is applied to this transistor, and the apparent threshold voltage of T _N2 increases. As a result, the characteristics of the output inverter are significantly reduced. Furthermore, there is a method of not providing a titanium silicide film in the source region and the drain region, but it is not preferable to configure the output invert with such a structure.

Referring to FIG. 4 which is a schematic circuit diagram and a schematic sectional view of the semiconductor device, the second embodiment of the present invention also includes
A transistor based on the 0.5 μm design rule is adopted,
It has the following configuration.

First, the gist of the circuit configuration of this embodiment will be described. The present embodiment relates to a semiconductor device having a protection circuit for protecting an input buffer, an output buffer, and an internal circuit from noise charge that enters from an input / output terminal. The transistors forming the internal circuit include T _N1 and T _P1 as in the first embodiment. The CMOS inverter forming the final stage of the output buffer is different from that of the first embodiment in that T _N 12 , T _P 12 It consists of The gate lengths of T _N12 and T _P12 are L _N1 and L _P1 respectively.
Is. The protection device is composed of an N-channel MOS transistor T _N3 having a gate length L _N1 and a P-channel MOS transistor T _P3 having a gate length L _P1 . T
The drain region of _{N3 and} the drain region of T _P3 are respectively connected to the input / output terminals. The gate electrode and source region of T _N3 are connected to the ground line. The gate electrode and the source region of T _P3 are connected to the power supply line [FIG. 4 (a)]. The absolute value of the threshold voltage of T _{P3 and} the threshold voltage of T _N3 are preferably set low in the range in which punch-through hardly occurs.

Next, the structure of the transistor of this embodiment (mainly the structure of the N-channel MOS transistor) will be described.
explain. P is formed in a predetermined area on the surface of the N-type silicon substrate 1.
Well 2 (and N well) is provided, and field oxide film 3 is provided in the element isolation region on the surface of N type silicon substrate 1 including the surface of P well 2 and P well 2 (and N well).
A gate oxide film 4 is provided in the element formation region on the surface of the N-type silicon substrate 1 including the well surface.

N channel M provided on the surface of P well 2
The gate oxide film 4 of the OS transistor T _N3 is
, A gate electrode 25 having a gate length L _N1 , and an N ⁻ type diffusion layer 2
6a, N ⁺ type diffusion layer 9a and titanium silicide film 10
Source region of N type and N ⁻ type diffusion layers 26a, N
It is composed of a ⁺ type diffusion layer 9b and an N type drain region made of a titanium silicide film 10. This gate electrode 25 is also a gate electrode having a polycide structure in which tungsten silicide and a polycrystalline silicon film are laminated.
On the side surface of the gate electrode 25 of T _{N3 on} the source region side,
A laminated insulating film spacer having a width of about 0.4 μm that directly covers the surface of the gate oxide film 4 is provided. The laminated insulating film spacer is composed of a silicon nitride film spacer 17 and silicon oxide film spacers 8ba and 8c.
Further, the side surface of the gate electrode 25 of T _{N3 on} the drain region side has a width of 0.4 μm that directly covers the surface of the gate oxide film 4.
A laminated insulating film spacer is provided to some extent. This laminated insulating film spacer is composed of a silicon nitride film spacer 17 and silicon oxide film spacers 8bb and 8c. The P channel MOS transistor T _P3 provided on the surface of the N well has a gate oxide film 4 and a gate length L _P1.
Gate electrode (not shown), a P ⁻ type diffusion layer (not shown), a P ⁺ type diffusion layer (not shown), and a source / drain region made of the titanium silicide film 10. The laminated insulating film spacers are also provided on the side surface of the gate electrode of T _P3 on the source region side and the side surface on the drain region side. Also, T _N12 and T
The structure of _P12 is the same as that of T _N1 and T _P1 , respectively (FIG. 4 (b)).

T _N1 , T _N3 , T _N12 , T _P1 , T _P3 and T
_{The P12 and the} like are covered with the interlayer insulating film 11. The interlayer insulating film 11 is provided with contact holes reaching the source region and drain region of each transistor, and metal wirings 12a connected to the source region and drain region through these contact holes,
12b, 32a, 32b and the like are provided. The metal wiring 32a allows the source region of T _N3 (and the gate electrode 2
5) is connected to the ground line. The drain region of T _N3, the drain region of T _P3 , and the input / output terminal are connected to the metal wiring 32b.
Are connected by [Fig. 4 (a), (b)].

Referring to FIG. 5 which is a schematic sectional view of the manufacturing process of the semiconductor device, T _{N3 and the} like of the second embodiment are formed as follows.

First, a P well 2 (and an N well) is formed in a predetermined region on the surface of the N type silicon substrate 1.
A field oxide film 3 is formed in the element isolation region on the surface of the N-type silicon substrate 1 including the surface of the P well 2 and a gate oxide film 4 is formed in the element formation region on the surface of the N-type silicon substrate 1. In the region where T _N3 is formed on the surface of the P well 2 (and in the region where T _P3 is formed on the N well surface), a low concentration of boron (and a low concentration of phosphorus, for example) is used for controlling the threshold voltage. Ion implantation is performed. For example, an N-type polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire surface, and these films are patterned to form gate electrodes 5, 25 and the like. Gate electrodes 5, 2
5 and the field oxide film 3 and a photoresist film (not shown) are used as masks for arsenic ion implantation, etc.
In the region where the N channel MOS transistor is formed on the surface of the well 2 (and the region where the well contact is formed on the N well surface), an N ⁻ type diffusion layer such as the N ⁻ type diffusion layer 26 is formed. Further, by ion implantation of boron difluoride (BF ₂ ) or the like using another photoresist film (not shown) as a mask, a region where well contacts on the P well 2 surface are formed (and P on the N well surface). Channel MO
A P ⁻ type diffusion layer such as the P ⁻ type diffusion layer 36 is formed in the region where the S transistor is formed (FIG. 5A).

Next, a silicon nitride film is formed on the entire surface,
This silicon nitride film is patterned to form silicon nitride film spacers 17. The thickness of this silicon nitride film is also the same as that of the N ⁺ type diffusion layer or P ⁺ in the subsequent process.
The thickness is required to function as a mask for ion implantation when forming the mold diffusion layer. The silicon nitride film spacer 17 covers the side surface (and the upper surface) of the gate electrode 25 and is not provided on the side surface of the gate electrode 5. The silicon nitride film spacer 17 is preferably formed only on the side surface of the gate electrode 25 on the side where the drain region is formed, as described in the first embodiment. If this is possible, the above-mentioned ion implantation for controlling the threshold voltage of T _N3 and T _P3 becomes unnecessary. However, (because the gate electrode 25 is formed with the minimum processing size), it is difficult to accurately form a fine pattern on the convex pattern having the width of the minimum processing size.

Then, a silicon oxide film is formed on the entire surface, and the silicon oxide film (and the gate oxide film 4) is etched back by anisotropic etching to form silicon oxide film spacers 8a, 8ba, 8bb, 8c. To be done. As a result, the silicon nitride film spacer 7, the silicon oxide film spacer 8ba, and the silicon oxide film spacer 8 are formed on the side surface of the gate electrode 25 on the side where the source region is formed.
A laminated insulating film spacer made of c is formed, and a laminated insulating film spacer made of the silicon nitride film spacer 7, the silicon oxide film spacer 8bb and the silicon oxide film spacer 8c is formed on the side surface of the gate electrode 25 on the side where the drain region is formed. Will be formed. The silicon oxide film spacers 8ba and bb are formed on the step portion of the silicon nitride film spacer 17. The width of the bottom surface of the silicon oxide film spacers 8ba and bb is equal to the width (of the bottom surface) of the silicon oxide film spacer 8a. The silicon oxide film spacer 8c is formed on the side surface of the silicon nitride film spacer 17, and the bottom surface of the silicon oxide film spacer 8c is in direct contact with the surface of the gate oxide film 4.

Next, by, for example, ion implantation of arsenic using the gate electrodes 5 and 25, the silicon oxide film spacer 8a, the above-mentioned laminated insulating film spacer and the field oxide film 3 and the photoresist film (not shown) as a mask. P well 2
N ⁺ type diffusion layers such as N ⁺ type diffusion layers 9a and 9b are formed in the region where the N channel MOS transistor is formed on the surface (and the region where the well contact is formed on the N well surface). Further, by ion implantation of boron difluoride (BF ₂ ) or the like using another photoresist film (not shown) as a mask, a region (and a surface of the N well surface) where a well contact is formed on the surface of the P well 2 is formed. A P ⁺ type diffusion layer such as the P ⁺ type diffusion layer 39 is formed in a region where the P channel MOS transistor is formed). At the same time, the N ⁻ type diffusion layers 6a, 26a and the like are left [FIG.
(B)].

Next, a titanium film is formed on the entire surface. Further, heat treatment is performed to form titanium silicide film 10 on the surfaces of N ⁺ type diffusion layers 9a and 9b and the surface of P ⁺ type diffusion layer 39 in a self-aligned manner. The unreacted titanium film is selectively removed by etching. As a result, the N ⁻ type diffusion layer 26
a, N ⁺ -type diffusion layer 9a and the source region and N of T _N3 consisting of titanium silicide film 10 ^- -type diffusion layer 26a, made of N ⁺ -type diffusion layer 9b and the titanium silicide film 10 T _N3
The formation of the drain region and the like is completed [FIG. 5 (c)]. After that, the interlayer insulating film 11 is formed, the contact holes are opened, and the metal wirings 12a, 12b, 32a, 32b, etc. are formed, and the semiconductor device having the structure shown in FIG. 4B is completed.

T _N3 which is an N-channel MOS transistor
6 and FIG. 4 which are graphs showing the IV characteristics of the above, the operation principle of T _{N3 and} the operation and effect of this embodiment are as follows.

When positive noise charge enters the output terminal, if the charge amount is a sufficiently large value, the value of BV _DSN3 of T _N3 (depending on device parameters such as gate length etc.) The drain voltage rises up to this, and the drain current starts to flow into this T _N3 and the back gate works to raise the drain voltage up to the value of BV _DSN1 of T _N1. The current rises.

When passing through this range (snapback area), this T _N3 can be regarded as a resistance element,
A drain current proportional to the increase in drain voltage can flow. This drain current is the sum of parasitic resistances (both R _DN22 ) of the drain region and the source region of T _N3 , which is 2 × R.
_Inversely proportional to _DN22 . The drain current flowing through T _N3 in this range (linear region) is a straight line shown by the solid line in FIG. On the other hand, when the insulating film spacer provided on the side surface of the gate electrode 25 of T _N3 on the side of the source region and the drain region is composed of the silicon oxide film spacer 8a as in the conventional case, the parasitic resistance of the source / drain region is 2 × R _DN21
( _≈1 × R _DN22 ), which is about 1/2 of this embodiment,
The drain current in the straight line region is a straight line formed by the alternate long and short dash line shown in FIG. 6, and a current about twice as large as that in this embodiment flows. From these facts, also in the present embodiment, as in the first embodiment, the voltage value reaching the current limit is doubled and the noise immunity is increased, as compared with the conventional structure. Also in this embodiment, when negative noise charge enters from the output terminal, T _P3 having the above-mentioned laminated insulating film spacer on the side surface of the gate electrode on the drain side has the same function, and therefore the same effect can be obtained.

In the present embodiment, as described above, the gate lengths of the gate electrodes of T _N3 and T _P3 are L _N1 and L _N , respectively.
_P1 is set, and ion implantation is performed to control the threshold voltage of these transistors. The reason for this is that it is not preferable to make the absolute value of BV _DS of these transistors larger than the absolute value of BV _DS of T _N12 and T _P12 which respectively form the final stage of the output buffer. When the absolute values of BV _DS of T _N3 and T _P3 are larger than the absolute values of BV _DS of T _N12 and T _P12 , respectively,
Before T _N3 and T _P3 function as protective devices, the first stage gate electrode of the input buffer or T _N12 and T _P3
Noise charges will enter the CMOS inverter composed of _P12 , and the reason for existence of these T _N3 and T _P3 will be lost. In addition, the lower limit of the gate width of T _N3 and T _P3 is
It is preferable to make the determination in consideration of electrostatic breakdown in the first stage of the input buffer. Considering the current limit for the noise charge of the protective device itself, it is preferable that the gate widths of these T _N3 and T _P3 are narrow, but if the current driving capability of the protective device is low, the gate electrode of the first stage of the input buffer is low. This is because the noise charge that penetrates into the input buffer cannot be ignored and it becomes difficult to avoid electrostatic breakdown in the first stage of the input buffer.

Although the second embodiment is a protective device related to input / output terminals, this embodiment can be applied to a protective device related to output terminals or input terminals. Further, in this embodiment, if the gate length of the N-channel MOS transistor and the P-channel MOS transistor forming the final stage of the output buffer can be increased, the N-channel MOS transistor and the P-channel MOS transistor forming the protection device can be provided. Can be made the same as the structure of the N-channel MOS transistor and the P-channel MOS transistor (the connection of the metal wiring is different) constituting the protection device of the first embodiment.

[0047]

As described above, according to the semiconductor device of the present invention, in the CMOS transistor having the source / drain region of the LDD structure and the salicide structure, at least the insulating film spacer provided on the side surface of the gate electrode on the drain region side is provided. A protective device is configured by an N-channel MOS transistor and a P-channel MOS transistor that are formed of a laminated insulating film spacer including a first insulating film spacer and a second insulating film spacer, and an N-channel MOS transistor and a P-channel that form an internal circuit or the like. The side surface of each gate electrode of the MOS transistor is composed of only the second insulating film spacer.

Therefore, in the semiconductor device of the present invention, the parasitic resistance of the drain regions of the transistors forming the protection device is increased, and the resistance to noise charge penetrating into the drain regions of these transistors is improved.

[Brief description of drawings]

FIG. 1A is a schematic circuit diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 6B is a schematic sectional view of a semiconductor element used in the protective device of this embodiment.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the semiconductor device of the first embodiment.

FIG. 3 is a diagram for explaining the effect of the first embodiment, in which I of the semiconductor element used in the protection device of the present embodiment.
It is a graph of -V characteristic.

FIG. 4A is a schematic circuit diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 6B is a schematic sectional view of a semiconductor element used in the protective device of this embodiment.

FIG. 5 is a schematic cross-sectional view of the manufacturing process of the semiconductor device of the second embodiment.

FIG. 6 is a diagram for explaining the effect of the second embodiment, in which I of the semiconductor element used in the protection device of the present embodiment.
It is a graph of -V characteristic.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-type silicon substrate 2 P well 3 Field oxide film 4 Between gate oxidation 5,15,25 Gate electrode 6,6a, 16a, 16aa, 16b, 16ba, 2
6,26a N ^- type diffusion layer 7,17 Silicon nitride film spacer 8a, 8b, 8ba, 8bb, 8c, 8ca, 8cb
Silicon oxide film spacer 9a, 9b N ⁺ type diffusion layer 10 Titanium silicide film 11 Interlayer insulating film 12a, 12b, 22a, 22b, 32a, 32b
Metal wiring 36 P ⁻ type diffusion layer 39 P ⁺ type diffusion layer T _N1 , T _N2 , T _N3 , T _N12 N channel MOS transistor T _P1 , T _P2 , T _P3 , T _P12 P channel MOS transistor

Claims (3)

[Claims] 1. An insulating film spacer provided on at least a side surface of a gate electrode on the drain region side is composed of a laminated insulating film spacer of a first insulating film spacer and a second insulating film spacer, and has an LDD structure and a salicide structure. A first N-channel MOS transistor having a source / drain region and an insulating film spacer provided on at least a side surface on the drain region side are the laminated insulating film spacers, and a LDD structure having a salicide structure source / drain region is provided. A source / drain region having an LDD structure and a salicide structure, wherein the insulating film spacer provided on the side surface of the gate electrode is the second insulating film spacer. Provided on the side surface of the gate electrode and a second N-channel MOS transistor having Insulating spacer which is from the second insulating spacer, L
A semiconductor device having an internal circuit configured to include a second P-channel MOS transistor having a source / drain region of a salicide structure having a DD structure. 2. The final stage CMOS inverter of the output buffer is composed of the first N-channel MOS transistor and the first P-channel MOS transistor, and the first N-channel MOS transistor and the first N-channel MOS transistor The insulating film spacers on the side surface of the gate electrode on the source region side of the first P-channel MOS transistor are each formed of the second insulating film spacer, and the gate length of the first N-channel MOS transistor is the first insulating film spacer. 2. The gate length of the second P-channel MOS transistor is longer than that of the second N-channel MOS transistor, and the gate length of the first P-channel MOS transistor is longer than that of the second P-channel MOS transistor. Semiconductor device. 3. The gate electrode and source region of the first N-channel MOS transistor are connected to a ground line, and the gate electrode and source region of the first P-channel MOS transistor are connected to a power line. A drain region of the first N-channel MOS transistor and a drain region of the first P-channel MOS transistor are connected to an input terminal, an output terminal or an input / output terminal, and the first N-channel MOS transistor and the Insulating film spacers on the side surface of the gate electrode on the source region side of the first P-channel MOS transistor are formed of the laminated insulating film spacers, and the gate length of the first N-channel MOS transistor is the second insulating film spacer. Is equal to the gate length of the N-channel MOS transistor, and has the first P-channel MOS Gate length of the semiconductor device according to claim 1, wherein together with equal to the gate length of the second P-channel MOS transistor of the transistor.