JP2000124329A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of an isolated structure with an element isolating film and make a fine structure by using a first Schottky electrode as a common drain region in a first and second field effect CMOS transistors. SOLUTION: An nMOS transistor Tr 1 has a gate oxide film 3, a gate electrode 4 and a Schottky source electrode 5 formed on the surface of a ptype well layer 2. On this well layer 2 and a surface of an n-type Si substrate 1, a Schottky drain electrode 6 is formed, and p+ type contact layer 7 is selectively diffused and formed beneath the Schottky source electrode 5. In the meantime, a pMOS transistor Tr 2 has a gate oxide film 9, a gate electrode 10, a Schottky source electrode 10 and a Schottky drain electrode 6 formed on the surface of the n-type Si substrate 1, and n+ type contact layer 12 is selectively diffused and formed beneath the Schottky source electrode 10. The Schottky drain electrode 6 is a common drain electrode to the MOS transistors Tr 1, Tr 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Complement
The present invention relates to a semiconductor device having a transistor.

[0002]

2. Description of the Related Art A CMOS transistor is known as one of semiconductor devices. FIG. 11 shows a cross-sectional view of a conventional CMOS transistor. In the figure, reference numeral 71 denotes an n-type silicon substrate, and a p-type well layer 72 is selectively formed on the surface of the n-type silicon substrate 71.

A CMOS transistor has a p-type well layer 7
2 formed n-channel MOS transistor Tr1
And an n-channel MO formed on an n-type silicon substrate 71.
The n-channel MOS transistor Tr1 has an n + -type drain diffusion layer 76 and an p + -type drain diffusion layer 80 of an n-channel MOS transistor Tr2 connected to each other via a common drain electrode 85. ing.

In the figure, reference numerals 73 and 78 denote gate oxide films, 74 and
79 is a gate electrode; 75 and 81 are n + -type and p + -type source diffusion layers; 77 and 82 are p + -type and n + -type contact layers;
4,86 are source electrodes, 83,87 are contact electrodes,
Reference numerals 88, 89, and 90 indicate element isolation insulating films, respectively.

When the applied voltage Vin to the gate electrodes 74 and 79 is at a high level, the n-channel MOS transistor T
r1 is turned on, the p-channel MOS transistor Tr2 is turned off, and a voltage of Vss (Low) is output from the common drain electrode 85. On the other hand, when the applied voltage Vin to the gate electrodes 74 and 79 is at a low level, the n-channel MOS transistor Tr1 is turned off and the p-channel MOS transistor T1 is turned off.
r2 is turned on, and Vdd (Hig
The voltage of h) is output. In either state, since one of the MOS transistors is turned off, power consumption is suppressed.

However, this kind of conventional CMOS transistor has the following problems. That is,
An element isolation insulating film 89 for separating the two n + -type drain diffusion layers 76 and n + -type drain diffusion layers 80 is required, and there is a problem that miniaturization is hindered.

[0007]

As described above, the conventional C
The MOS transistor has a problem that an element isolation insulating film is required to separate the n + -type drain diffusion layer and the p + -type drain diffusion layer, and miniaturization is hindered.

The present invention has been made in consideration of the above circumstances, and has as its object to reduce the size of C, which is finer than before.
An object of the present invention is to provide a semiconductor device having a MOS transistor.

[0009]

Means for Solving the Problems To achieve the above object, a semiconductor device according to the present invention comprises a first conductive type semiconductor substrate in which a second conductive type channel is induced on a surface of the first conductive type semiconductor substrate.
A CMOS transistor comprising: a field-effect transistor of the type described above; and a second field-effect transistor having a channel induced on the surface of the second conductivity type well layer formed on the surface of the first conductivity type semiconductor substrate; And the second field-effect transistor uses the first Schottky electrode as a common drain region.

According to the present invention (claims 1 to 5), the drain region is constituted by the common first Schottky electrode.
N + type drain diffusion layer of S transistor and p channel M
A structure for separating the p + -type drain diffusion layer of the OS transistor from the p + -type drain diffusion layer by the element isolation insulating film becomes unnecessary, and as a result, miniaturization can be achieved by the element isolation insulating film.

Here, from the first Schottky electrode, C
Prevention of leakage current to an n-type p-type contact layer and a p-type contact layer, which is essential in a MOS transistor, utilizes a novel fact found by the present inventors. That is, according to the earnest study of the present inventors, the depletion layer extending from the interface between the first conductivity type semiconductor substrate and the second conductivity type well layer causes
It has been found that the generation of the leak current can be suppressed (claim 3).

Depending on the position of the junction interface between the first conductivity type semiconductor substrate and the second conductivity type well layer, there is a possibility that the effect of suppressing the leakage current by the depletion layer may be insufficient. In this case, as in the present invention (claims 4 and 5), a Schottky electrode having an appropriate work function, in other words, a material of an appropriate Schottky electrode and a first conductive type semiconductor substrate (a second conductive type well) are used. The leakage current can be sufficiently suppressed by the combination with the material of the layer).

[0013]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a CMOS transistor according to the embodiment.

In FIG. 1, reference numeral 1 denotes an n-type silicon substrate, and a p-type well layer 2 is provided on the surface of the n-type silicon substrate 1.
Are selectively formed by diffusion. In the p-type well layer 2, an n-channel MOS transistor Tr1 is formed.

This n-channel MOS transistor Tr1
Can be roughly divided into a gate oxide film 3 formed on the surface of the p-type well layer 2, a gate electrode 4 formed on the gate oxide film 2, a gate oxide film 3 formed on the surface of the p-type well layer 2, and a Schottky source electrode 5 that forms a Schottky junction with the p-type well layer 2; a Schottky junction formed on the surface of the p-type well layer 2 and the n-type silicon substrate 1; And a p + -type contact layer 7 selectively diffused on the surface of the p-type well layer 2 below the Schottky source electrode 5.

The Schottky drain electrode 6 is a common drain electrode used also as a drain electrode of the p-channel MOS transistor Tr2. The length of the Schottky drain electrode 6 is set shorter than the depletion layer 8 extending to both the n-type silicon substrate 1 and the p-type well layer 2.

In other words, the depletion layer 7 is formed so as to surround the Schottky drain electrode 6. In order for such a depletion layer 7 to be easily formed, p
The junction interface between the mold well layer 2 and the surface of the n-type silicon substrate 1 is set below the center of the Schottky drain electrode 6.

On the other hand, a p-channel MOS transistor Tr
2 is roughly divided into a gate oxide film 9 formed on the surface of the n-type silicon substrate 1, a gate electrode 10 formed on the gate oxide film 9, and a surface of the n-type silicon substrate 1, In addition, a Schottky source electrode 11 that makes a Schottky junction with the n-type silicon substrate 1, the above-described Schottky drain electrode 6, and n selectively diffused on the surface of the n-type silicon substrate 1 below the Schottky source electrode 10. + Contact layer 12.

Although the Schottky source electrodes 5 and 11 and the Schottky drain electrode 6 are formed of silicide, they may be formed of metal. In the case of forming with silicide, as shown in FIG.
A silicide layer 13 is formed on the side surface and the upper surface of 10.

When the voltage Vin applied to the gate electrodes 4 and 10 is at a high level, electrons tunnel through a Schottky barrier formed at the interface between the Schottky source electrode 5 and the n-type silicon substrate 1 so that the n-channel The MOS transistor Tr1 is turned on, the p-channel MOS transistor Tr2 is turned off, and V
ss (Low) voltage is output.

On the other hand, the voltage Vin applied to the gate electrodes 4 and 10
Is at a low level, the n-channel MOS transistor Tr1 is turned off, and holes tunnel through the Schottky barrier formed at the interface between the Schottky source electrode 11 and the n-type silicon substrate 1, so that the p-channel MOS transistor Tr2 Is turned on, and a voltage of Vdd (High) is output from the Schottky drain electrode 6. In either state, one of the MOS transistors is turned off.
Power consumption is suppressed as in the conventional case.

Further, according to the present embodiment, the output Vout
Schottky drain electrode 6 is composed of n-channel MOS transistor Tr1 and p-channel MOS transistor Tr
2 and the element isolation insulating film 89 shown in FIG. 11 becomes unnecessary, so that the element can be miniaturized.

Further, by setting the length of the Schottky drain electrode 6 to be shorter than the width of the depletion layer 7 extending to both the n-type silicon substrate 1 and the p-type well layer 2, The depletion layer 7 can sufficiently suppress the leak current due to the electrons flowing through the + type contact layer 12 and the leak current due to the holes flowing from the Schottky drain electrode 6 to the p + type contact layer 7. The effect that the depletion layer 7 can suppress the leak current is a novel fact first discovered by the present inventors.

Further, by using the Schottky source electrodes 5 and 11, the p + -type contact layer 7 is formed on the surface of the p-type well layer 2 under the Schottky source electrode 5, and the n + -type contact layer 12 is formed on the Schottky source layer 5. It can be formed on the surface of the n-type silicon substrate 1 under the source electrode 11. As a result, the element isolation insulating films 88 and 90 shown in FIG. 11 become unnecessary, and thus the element can be miniaturized.

In general, even at the same applied voltage, the spread of the depletion layer from the metal / semiconductor interface at the Schottky junction is smaller than that at the p-type semiconductor layer / p-type semiconductor layer interface at the pn junction. As a result, the CMOS transistor of this embodiment using the Schottky drain electrode 6 suppresses the short-channel effect as compared with the conventional CMOS transistor, so that the device can be miniaturized.

As described above, according to the present embodiment, the element isolation insulating films 88, 89, and 90 shown in FIG. 11 become unnecessary, and the short channel effect is suppressed. Will be realized.

Explaining the miniaturization in detail, assuming that the design rule is F, in the case of the conventional CMOS transistor of FIG. 11, as shown in FIG. The area is F, which is about 18F in total. On the other hand, in the case of the CMOS transistor of the present embodiment, as shown in FIG. 2B, the area is 8F, and the ratio is 8F / 18F = 0.44. Become. Therefore, it can be reduced to about 45% of the conventional size.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a CMOS transistor according to the embodiment. Note that the same reference numerals as in FIG. 1 denote the same parts as in FIG. 1, and a detailed description thereof will be omitted (the same applies to embodiments later than the second embodiment).

The feature of the CMOS transistor of this embodiment is that it has a structure advantageous in terms of process. That is, conventionally, a step of implanting n-type impurity ions into a polycrystalline silicon film as the gate electrode 4 and a step of
And a step of implanting p-type impurity ions into the polycrystalline silicon film as above was required. However, the present element can be formed without going through these ion implantation steps, whereby the number of steps can be reduced. .

FIGS. 4 and 5 show the CMOS of this embodiment.
FIG. 7 is a process cross-sectional view illustrating the method for manufacturing the transistor.

First, as shown in FIG. 4A, a gate oxide film 9 is formed on the surface of an n-type silicon substrate 1 by thermal oxidation, and then a p + -type polysilicon serving as a gate electrode of a p-channel MOS transistor Tr2 is formed. A crystalline silicon film 10 is formed by a CVD method.

This p + -type polycrystalline silicon film 10 is not used for gate electrode 4 of n-channel MOS transistor Tr1. Therefore, a step of selectively implanting p-type impurity ions into a portion to be the gate electrode 10 becomes unnecessary, and the number of steps can be reduced accordingly.

Next, as shown in FIG. 4B, an opening is formed in a region to be the p-type well layer 2 by patterning the p + -type polycrystalline silicon film 10, and the substrate surface is formed through this opening. Then, boron ions (B @ +) are implanted, followed by annealing to form a p-type well layer 2.

Next, as shown in FIG. 4C, after a nitride film 14 is formed on the surface of the p + -type polycrystalline silicon film 10 by thermal nitridation, the gate oxide film 9 on the p-type well layer 2 is selected. Removed.

Next, as shown in FIG. 4D, after a gate oxide film 3 is formed on the surface of the p-type well layer 2 by thermal oxidation, an n + -type polycrystal serving as a gate electrode of the n-channel MOS transistor Tr1 is formed. A silicon film 4 is formed by a CVD method.

This n + -type polycrystalline silicon film 4 is not used for the gate electrode 10 of the p-channel MOS transistor Tr2. Therefore, a step of selectively implanting n-type impurity ions into a portion to be the gate electrode 4 becomes unnecessary, and
The number of steps can be reduced accordingly.

Next, as shown in FIG. 4E, the gate electrode 4 is formed by etching the n + -type polycrystalline silicon film 4 using the resist pattern 15 as a mask.
At this time, an electrode (hereinafter, referred to as a dummy gate electrode) 4 'is formed on the formation region of the p-channel MOS transistor.

Next, as shown in FIG. 4F, after the resist pattern 15 is stripped, the exposed gate oxide film 3 is removed.
Is selectively removed.

Next, as shown in FIG. 5 (g), the exposed silicon surface is silicided to form a Schottky source electrode 5, a Schottky drain electrode 6a, and a silicide layer 13a.

Here, the silicide layer 13a formed on the side and top surfaces of the dummy gate electrode 4 'is used as a mask when patterning a p + -type polycrystalline silicon film which will become the gate electrode 10 in a later step. The dummy gate electrode 4 'is formed simultaneously with the gate electrode 4 in the step of FIG. 4E, and similarly, the silicide layer 1 on the dummy gate electrode 4' is formed.
3a is also formed simultaneously with the silicide layer 13a on the gate electrode 4 in this step.

Therefore, the mask (silicide layer 13a on dummy gate electrode 4 ') used for patterning the p + -type polycrystalline silicon film can be formed without increasing the number of steps.

Next, as shown in FIG. 5H, after removing the exposed nitride film 14, the p + -type polycrystalline silicon film 10 is etched using the silicide layer 13a as a mask to form a gate electrode. Form 10.

Next, as shown in FIG. 5I, the silicide layer 13a, the dummy gate electrode 4 'and the nitride film 14 are polished by chemical mechanical polishing (CMP).
ing).

Next, as shown in FIG. 5 (j), the exposed gate oxide film 9 is removed and the silicon surface that appears is silicided to form a Schottky drain electrode 6b, a silicide layer 13b and a Schottky layer. The source electrode 11 is formed. In this step, the common Schottky drain electrode 6 is completed. Next, as shown in FIG. 5 (k), arsenic ions (As @ +) are added to the substrate via the Schottky source electrode 11 using the resist pattern 17 as a mask. The n + -type contact layer 12 is formed by implanting it into the surface and then annealing. After that, the resist pattern 17 is peeled off.

Finally, as shown in FIG. 5 (l), using the resist pattern 18 as a mask, boron ions (As +) are implanted into the surface of the substrate via the Schottky source electrode 5, followed by annealing. Then, a p @ + -type contact layer 7 is formed to complete a CMOS transistor.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a CMOS transistor according to the embodiment.

This embodiment is different from the first embodiment in that the entirety of the Schottky drain electrode 6 is formed in the p-type well 2.
In other words, the Schottky drain electrode 6 is formed at a position surrounded by the p-type well layer 2. With such a configuration, effects similar to those of the first embodiment can be obtained.

However, n of the Schottky drain electrode 6
The end on the side of the channel MOS transistor Tr1 may not be covered by the depletion layer, and as a result, a leak current may flow due to holes.

However, as a Schottky drain electrode 6, a barrier against holes injected from the Schottky drain electrode 6 into the p-type well layer 2 prevents electrons injected from the Schottky drain electrode 6 into the p-type well layer 2. If a material having a work function higher than that of the barrier is used, generation of a leak current can be prevented.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a CMOS transistor according to the embodiment.

This embodiment is different from the first embodiment in that the entirety of the Schottky drain electrode 6 is formed on the surface of the n-type silicon substrate 1, in other words, the Schottky drain electrode 6 is made of n-type silicon. That is, it is formed at a position surrounded by the substrate 1. With such a configuration, effects similar to those of the first embodiment can be obtained.

However, the p of the Schottky drain electrode 6
There is a possibility that the end on the channel MOS transistor Tr2 side is not covered by the depletion layer, and as a result, a leak current due to electrons may flow.

However, as the Schottky drain electrode 6, a barrier against electrons injected from the Schottky drain electrode 6 into the n-type silicon substrate 1 is provided for a hole injected from the Schottky drain electrode 6 into the n-type silicon substrate 1. If a material having a work function higher than that of the barrier is used, generation of a leak current can be prevented.

(Fifth Embodiment) FIG. 8 shows a fifth embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a CMOS transistor according to the embodiment.

The difference between the present embodiment and the first embodiment is that the junction interface between the surface of the n-type silicon substrate 1 and the surface of the p-type well layer 2 is located between the center of the Schottky drain electrode 6 and the p-channel MOS transistor Tr2. That is, it is formed at a position shifted to the side. Since the p-type well layer 2 is formed by diffusion, a junction interface below the junction interface is similarly formed at a position shifted toward the p-channel MOS transistor Tr2. With such a configuration, effects similar to those of the first embodiment can be obtained.

However, n of the Schottky drain electrode 6
The end on the channel MOS transistor Tr1 side may not be covered by the depletion layer, and as a result, a leak current may flow due to holes.

However, as the Schottky drain electrode 6, a barrier against holes injected from the Schottky drain electrode 6 into the p-type well layer 2 prevents electrons injected from the Schottky drain electrode 6 into the p-type well layer 2. If a material having a work function higher than that of the barrier is used, generation of a leak current can be prevented.

(Sixth Embodiment) FIG. 9 shows a sixth embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a CMOS transistor according to the embodiment.

This embodiment is different from the first embodiment in that the junction interface between the surface of the n-type silicon substrate 1 and the p-type well layer 2 and the junction thereunder are located from the center of the Schottky drain electrode 6. n-channel MO
It is formed at a position shifted toward the S transistor Tr1. With such a configuration, effects similar to those of the first embodiment can be obtained.

However, the p of the Schottky drain electrode 6
There is a possibility that the end on the side of the channel MOS transistor Tr1 is not covered by the depletion layer, and as a result, a leak current due to electrons may flow.

However, as the Schottky drain electrode 6, a barrier against electrons injected from the Schottky drain electrode 6 into the n-type silicon substrate 1 is provided for a hole injected from the Schottky drain electrode 6 into the n-type silicon substrate 1. If a material having a work function higher than that of the barrier is used, generation of a leak current can be prevented.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the material of the Schottky source electrode 5 may be a material having a low barrier against silicon for electrons, and the material of the Schottky source electrode 11 may be a material having a high barrier against silicon for holes. . By selecting such a material, tunnel resistance is reduced and driving force is improved.

In order to form a CMOS transistor using different materials for the Schottky source electrode 5 and the Schottky source electrode 11 as described above, the second embodiment (FIGS. 5G and 5J) ), The metal (first metal) used in the step of forming the Schottky source electrode 8, the Schottky drain electrode 6a, and the silicide layer 13a.
A metal having a different work function may be used between the metal (metal) and the metal (second metal) used in the process of forming the Schottky drain electrode 6b, the silicide layer 13b, and the Schottky source electrode 11.

More specifically, a first metal having a work function that increases the barrier against silicon for holes and a second metal having a work function that reduces the barrier for electrons may be used as the second metal. By using such a combination of the first and second metals, a leakage current due to holes flowing from the Schottky drain electrode 6 to the Schottky source electrode 5, and a leakage current due to electrons flowing from the Schottky drain electrode 6 to the Schottky source electrode 11 are obtained. Leakage current can be further reduced.

The present invention can be applied to the case where an SOI substrate is used. FIG. 10 shows a cross-sectional view when the CMOS transistor of the first embodiment is formed on an SOI substrate. In the figure, reference numeral 19 denotes a supporting substrate, and 20 denotes a buried oxide film. As the SOI substrate, for example, a substrate formed by a direct bonding method is preferably used.

In the case of the device shown in FIG. 10, in addition to the advantages of using the SOI substrate of high driving force and high radiation resistance,
The p + -type contact layer 7 and the n + -type contact layer 12 can also suppress the floating effect, which is a drawback of the SOI substrate.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0069]

As described in detail above, according to the present invention, n
Since the drain regions of the p-type MOS transistor and the p-type MOS transistor are formed of a common first Schottky electrode, the n-type drain diffusion layer of the n-channel MOS transistor and the p-type Since the structure for separating the diffusion layer from the diffusion layer by the element isolation insulating film becomes unnecessary, the miniaturization of the CMOS transistor can be achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a CMOS transistor according to a first embodiment of the present invention;

FIG. 2 is an effect (miniaturization) of the CMOS transistor of FIG. 1;
Diagram for explaining

FIG. 3 is a sectional view showing a CMOS transistor according to a second embodiment of the present invention;

FIG. 4 is a process sectional view showing the first half of the method of manufacturing the CMOS transistor;

FIG. 5 is a process sectional view showing the latter half of the manufacturing method of the CMOS transistor;

FIG. 6 is a sectional view showing a CMOS transistor according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing a CMOS transistor according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a CMOS transistor according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing a CMOS transistor according to a sixth embodiment of the present invention.

FIG. 10 shows a CMOS transistor according to a seventh embodiment,
Sectional view when formed on OI substrate

FIG. 11 is a sectional view showing a conventional CMOS transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type silicon substrate 2 ... p-type well layer 3 ... gate oxide film 4 ... gate electrode 4 ... dummy gate electrode 5 ... Schottky source electrode (second Schottky electrode) 6, 6a, 6b ... Schottky drain electrode (First Schottky electrode) 7 depletion layer 8 p + type contact layer (second conductivity type contact layer) 9 gate oxide film 10 gate electrode 11 Schottky source electrode (third Schottky electrode) 12 n + type contact layer (first conductivity type contact layer) 13, 13a, 13b silicide layer 14 nitride film 15 resist pattern 16a, 16b, 16 silicide layer 17, 18 resist pattern 19 support substrate 20 ... buried oxide film Tr1 ... n-channel MOS transistor (second MOS
Transistor) Tr2 ... p-channel MOS transistor (first MOS)
Transistor)

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Akira Nishiyama 8F Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama Office 5F048 AA01 AA07 AA09 AC03 BA01 BB06 BB07 BC02 BC05 BC19 BE09 BE10 BF17

Claims (5)

[Claims] 1. A first field-effect transistor in which a channel of a second conductivity type is induced on a surface of a semiconductor substrate of a first conductivity type;
A CMOS transistor comprising a second field effect transistor having a channel induced on a surface of a second conductivity type well layer formed on a surface of the first conductivity type semiconductor substrate; Wherein the first Schottky electrode is used as a common drain region. 2. The semiconductor device according to claim 1, wherein the first field-effect transistor has a second Schottky electrode formed on a surface of the first conductivity type semiconductor substrate as a source region, and the second Schottky electrode below the second Schottky electrode. A first conductivity type contact layer on a surface of the one conductivity type semiconductor substrate, wherein the second field effect transistor uses a third Schottky electrode formed on a surface of the second conductivity type well layer as a source region; 2. The semiconductor device according to claim 1, further comprising a second conductivity type contact layer on a surface of said second conductivity type well layer below said third Schottky electrode. 3. The semiconductor device according to claim 1, wherein said first conductive type semiconductor substrate and said second conductive type semiconductor substrate are provided.
These bonding interfaces on the surface of the conductive type well layer are formed at positions traversed by the first Schottky electrode, and the width of the first Schottky electrode is equal to the width of the first conductive type semiconductor substrate and the second conductive type. 2. The semiconductor device according to claim 1, wherein the width of the depletion layer is set to be shorter than the width of a depletion layer extending from a junction interface with the conductive type well layer. 4. The method according to claim 1, wherein the first Schottky electrode is connected to the first Schottky electrode.
The first Schottky electrode is formed on the surface of the conductive type semiconductor substrate or the second conductive type well layer; and the first Schottky electrode is formed on the surface of the first conductive type semiconductor substrate. The electrode is connected to the first Schottky electrode from the first Schottky electrode.
A barrier for a first polarity carrier having the same polarity as a majority carrier of the first conductivity type semiconductor substrate injected into the first conductivity type semiconductor substrate is injected from the first Schottky electrode into the first conductivity type semiconductor substrate; The second conductivity type well layer has a work function higher than a barrier for the second polarity carrier having the same polarity as the majority carrier, and the first Schottky electrode is formed on the surface of the second conductivity type well layer. In the case where the first Schottky electrode is provided, a barrier to the second polarity carrier injected from the first Schottky electrode into the second conductivity type well layer is formed by the first Schottky electrode. From the electrode to the second
2. The semiconductor device according to claim 1, wherein the semiconductor device has a work function higher than a barrier to the first polarity carrier injected into the conductive well layer. 3. 5. The semiconductor device according to claim 1, wherein said first conductive type semiconductor substrate and said second conductive type semiconductor substrate are provided.
When these junction interfaces on the surface of the conductivity type well layer are traversed by the first Schottky electrode, a depletion layer extending from the first conductivity type semiconductor substrate to the second conductivity type well layer is When the first Schottky electrode is not formed so as to surround the end of the first Schottky electrode on the side of the first field-effect transistor, the first Schottky electrode is separated from the first Schottky electrode by the first conductivity type semiconductor. A barrier for a first polarity carrier having the same polarity as a majority carrier of the first conductivity type semiconductor substrate injected into the substrate;
Having a work function higher than a barrier for a second polarity carrier having the same polarity as a majority carrier of the second conductivity type well layer injected from the Schottky electrode into the first conductivity type semiconductor substrate; If the depletion layer extending from the one conductivity type semiconductor substrate to the second conductivity type well layer is not formed so as to surround the end of the first Schottky electrode on the second field effect transistor side, The Schottky electrode has a barrier against the second polarity carrier injected from the first Schottky electrode into the second conductivity type well layer, and a barrier from the first Schottky electrode to the second conductivity type well layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a work function higher than a barrier to the injected first polarity carrier.