JP2846329B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device suitable for forming a shallow impurity diffusion layer in which impurity diffusion is suppressed.

[Conventional technology]

A conventional method for forming an impurity diffusion layer in the manufacture of a semiconductor device is a method in which an impurity is introduced into a main surface of a semiconductor substrate by ion implantation and then thermal diffusion is performed as described in JP-A-63-136661. Had been implemented. Also, as described in JP-A-63-9924, the formation of a shallow impurity diffusion layer is performed by a method using lamp heating after introducing impurities by ion implantation. The injection of fluorine into the interface between the substrate and the insulating film is described in JP-A-61-90431. Further, as described in JP-A-63-136645, an epitaxial substrate is manufactured by forming an epitaxially grown layer having a low impurity concentration on a semiconductor substrate having a high impurity concentration. Was. In addition to the above conventional example,
The buried type impurity-introduced layer using high-energy impurity implantation has been formed by short-time annealing in order to reduce the redistribution of impurities, as described in JP-A-63-124519.

[Problems to be solved by the invention]

Among the above-mentioned conventional methods, the formation of the impurity diffusion layer by thermal diffusion has a speed of diffusion due to ion implantation damage or the like, so that the diffusion depth becomes large, and no consideration is given to cope with miniaturization of semiconductor elements. In addition, there is a problem that it is difficult to manufacture a fine semiconductor element. In addition, in the above-described conventional method using lamp heating or short-time annealing, rapid heating and
Because of the quenching process, there is a problem that the leakage current at the junction in the semiconductor element increases. Furthermore, in the method based on the epitaxial growth, a high-concentration impurity diffuses into the epitaxial layer by autodoping, so that the low-concentration region of the epitaxial layer is narrowed,
There was a problem that it was difficult to obtain a thin epitaxial layer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing a disadvantageous impurity diffusion in a semiconductor element and the above-described auto-doping, and forming a shallow impurity-doped layer without increasing junction leakage current. It is in.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which impurity diffusion is performed by using fluorine in at least one of a front surface and a rear surface of a silicon semiconductor substrate or a semiconductor substrate in which impurity diffusion is performed. In this state, impurity diffusion is performed.

Further, in order to cause the fluorine to be present on the front surface, the back surface, or inside of the substrate, regions having crystal defects are formed in the respective regions, and fluorine is trapped in the defect regions by thermal diffusion or ion implantation of the fluorine. That's what we did. Further, in order to control the amount of trapped fluorine, the amount of defects in the defect region is controlled.

In the above method, in order to remove a defect region where fluorine on the surface of the semiconductor substrate exists, after the impurity diffusion,
The etching or the oxidation is performed. Here, the impurity diffusion is usually performed in a state where the surface of the semiconductor substrate is covered with an insulating film, and in order to achieve the above-mentioned object, even in the vicinity of the surface, the interface between the semiconductor substrate and the insulating film is formed. Fluorine is trapped.

In order to achieve the above object, an impurity diffusion layer is formed using a semiconductor substrate containing fluorine. Here, the fluorine-containing distribution in the semiconductor substrate is such that the fluorine is uniformly distributed in the substrate, or such that fluorine is not contained on the surface of the substrate but is contained inside the substrate.

[Action]

Fluorine present on the substrate surface acts to prevent interstitial Si atoms from diffusing into the inside of the Si substrate in impurity diffusion caused by a mechanism via diffusion of interstitial Si atoms in a silicon (Si) substrate. The impurity diffusion generated by the mechanism through the diffusion of interstitial Si atoms includes, for example, diffusion of boron, phosphorus, arsenic, and the like. Thereby, the impurity does not diffuse deeply. Fluorine existing inside the substrate acts to prevent the interstitial Si atoms from diffusing deeper. This prevents the impurity from diffusing beyond its depth. Therefore, the diffusion depth of the impurity can be controlled by the depth of the fluorine existing region inside the substrate.

Since a crystal defect in a semiconductor substrate acts as a fluorine trap site, a fluorine existing region can be localized in a desired region of a substrate by forming a defect at a desired position. In the case of a Si substrate, the solid solubility of fluorine is about 1 × 10 ¹⁸ / cm ³ or less in a region where there is no defect.
At least 10 ²⁰ / cm ³ of fluorine should be present. In this manner, the amount of fluorine can be reduced in a region where fluorine is unnecessary, and high-concentration fluorine can be present only in a portion where fluorine is required. That is, in a defect region requiring fluorine having a solid solubility of fluorine (about 1 × 10 ¹⁸ / cm ³ or less) or more, about 1 × 10 ¹⁸ / cm ³ or more or about 1 × 10 ²⁰ / cm ³ or more Can be adjusted so that fluorine having a solid solubility (about 1 × 10 ¹⁸ / cm ³ or less) or less exists in a region where there is no defect that does not require fluorine. Therefore, by forming the defect area on the surface of the substrate, inside the substrate, or on the back surface of the substrate, a fluorine existing area can be formed at a desired portion. When fluorine is made to exist on the surface of the semiconductor substrate by the above method, the impurity diffused through the interstitial Si atoms is not diffused deeply. Also,
When fluorine is present inside the semiconductor substrate by the above method,
The amount of impurities diffused deeper than the fluorine existing region can be suppressed. Further, when fluorine is present on the back surface of the substrate by the above-described method, the above-described impurity diffusion from the back surface can be prevented, so that the state of the back surface does not significantly change.

Further, when the defect amount in the defect region in the semiconductor substrate, for example, the defect density is kept constant, the amount of fluorine trapped can be controlled by controlling the width of the defect region. Thereby, the diffusion amount of interstitial Si atoms is also controlled, and as a result, impurity diffusion can be controlled. Therefore, an impurity diffusion layer having a different impurity diffusion depth can be formed in a desired region.

The defect region is not changed by the heat treatment process such as the impurity diffusion. This is because the fluorine present in the defect region prevents the release of interstitial Si atoms,
This is because there is no defect movement due to the movement of Si atoms. However, on the surface of the semiconductor substrate, if the presence of the defective area causes a problem, it is necessary to remove the defective area. Therefore, after the impurity diffusion, the defective region is removed by performing etching or oxidation.

Further, fluorine present at the interface between the semiconductor substrate and the insulating film also acts to prevent impurity diffusion involving interstitial Si atoms. Therefore, not only impurity diffusion into the inside of the semiconductor substrate but also impurity diffusion near the interface is suppressed.

As is clear from the above description, the semiconductor substrate containing fluorine functions as a substrate for suppressing impurity diffusion. Since the fluorine content distribution determines the impurity diffusion distribution,
When the fluorine content distribution is uniform in the substrate, the effect of suppressing impurity diffusion can be uniform in the substrate. In addition, the above-mentioned fluorine content distribution does not include fluorine on the substrate surface, and includes fluorine within the substrate, so that impurity diffusion from the substrate surface is not affected, and impurity diffusion reaching the inside of the substrate is suppressed. To do it. In this case, in the impurity diffusion from the substrate surface, the diffusion is fast in the vicinity of the surface and the diffusion is slow in the inside, so that the impurity concentration distribution can be made closer to a step-like impurity concentration distribution. Further, in the impurity diffusion from inside the substrate, another impurity diffusion can be performed at a normal speed from the substrate surface while suppressing diffusion to the surface side.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. First
FIGS. 1A and 1B are explanatory views of a case where the present invention is applied to the formation of a boron diffusion layer, wherein FIGS.
FIG. 2 (c) is a diagram showing the concentration distribution of boron in the diffusion layer, and FIG. 2 is an explanatory view in the case where the present invention is applied to the formation of a phosphorus diffusion layer, and FIGS. 2 (a) and 2 (b) each show a manufacturing process. Figure,
(C) is a diagram showing the concentration distribution of phosphorus in the diffusion layer, and FIG.
The figure is an explanatory view of the case where the present invention is applied to the formation of a well layer,
(A) to (d) are manufacturing process diagrams, (e) is a diagram showing an impurity concentration distribution, and FIG. 4 is an explanatory diagram of another case in which the present invention is applied to the formation of a well layer, wherein (a) to (d) ) Is the manufacturing process diagram,
(E) is a diagram showing an impurity concentration distribution, and FIGS.
(D) is a diagram showing each step when the present invention is applied to the manufacture of a bipolar transistor, and FIGS. 6 (a) to (c) show respective steps when the present invention is applied to the manufacture of a complementary MOS transistor. FIG.

First Embodiment As shown in FIG. 1A, a first embodiment in which the present invention is applied to the formation of a boron diffusion layer is an n-type, (100), 10Ω
A silicon substrate 1 having a thickness of 10 cm was thermally oxidized to form a silicon oxide film (SiO ₂ film) 2 having a thickness of 10 nm, and a fluorine existing region 3 was formed on the surface of the Si substrate 1 by ion implantation.
At this time, fluorine was ion-implanted at 50 keV by 1 × 10 ¹⁵ / cm ² . Thereafter, boron is ion-implanted at 30 keV by 2 × 10 ¹⁵ / cm ² , and heat diffusion is performed at 900 ° C. for 1 hour in a nitrogen atmosphere (N ₂ ). As shown in FIG. 4
Was formed. The concentration distribution in the boron diffusion layer 4 obtained at this time is represented by a curve 5 shown in (c), and is about 0.15 μm deeper than the concentration distribution 6 when fluorine is not present.

Second Embodiment As shown in FIG. 2 (a), a second embodiment in which a phosphorus diffusion layer is formed is formed by thermally oxidizing a p-type, (100), 10Ω.cm Si substrate 7 to a thickness of 10 nm. A SiO ₂ film 8 having a thickness is formed, and a fluorine existing region 9 is formed inside the Si substrate 7 by ion implantation.
Was formed. At this time, fluorine was ion-implanted at 600 keV by 5 × 10 ¹⁴ / cm ² . Then, 5x1 phosphorus at 30keV
Implantation of 0 ¹⁵ / cm ² was performed, and thermal diffusion was performed in N ₂ at 1000 ° C. for 30 minutes to form a phosphorus diffusion layer 10 as shown in FIG.
The concentration distribution of the phosphorus diffusion layer 10 obtained at this time is represented by a curve (c).
As shown in Fig. 11, the concentration distribution in the absence of fluorine
Compared with 12, the concentration was higher on the surface side and the diffusion depth was shallower.

Third Embodiment In FIG. 3 showing a third embodiment in which an n-type well layer is formed by phosphorus diffusion, a p-type, (100), 10 Ω · cm
After forming an SiO ₂ film 13 having a thickness of 20 nm on the surface of the substrate 7 as shown in FIG. 2A, 5 × 10 ¹⁵ / cm ^{2 of} Si ions are implanted at 30 keV. and, 900 in N ₂
Heat treatment was performed at 10 ° C. for 10 minutes to form a defect region 14 near the Si surface. Then, after removing the SiO ₂ film 13, a heat treatment was performed at 900 ° C. for 10 minutes in a nitrogen trifluoride atmosphere (NF ₃ ) to trap fluorine in the defect region 14 (b).
Thereafter, an SiO ₂ film 15 is formed to a thickness of 20 nm, and phosphorus is applied at 5 × 10 5 at 150 keV.
^An n-type well layer 16 was formed by ion implantation at ¹² / cm ² and well diffusion in N ₂ at 1150 ° C. for 20 hours as shown in FIG. Next, after removing the SiO ₂ film 15, a 50 nm SiO ₂ film 17 is formed by thermal oxidation as shown in FIG.
The defect region 14 was oxidized. The phosphorus concentration distribution of the well layer at this time is as shown by a curve 18 in (e), and the distribution curve when the formation of the defect region 14 and the fluorine treatment are not performed.
Very shallow compared to 19.

Fourth Embodiment FIG. 4 shows a fourth embodiment showing the formation of a p-type retrograde well layer as another embodiment of the well layer formation. 4th
As shown in FIG. 1A, p-type, (100), 10Ω · cm Si
After forming a SiO ₂ film 20 having a thickness of 30 nm using the substrate 7, boron is ion-implanted at 5 × 10 ¹⁴ / cm ² at 1.2 MeV, and heat treatment is performed at 800 ° C. for 10 minutes in N _2. Perform p-type high concentration layer 2
Formed one. At this time, a defect region exists inside the p-type high concentration layer 21. Then, after removing the SiO ₂ film 20, a heat treatment was performed in NF ₃ at 900 ° C. for 30 minutes to trap fluorine in a defect region inside the p-type high concentration layer 21 (b). Thereafter, an SiO ₂ film 22 having a thickness of 30 nm is formed,
As shown in (c), boron is applied at 5 × 10 ¹¹ / cm ² and 50 at 300 keV.
After ion-implanting 5 × 10 ¹¹ / cm ^{2 at 0} keV and 5 × 10 ¹¹ / cm ² at 800 keV, heat treatment is performed at 1000 ° C. for 2 hours in N ₂ , and as shown in FIG. Layer 23 was formed.
Then, a field oxide film 24 having a thickness of 500 nm was formed by a normal selective oxidation method as shown in FIG. here,
The heat treatment at the time of the selective oxidation is at 1000 ° C. for 2 hours. The boron concentration distribution of the retrograde well layer obtained in this example is as shown by a curve 25 in (e), and the concentration on the surface of the Si substrate is kept almost constant. However, the distribution without the conventional fluorine trap is as shown by a curve 26, and an increase in the surface concentration due to the diffusion of boron is observed. This increase in the surface concentration changes the characteristics of the junction and the SiO ₂ / Si interface formed in the well layer, and makes it difficult to control the surface concentration. Therefore, according to the present embodiment, unnecessary boron diffusion by fluorine can be suppressed, and the problem as in the above-described conventional example does not occur.

Fifth Embodiment FIG. 5 shows a fifth embodiment in which the present invention is applied to the manufacture of a bipolar transistor. As shown in FIG.
On a surface of an n-type, (100), 0.005Ω · cm
An epitaxial growth layer 28 having a thickness of 5 Ω · cm and a thickness of 2 μm is formed. The Si substrate 27 contains phosphorus as an n-type impurity and fluorine having a concentration of 5 × 10 ¹⁸ / cm ³ ,
The epitaxial growth layer 28 contains only phosphorus. On the main surface of the substrate, as shown in (b), device isolation grooves buried with a 50 nm-thick SiO ₂ film 29 and a SiO ₂ film 30 were formed. Then (c), the modulo-containing 3 × 10 ¹⁴ / cm ² by ion implantation and at 100 keV, 90 in N ₂
Heat treatment at 0 ° C. for 1 hour to form a p-type layer 3 serving as a base region
After forming 1, Si is applied to the portions 32, 33 and 34 serving as the emitter regions at 1 × 10 ¹⁴ / cm ² and 1 × 10 ¹⁵ / cm at 30 keV, respectively.
performed cm by ² and 1 × 10 ¹⁶ / cm ² Ion implantation, 900 ° C. in NF _3, and a heat treatment for 10 minutes, the defective area 32, 33 and 3
Formed four. At this time, the amount of defects in the defect regions 32, 33 and 34 increased in the above order, and the amount of fluorine trapped in each of the defect regions also increased in the above order. Then, phosphorus is ion-implanted into the emitter regions 32, 33 and 34 at 30 keV by 5 × 10 ¹⁵ / cm ² and heat-treated at 1000 ° C. for 3 minutes in N ₂ to form n-type layers 35, 36 and 37. Was formed as shown in (d). At this time, the depth of each of the n-type layers 35, 36 and 37 is 0.3 μm, 0.25 μm and 0.2 μm, and the p-type layer 31 at a portion deeper than the n-type layers 35, 36 and 37 is 0.35 μm, 0.3 μm and 0.25 respectively
μm. Therefore, although the base width is the same as 0.1 μm, the boron concentration in the intrinsic base region increases in the above order, so that the characteristics such as withstand voltage, amplification or frequency can be improved under the same boron and phosphorus implantation / heat treatment conditions. It can be made with different bipolar transistors. That is,
Without changing the conditions for forming the emitter / base, devices having various characteristics can be manufactured depending on the defect amount (that is, the trapped fluorine amount) in the defect region. When fluorine is not contained in the Si substrate 27, the substrate is subjected to auto-doping during epitaxial growth and subsequent heat treatment.
Although the phosphorus diffusion from the 27-type increases and the breakdown voltage of the base / collector junction decreases, in the present embodiment, the phosphorus diffusion due to the above-described auto-doping and subsequent heat treatment is suppressed. There is no decline. As described above, in this embodiment, elements having various characteristics can be easily formed without deteriorating the element characteristics.

Sixth Embodiment A sixth embodiment in which the present invention is applied to the manufacture of a complementary MOS transistor will be described with reference to FIG. 2 × 10 ¹⁸ / c fluorine
Using a p-type (100), Si substrate 38 that contains m ³ uniformly,
After depositing an amorphous Si film having a thickness of 500 nm on the back surface, the film was allowed to stand in fluorine plasma to add fluorine to the polycrystalline Si film. Then, a SiO ₂ film 39 having a thickness of 30 nm is formed as shown in FIG. 6 (a), and phosphorus and boron are each deposited at 50 keV.
Ion implantation at 1 × 10 ¹² / cm ² in N ₂ at 1100 ° C.
By performing heat treatment for a long time, an n-type well layer 40 and a p-type well layer 41 were formed. At this time, fluorine was trapped at the interface between the SiO ₂ film 39 and the Si substrate 38 on the Si surface. In addition, fluorine is present in the defects formed when the amorphous Si is grown. Then, after removing the SiO ₂ film 39, a field oxide film 42 having a thickness of 500 nm is formed by a normal selective oxidation method.
Forming a, 3 × 10 ¹³ in 2MeV phosphorus to the n-type well layer 40
/ cm ² and 1M of boron in the p-type well layer 41
Implant 5 × 10 ¹³ / cm ^{2 with} eV and 1000 in N ₂
A heat treatment was performed at 1 ° C. for one hour to form an n-type implanted layer 43 and a p-type buried layer 44. The field oxide film 42
Below and within the p-type well layer, the surface concentration is 2 ×
A 10 ¹⁷ / cm ³ p-type channel stopper layer 45 is formed as shown in FIG. After this, a gate SiO _{2 with} a thickness of 10 nm
The film 46 was formed. Next, the polycrystalline Si film doped with phosphorus
A gate electrode is formed by 47, boron is implanted into the n-type well layer 40 at 10 keV at 2 × 10 ¹⁵ / cm ² , and arsenic is implanted into the p-type well layer 41 at 40 keV at 5 × 10 ¹⁵ / cm ^2. Then, heat treatment is performed at 950 ° C. for 10 minutes in N _{2 to} form a p-type source / drain layer 48 and an n-type source / drain layer 49,
It was formed as shown in FIG. Thereafter, steps such as ordinary electrode formation were performed to manufacture a complementary MOS transistor.

According to the present embodiment, since the diffusion of phosphorus and boron in the n-type well layer 40 and the p-type well layer 41 is suppressed by fluorine, the diffusion not only in the depth direction but also in the lateral direction is reduced, and the well layer It is possible to miniaturize the formation, and as a result, it is effective in miniaturizing the element. In this embodiment, the high-concentration buried layer is formed inside the well layer. However, due to the presence of fluorine, the buried layer expands by heat treatment (ie,
Since the diffusion of impurities in the buried layer can be reduced, the characteristics of the element formed on the surface of the well layer are not affected while keeping the well resistance low. This allows
It was possible to effectively prevent the element from being wrapped up by parasitic bipolar. Further, in the present embodiment, fluorine is trapped at the interface between the SiO ₂ film formed by thermal oxidation and the Si substrate, so that impurity diffusion at the interface is suppressed, and the redistribution of boron in the channel stopper layer 45 is small. became. This means that the decrease in the boron concentration under the field oxide film 42 is small, and as a result, the element isolation ability can be increased. In addition, since the source / drain junction can be made shallower and the diffusion of impurities under the gate electrode 47 can be suppressed, the difference (dimension) between the gate electrode length (gate length) and the effective gate length can be reduced. Shift) could be reduced. This makes it difficult for the short channel effect to occur even when the gate is miniaturized, and is effective in miniaturizing the device while maintaining the device characteristics. For example, the dimensional shift at the gate can be reduced by about 0.1 μm as compared with the normal (0.3 μm) in the n-type source / drain layer due to the presence of fluorine, and is usually reduced by (0.6 μm) in the p-type source / drain layer.
m) can be reduced to about 0.3 μm as compared with m). further,
By having fluorine at the interface between the SiO ₂ film and the Si substrate,
The leak current at the interface can be reduced, and the defect region after the crystal growth of the amorphous Si film trapped with fluorine formed on the back surface has a gettering effect. , Leakage current due to recombination, and leakage current due to diffusion of minority carriers in the substrate could be reduced. Each of the above leakage currents is
It could be reduced to about 50-70%. The film deposited on the back surface of the substrate before the treatment in the above-mentioned fluorine plasma obtained the same result as a polycrystalline Si film instead of the amorphous Si film.

〔The invention's effect〕

As described above, the method of forming an impurity diffusion layer according to the present invention is a method of forming an impurity diffusion layer by diffusing an impurity into a semiconductor substrate. By diffusing an impurity in a state where fluorine is present in at least one or more places, the impurity diffusion can be suppressed, a shallow impurity diffusion layer can be formed, and the effect of miniaturizing a semiconductor element can be obtained. . In addition, since impurity diffusion can be controlled, each element having various characteristics can be easily manufactured without changing a method of manufacturing a semiconductor element.
Furthermore, since the performance of the element can be improved without deteriorating the element characteristics, a highly reliable semiconductor element can be manufactured.

[Brief description of the drawings]

FIGS. 1A and 1B are explanatory views of a first embodiment in which the present invention is applied to the formation of a boron diffusion layer. FIGS. 1A and 1B each show a manufacturing process, and FIG. FIG. 2 is a view showing a concentration distribution, FIG. 2 is an explanatory view of a second embodiment in which the present invention is applied to the formation of a phosphorus diffusion layer, (a) and (b) each show a manufacturing process, and (c) is a diffusion chart. FIG. 3 is a diagram showing a phosphorus concentration distribution in a layer, FIG. 3 is an explanatory view of a third embodiment in which a well layer is formed, (a) to (d) are manufacturing process diagrams, and (e) is an impurity concentration distribution. FIGS. 4A and 4B are explanatory views of a fourth embodiment in which a well layer is formed. FIGS.
(E) is a diagram showing an impurity concentration distribution, and FIGS.
(D) is a diagram showing each manufacturing process of the fifth embodiment implemented for manufacturing a bipolar transistor, and FIGS. 6 (a) to (c) are manufacturing processes of the sixth embodiment implemented for manufacturing a complementary MOS transistor. FIG. 1, 7, 27, 38 ... semiconductor substrate 3, 9 ... fluorine existing area 14, 21, 32, 33, 34 ... defect area

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Joe Yoji 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Nobuyoshi Natsuaki 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory (72) Inventor Masanobu Miyao 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory Co., Ltd. (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/22 H01L 21/265

Claims (3)

(57) [Claims] When forming an impurity diffusion layer by introducing and diffusing an impurity from the surface of a silicon substrate, a crystal defect is formed in the entire silicon substrate or in a region deep from the main surface of the silicon substrate to form an impurity. Contains 1 × 10 ¹⁸ / cm ³ or more of fluorine. 2. When forming an impurity diffusion layer on a main surface of a silicon substrate, a crystal defect is formed in the silicon substrate other than a region where the impurity diffusion layer is formed, and a concentration of 1 × 10
^{18. A} method for manufacturing a semiconductor device, comprising ¹⁸ / cm ³ or more of fluorine. 3. When forming an impurity diffusion layer on a main surface of a silicon substrate, a crystal defect is formed at two or more of the main surface, a region deep from the main surface, and the back surface of the silicon substrate to reduce the concentration. A method for manufacturing a semiconductor device, comprising 1 × 10 ¹⁸ / cm ³ or more of fluorine.