JPH01112772A - Mis-type semiconductor device - Google Patents

Abstract

PURPOSE:To avoid increasing of element area and to realize high density and high integration by introducing germanium atoms at least into a region near a drain junction in a channel formation region. CONSTITUTION:A germanium introduction region 13 wherein germanium is introduced at a high density is formed over the entire surface of an element region 12 which is defined by a field oxide film 3 and a p-type channel stopper 2, and includes a channel formation region 11, a n<+>-type drain region 9 and an n<+> type source region 10. A germanium introduction region of high density is formed thereby at least in a region including a region near a germanium junction of a channel region, and the carrier mobility in the region is reduced thus realizing reduction of element area through short channeling.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the structure of an MIS type semiconductor device that is made into a short channel, the purpose of this invention is to provide a structure that can prevent the generation of hot carriers without increasing the device area. This is a MIS type semiconductor device formed on a substrate, and has a structure in which germanium atoms are introduced into at least a region near a drain junction in a channel formation region.

[Industrial application field]

The present invention relates to an improvement in the structure of an MIS type semiconductor device, and particularly to a MIS type semiconductor device that is made into a short channel.

In order to avoid the reduction in operating speed that occurs with the increase in the scale of semiconductor ICs such as LSIs, MISFETs built into LSIs and the like have recently been rapidly short-channeled.

When the MISFET is made into a short channel in this way, a problem arises in that the reliability decreases due to the generation of hot carriers.

The amount of energy possessed by hot carriers is Lack
According to the y Electron model, it is expressed by the following equation (1).

E=c4tl (1) E: Carrier energy q: Elementary charge ε: Electric field strength 1: Mean free path of carriers Even when a MISFET is made into a short channel, it has a normal channel length between the drain and source. Conventional M
As with the ISFET, a voltage v0 of about 5V is applied.

Therefore, in a short channel MISFET, the electric field strength ε near the drain junction in equation (1) above is
becomes significantly stronger, producing hot carriers whose carrier energy E increases according to Equation 11.

Then, the accelerated hot carriers with high energy penetrate into the gate insulating film and accumulate in the MISFET.
The dark value voltage V is changed over time to reduce the intensity of the electric field formed and suppress the generation of hot carriers.
(Lightry Doped Drain) structure and D” (Double Diffused Drain)
structure is proposed.

Figures 8 and 9 show MOSs of LDD structure and D3 structure.
FIG. 2 is a side sectional view schematically showing an FET.

In these figures, 1 is a p-type silicon substrate, 2 is a p-type silicon substrate, and 2 is a p-type silicon substrate.
3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is an insulating film sidewall, 7 and 107 are n-type (low concentration) drain regions, 8 and 108 are n-type ( 9 is an n-type (low concentration) source region;
10 is an n0 type (highly doped) source region, and 11 is a channel forming region.

[Problem that the invention seeks to solve]

However, in both the LDD structure and the D″ structure, a lightly doped drain region ?
07 and low concentration source regions 8, 108, etc., the element area is expanded, and the short channel MISFE
There is a problem in that the degree of integration of ICs using T is reduced.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an MIS type semiconductor device that can prevent the generation of hot carriers without increasing the device area.

c) Means for solving the problem] The above problem is caused by the MIS formed on a silicon semiconductor substrate.
This problem is solved by the MIS type semiconductor device according to the present invention, in which germanium atoms are introduced into at least the region near the drain junction in the channel forming region.

[For production]

When the electric field is kept constant, the following relationship (2) holds between carrier mobility μ and mean free path l.

μw K 11'' (2) K: proportionality constant On the other hand, the mean free path l of the carrier and the energy E of the carrier are in a directly proportional relationship as shown in the above equation (11).

Therefore, in the present invention, germanium atoms, which form mixed crystals with silicon in any ratio and have the effect of reducing carrier mobility μ, are added to the channel region at a concentration that effectively reduces carrier mobility. is introduced to shorten the carrier mean free path l, thereby reducing the carrier energy E based on equation (11) and preventing the generation of hot carriers.

Thus, according to the present invention, there is no need to provide a low concentration drain region or source region to prevent the generation of hot carriers, thereby avoiding an increase in the device area and achieving high density and high integration of short channel Mis semiconductor devices. .

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

1, 2, 3, and 4 are the first and second embodiments of the present invention.
, a schematic side sectional view showing the main parts of the third and fourth embodiments, and the fifth embodiment.
6 are schematic side sectional views of main parts of different application examples of the present invention, and FIG. 7 is a diagram showing the mobility of carriers in a silicon (Si)-germanium (Ge) mixed crystal.

Identical objects are indicated by the same reference numerals throughout the figures.

In FIG. 1 showing the first embodiment of the present invention, 1 is p-
type silicon substrate, 2 is a p-type channel stopper, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 9
10 is an n-type (high concentration) drain region, 10 is an n1-type (high concentration) source region, 11 is a channel formation region, 12 is an element formation region, and 13 is a germanium-introduced region.

In the first embodiment shown in the figure, a device region 12 including a channel forming region 11, an n-type drain region 9, and an n3-type source region 10 is defined by a field oxide film 3 and a p-type channel stopper 2. Germanium (Ge) is introduced into the entire surface at a predetermined high concentration to a depth of, for example, 10
A germanium introduction region 13 of about 0.00 is formed.

The carrier mobility, that is, the electron mobility μ, in the 5i-Ge mixed crystal shown in FIG.
), and the change (b) in the hole mobility μm depending on the component ratio.
It is about %. Therefore, the Ge concentration in the Ge single region 13 is controlled to be approximately 5 x 10" to I x 10" cm3.

In forming the structure shown in FIG. 1, before forming the gate electrode 5, a Ge introduced region 13 is formed on the entire surface of the element forming region 12 by vapor phase diffusion or ion implantation, and the source and drain regions 9. 10, after forming the gate electrode 5,
For example, 30 mm is aligned with the gate electrode 5 by ion implantation.
Formed at a depth of about 0.00 people.

In the second embodiment shown in FIG.
This is a modification of the first embodiment in which the depth is approximately zero. Note that the method for forming this structure and the Ge concentration in the germanium introduced region 113 are the same as in the first embodiment.

The above is an example in which the germanium introduced region is formed throughout the channel forming region 11.

In the third embodiment shown in FIG. 3, a germanium-introduced region 1 penetrates into the end of the channel forming region 11 from the surface of the source and drain regions 9 and 10 to a depth of about 1000.
This is an example in which 3A and 13B are formed.

Since hot carriers are generated near the drain junction where the electric field is strong, the generation of hot carriers can be suppressed by reducing the mobility of carriers in the vicinity of the drain region 10 in the channel forming region 11. Further, in the structure of this embodiment, since a low mobility region is not formed in the entire channel forming region 11, it is more advantageous than the previous embodiment in terms of improving the operating speed.

Note that when forming this structure, after forming the gate electrode 5, the element formation region 1 is formed using the gate electrode 5 as a mask.
Germanium is ion-implanted into the gate electrode 5 in a shallow manner, and the germanium is stretched and diffused by heat treatment so that the germanium-introduced regions 13A and 13B penetrate deeper into the end of the channel forming region 11 than the source and drain regions. Using as a mask, impurity ions are implanted to form a source region 9 and a drain region 10. The germanium introduction regions 13A and 13B completed here are as follows:
As in the above example, Ge9 degree is 5 X1021~I XI
The source and drain regions 9 and 10 are formed to a depth of about 3,000 cm and a depth of about 3,000 cm.
Be with people.

The fourth embodiment shown in FIG. 4 is a modification of the third embodiment in which germanium introduced regions L13A and 113B are formed that do not communicate in the channel forming region 11 and are deeper than the source and drain regions 9 and 10. It is. The Ge:a degree of the germanium-introduced region is the same as in the above embodiment, and the depth is, for example, about 4000 deep, which is about 1000 deep from the source and drain regions 9.10.

The advantages of this structure for speeding up are the same as in the third embodiment.

Note that the germanium introduced regions 113A and 113B are formed by deeply ion-implanting Ge using the gate electrode 5 as a mask.

Although not shown, a structure in which a large germanium conductive region is selectively formed only in the vicinity of the drain region in the channel region also produces effects and advantages similar to those of the third and fourth embodiments.

In the structure of the present invention as shown in the embodiments above, a high-concentration germanium-introduced region is formed in the region of the channel region including at least the region near the drain junction, and the carrier mobility in this region is reduced. Even when a short channel is formed and a high electric field is formed near the drain junction, the carrier energy E is suppressed from increasing to a level that generates hot carriers.

In an energization acceleration test that is normally performed as a reliability test, fluctuations in the dark value voltage V were suppressed within an allowable range, and a reliability life equivalent to that of the LDD structure and the D3 structure was obtained.

Therefore, in order to prevent the generation of hot carriers, the LD
Unlike the D structure and the D3 structure, there is no need to interpose a lightly doped drain region between the highly doped drain region and the channel forming region to reduce the electric field strength near the drain junction, and the device area can be reduced.

FIG. 5 shows an application example of the present invention in which the configuration of the first embodiment is added to the LDD structure to further enhance the effect of preventing hot carriers.

In the figure, 1 is a p-type silicon substrate, 2 is a p-type channel stopper, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is an insulating film sidewall, and 7 is an n-type silicon substrate.
8 is an n-type (low concentration) source region, 9 is an n-type drain region 10 is an n-type source region, 11 is a channel forming region, and 13 is a germanium quadruple region.

FIG. 6 shows another application example of the present invention in which the configuration of the fourth embodiment is added to the D3 structure to further enhance the hot carrier prevention effect.

In the figure, 107 is an n-type (low concentration) drain region, 10B
indicates an n-type (low concentration) source region, and other symbols indicate the same objects as in FIG.

Note that the present invention provides an M
Of course, the present invention is also applied to IS semiconductor devices.

〔Effect of the invention〕

As explained above, according to the present invention, the mean free path of carriers in the channel region is shortened to reduce the charge of the carriers, thereby preventing the generation of hot carriers, so that the electric field near the drain junction of the channel region There is no need to provide low impurity concentration source/drain regions to reduce the strength, and the device area can be reduced.

Therefore, the present invention is effective for increasing the degree of integration of short channel MISICs.

[Brief explanation of the drawing]

1, 2, 3, and 4 are the first and second embodiments of the present invention.
, FIGS. 5 and 6 are schematic side sectional views of the main parts of different application examples of the present invention, and FIG. 7 is a schematic side view showing the main parts of the third and fourth embodiments. Diagrams showing carrier mobility in mixed crystals, Figures 8 and 9 are MO3F with LDD structure and D3 structure.
ET is a schematic side sectional view. In the figure, 1 is a p-type silicon substrate, 2 is a p-type channel stopper, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is an insulating film sidewall, and 7.107 is an n-type ( low concentration) drain region, 8.10
8 is an n-type (low concentration) source region, 9 is an n'' type (high concentration) drain region, 10 is an n'' type (high concentration) source region, 11 is a channel formation region, 12 is an element formation region, 13. 13A, 13B, 113.113A,
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Claims (1)

[Scope of Claim] An MIS type semiconductor device formed on a silicon semiconductor substrate, characterized in that germanium atoms are introduced into at least a region near a drain junction in a channel forming region.