JPH0366165A - Diffusion of impurities to semiconductor substrate - Google Patents
Diffusion of impurities to semiconductor substrateInfo
- Publication number
- JPH0366165A JPH0366165A JP20334989A JP20334989A JPH0366165A JP H0366165 A JPH0366165 A JP H0366165A JP 20334989 A JP20334989 A JP 20334989A JP 20334989 A JP20334989 A JP 20334989A JP H0366165 A JPH0366165 A JP H0366165A
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- region
- diffusion
- ion implantation
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 title claims abstract description 42
- 238000009792 diffusion process Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen or nitrogen Chemical compound 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、短チヤネル効果が期著になる領域の微細ルー
ルで加工される半導体素子、例えば高耐圧MO3I−ラ
ンジスタ、メモリセルに用いられる不純物拡散方法に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to impurities used in semiconductor devices, such as high-voltage MO3I transistors and memory cells, which are processed according to fine rules in a region where the short channel effect is significant. Concerning diffusion methods.
本発明は、より低温熱処理で深さ方向より水平方向の異
方性をもつ不純物熱拡散を行うために、イオンインプラ
法により形成された不純物領域の底部にその不純物の熱
拡散定数の小さな物質を高エネルギーイオンインプラ法
で深く打ち込むことで不純物拡散ストソバ領域を形成し
た。In order to perform impurity thermal diffusion with anisotropy in the horizontal direction rather than in the depth direction with lower temperature heat treatment, a substance with a small thermal diffusion constant of the impurity is added to the bottom of the impurity region formed by the ion implantation method. An impurity-diffused stosobar region was formed by deeply implanting the impurity using high-energy ion implantation.
第2図は従来の方法を用いて作製された、2重拡散領域
をソース、ドレイン領域としなもつ2重拡散ドレイン(
D D D (DOUBLE DIFFIISED D
RAIN))型MOS)ランジスタの断面構造図である
。このトランジスタでは半導体基板1の表面部分にゲー
ト絶縁膜2が形成されている。その上にポリシリコン電
極3を化学気相成長(CVD)法により堆積する。さら
にこのポリシリコン電極に、リンをセルファライン的に
イオンインプラ法で半導体基振巾に打ち込む。次にこの
リンインプラ領域のアニールと拡散のために1000℃
窒素雰囲気中でアニールを行い、n−領域5を形成する
。そして、砒素をインプラし、n+を6を形成した。Figure 2 shows a double-diffused drain fabricated using a conventional method, with double-diffused regions serving as source and drain regions.
D D D
FIG. 2 is a cross-sectional structural diagram of a RAIN) type MOS) transistor. In this transistor, a gate insulating film 2 is formed on a surface portion of a semiconductor substrate 1. A polysilicon electrode 3 is deposited thereon by chemical vapor deposition (CVD). Furthermore, phosphorus is implanted into the semiconductor substrate width into this polysilicon electrode using an ion implantation method in a self-aligned manner. Next, the temperature was set at 1000°C for annealing and diffusion of this phosphorus implantation region.
Annealing is performed in a nitrogen atmosphere to form n- region 5. Then, arsenic was implanted to form n+6.
上記で述べたように、DDD型MO3)ランジスタでは
、ドレイン耐圧向上のために、n−領域の拡散長Xjを
長くしてなだらかな不純物プロファイルにしてドレイン
領域の電界緩和をする必要がある。このn−領域の熱拡
散では、通常1000℃窒素ガス雰囲気中で20〜30
分のアニールが行われるが、1000℃の高温熱処理は
ソース、ドレイン領域の熱拡散が大きいためパンチスル
ー等の短チヤネル効果を引き起こし、微細なトランジス
タを作製するのが非常に困難になる。As described above, in the DDD type MO3) transistor, in order to improve the drain breakdown voltage, it is necessary to lengthen the diffusion length Xj of the n- region to create a gentle impurity profile to relax the electric field in the drain region. In this n-region thermal diffusion, normally 20 to 30
However, high-temperature heat treatment at 1000° C. causes large thermal diffusion in the source and drain regions, causing short channel effects such as punch-through, making it extremely difficult to fabricate fine transistors.
以上の述べた課題を解決するために、本発明では、より
低温熱処理温度で深さ方向より水平方向の異方性をもつ
不純物熱拡散を行うために、イオンインプラ法により形
成された不純物領域の底部にその不純物の熱拡散定数の
小さな物質を高エネルギーイオンインプラ法で深く打ち
込むことで、不純物拡散ストッパ領域を形成した。In order to solve the above-mentioned problems, in the present invention, in order to perform impurity thermal diffusion with anisotropy in the horizontal direction rather than in the depth direction at a lower heat treatment temperature, an impurity region formed by an ion implantation method is An impurity diffusion stopper region was formed by deeply implanting a material with a small impurity thermal diffusion constant into the bottom using high-energy ion implantation.
上記のごとく、イオンインプラ法により形成された不純
物領域の底部にその不純物の熱拡散定数の小さな物質を
高エネルギーイオンインプラ法で深く打や込むことで、
不純物拡散ストソバ領域を形成することにより、深さ方
向より水平方向の熱拡散の早い異方性不純物熱拡散が行
えるので、より低温熱処理温度で、短時間に、不純物熱
拡散を行えるようになった。従って、微細加工に伴う短
チヤネル効果を抑制することが可能になった。As mentioned above, by deeply implanting a material with a small thermal diffusion constant of the impurity into the bottom of the impurity region formed by the ion implantation method, using the high energy ion implantation method,
By forming an impurity diffusion layer region, it is possible to perform anisotropic impurity thermal diffusion in which thermal diffusion is faster in the horizontal direction than in the depth direction, making it possible to perform impurity thermal diffusion in a shorter time at a lower heat treatment temperature. . Therefore, it has become possible to suppress the short channel effect caused by microfabrication.
以下に、本発明の実施例を図面に基づいて詳細に説明す
る。第1図は本発明の不純物拡散方法を用いて作製され
たDDD型MO3)ランジスクの断面構造図である。こ
のトランジスタでは半導体基板1の表面部分にゲート絶
縁膜2が形成されている。その上にポリシリコン電極3
をCVD法により堆積する。次にこのポリシリコン電極
にリンをセルファライン的にイオンインプラ法で半導体
基板中に打ち込む(後にn −%l域5になる)。ここ
で高エネルギーイオンインプラ法でリンの熱拡散定数の
小さな、例えば酸素もしくは窒素等のイオン種を半導体
基板の深い部分に打ち込み、不純物拡散ストソバ領域4
を形成する。さらにリンインプラ領域のアニールと拡散
のために窒素雰囲気中でアニールを行い、n−61域5
を形成する。Embodiments of the present invention will be described in detail below based on the drawings. FIG. 1 is a cross-sectional structural diagram of a DDD type MO3) disk manufactured using the impurity diffusion method of the present invention. In this transistor, a gate insulating film 2 is formed on a surface portion of a semiconductor substrate 1. On top of that, polysilicon electrode 3
is deposited by CVD method. Next, phosphorus is implanted into the semiconductor substrate into this polysilicon electrode by an ion implantation method in a self-aligned manner (later, it becomes an n-%l region 5). Here, ion species with a small thermal diffusion constant of phosphorus, such as oxygen or nitrogen, are implanted into the deep part of the semiconductor substrate using a high-energy ion implantation method.
form. Furthermore, annealing was performed in a nitrogen atmosphere for annealing and diffusion of the phosphorus implant region.
form.
しかし、先に形成した不純物拡散ストッパ領域のため、
深さ方向より水平方向の異方性をもつ不純物熱拡散が行
えるので、より低温熱処理温度で、短時間に、不純物熱
拡散を行えるようになった。However, due to the previously formed impurity diffusion stopper region,
Since impurity thermal diffusion can be performed with more anisotropy in the horizontal direction than in the depth direction, impurity thermal diffusion can now be performed at lower heat treatment temperatures and in a shorter time.
従って、微細加工に伴う短チヤネル効果を抑制すること
が可能になる。そして、砒素をインプラし、n″領域6
を形成した。Therefore, it becomes possible to suppress the short channel effect caused by microfabrication. Then, arsenic is implanted into the n″ region 6.
was formed.
本発明の半導体基板への不純物の拡散方法は、以上説明
したようにイオンインプラ法により形成された不純物領
域の底部にその不純物の熱拡散定数の小さな物質を高エ
ネルギーイオンインプラ法で深く打ち込むことで、不純
物拡散ストソバ領域を形成することにより、深さ方向よ
り水平方向の熱拡散の早い異方性不純物拡散が行えるの
で、より低温の熱処理温度で、短時間に不純物熱拡散を
行えるようになった。従って、微細加工に伴う短チヤネ
ル効果を抑制することが可能になった。As explained above, the method for diffusing impurities into a semiconductor substrate of the present invention is to deeply implant a substance with a small thermal diffusion constant of the impurity into the bottom of the impurity region formed by the ion implantation method using a high energy ion implantation method. By forming an impurity-diffusion stratobar region, it is possible to perform anisotropic impurity diffusion in which thermal diffusion is faster in the horizontal direction than in the depth direction, making it possible to perform impurity thermal diffusion in a shorter time at a lower heat treatment temperature. . Therefore, it has become possible to suppress the short channel effect caused by microfabrication.
第1図は本発明の半導体基板への不純物拡散方法を用い
て作製されたDDD型MO3)ランジスタの断面構造図
、第2図は従来の半導体基板への不純物拡散方法を用い
て作製されたDDD型MOSトランジスタの断面構造図
である。
半導体基板
ゲート絶縁膜
ポリシリコン電極
不純物拡散ストソバ領域
n−領域
6
・n°領領
域
上Figure 1 is a cross-sectional structural diagram of a DDD type MO3) transistor manufactured using the method of diffusing impurities into a semiconductor substrate according to the present invention, and Figure 2 is a cross-sectional diagram of a DDD type transistor manufactured using the conventional method of diffusing impurities into a semiconductor substrate. FIG. 2 is a cross-sectional structural diagram of a type MOS transistor. Semiconductor substrate gate insulating film polysilicon electrode impurity diffusion layer region n- region 6 ・On n° region
Claims (1)
て打ち込み、熱拡散することで拡散領域を形成する半導
体素子において、前記不純物がイオンインプラ法により
打ち込まれた不純物領域の底部に、前記不純物の熱拡散
定数の小さい物質を高エネルギーイオンインプラ法によ
り深く打ち込むことで不純物拡散ストッパ領域を形成し
、その後の不純物熱拡散を行うとき、深さ方向よりも水
平方向の熱拡散を大きくさせた異方性不純物熱拡散の効
果により、低温処理を可能にした不純物拡散方法。In a semiconductor element in which a diffusion region is formed by implanting an impurity near the surface of a semiconductor substrate using an ion implantation method and thermally diffusing the impurity, the impurity is thermally diffused into the bottom of the impurity region into which the impurity is implanted by the ion implantation method. An impurity diffusion stopper region is formed by deeply implanting a material with a small constant using high-energy ion implantation, and when subsequent impurity thermal diffusion is performed, an anisotropic impurity that causes greater thermal diffusion in the horizontal direction than in the depth direction. An impurity diffusion method that enables low-temperature processing due to the effect of thermal diffusion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20334989A JPH0366165A (en) | 1989-08-04 | 1989-08-04 | Diffusion of impurities to semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20334989A JPH0366165A (en) | 1989-08-04 | 1989-08-04 | Diffusion of impurities to semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0366165A true JPH0366165A (en) | 1991-03-20 |
Family
ID=16472560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20334989A Pending JPH0366165A (en) | 1989-08-04 | 1989-08-04 | Diffusion of impurities to semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0366165A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05129607A (en) * | 1991-10-31 | 1993-05-25 | Sharp Corp | Manufacture of semiconductor device |
US5514902A (en) * | 1993-09-16 | 1996-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having MOS transistor |
US5943589A (en) * | 1997-01-30 | 1999-08-24 | Nec Corporation | Method of fabricating semiconductor device with a trench isolation |
US6153910A (en) * | 1994-06-22 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with nitrogen implanted channel region |
US6225663B1 (en) | 1996-06-14 | 2001-05-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having SOI structure and method of fabricating the same |
JP2005340851A (en) * | 2005-06-27 | 2005-12-08 | Sharp Corp | Semiconductor device and its manufacturing method |
JP2008140817A (en) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | Semiconductor device |
-
1989
- 1989-08-04 JP JP20334989A patent/JPH0366165A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05129607A (en) * | 1991-10-31 | 1993-05-25 | Sharp Corp | Manufacture of semiconductor device |
US5514902A (en) * | 1993-09-16 | 1996-05-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having MOS transistor |
US6475887B1 (en) | 1993-09-16 | 2002-11-05 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
US6153910A (en) * | 1994-06-22 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with nitrogen implanted channel region |
US6380036B1 (en) | 1994-06-22 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US6225663B1 (en) | 1996-06-14 | 2001-05-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having SOI structure and method of fabricating the same |
US6509211B2 (en) | 1996-06-14 | 2003-01-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having SOI structure and method of fabricating the same |
US5943589A (en) * | 1997-01-30 | 1999-08-24 | Nec Corporation | Method of fabricating semiconductor device with a trench isolation |
JP2005340851A (en) * | 2005-06-27 | 2005-12-08 | Sharp Corp | Semiconductor device and its manufacturing method |
JP2008140817A (en) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | Semiconductor device |
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