JPH0272634A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shallow an impurity layer by forming an insulating film which has fixed charge on a semiconductor substrate adjacent to a gate electrode, and changing the right below carrier concentration by the fixed carrier. CONSTITUTION:An Al-implanted insulating film 3 adjacent to a gate insulating film 2 is formed, and Al ions 4 act as negative fixed charged particles in this insulating film. By this fixed charge an inversion layer 6 is induced in an Si substrate 5, and appropriate electrodes are provided in this inversion layer 6, and those are used as a source and a drain. At that time, for example, wiring itself connected to the source and drain is arranged such that an insulating film 3 having fixed charge is formed on a substrate 5 and an induced inversion layer 6 is formed right below that. That is, the type and concentration of carriers in the substrate 5 are changed. Hereby, only by applying a simple process a shallow junction can be formed.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a novel semiconductor device structure in which the impurity layer can be made shallow with respect to a semiconductor device that requires the formation of a shallow impurity layer. In a semiconductor device including a gate electrode on a semiconductor substrate and semiconductor regions constituting a source and a drain, an insulating film having a fixed charge is formed on the semiconductor substrate adjacent to the gate electrode, and the carrier concentration directly below is changed. Configure it so that

[Industrial application field]

The present invention relates to a semiconductor device in which it is necessary to form a shallow impurity region, and particularly to a semiconductor device in which the formation of a source/drain or the carrier concentration near the surface thereof is changed.

With the recent increase in the degree of integration of LSIs, it has become an essential issue to make the source/drain of a transistor shallower. However, the large diffusion of impurities in St inhibits shallowing. There is a need for an alternative technique to simply diffusing impurities into 3i.

[Conventional technology]

FIG. 4 shows a cross-sectional view of a conventional MO3 type transistor.

In the figure, 1 is a gate electrode, 2 is a gate insulating film, 5 is a Si substrate of one conductivity type, and 7 is an impurity region layer of the opposite conductivity type, which constitutes a source and a drain. It is necessary to form the impurity region layer 7 constituting the source/drain sufficiently shallowly in order to prevent the short channel effect. Conventionally, the following method has been considered as a method for making the impurity region layer 7 shallow.

■Low-acceleration ion implantation ■Method using ECR (electron cyclotron resonance) etc. ■In-phase diffusion: Impurities are introduced into the Si substrate from an impurity-containing insulating film through heat treatment.

(2) Use of impurities with small diffusion coefficients: For example, in the case of a P channel, Ga is used instead of B. For N channel As
Use sb instead of or P.

Of these, methods ① and ③ are severely restricted by the equipment, and there are many issues to be solved in putting them into practical use. In ion implantation (2), even at low acceleration, there is a limit to the formation of shallow junctions due to phenomena such as channeling. Furthermore, heat treatment is required to activate the implanted ions, and the spread of the impurity layer due to thermal diffusion cannot be avoided. ■ ECR
Although uniformity can be expected, it is not a technology that can be immediately applied in terms of process because the equipment has not yet been established.

Furthermore, thermal expansion of the impurity layer cannot be avoided.

■■ has the problem of unstable process and lack of controllability. (2) has poor uniformity and is difficult to control the profile. (2) Ga and sb have poor process consistency. With Ga, etc., it is difficult to achieve shallowness and a required high concentration.

[Problem to be solved by the invention]

An object of the present invention is to solve the problem that it is difficult to form a shallow impurity layer in any of the conventional methods described above, and to provide a novel semiconductor device structure that can make the impurity layer shallow. .

[Means to solve the problem]

The inventors have come to the conclusion that there is a limit to the formation of shallow impurity regions using the method of directly introducing impurities into a substrate. Therefore, among various considerations, we focused on the phenomenon that the carrier concentration on the substrate surface can be controlled by charges fixed in the insulating film. The present invention was developed based on the idea of the semiconductor device to be used.

In other words, the present invention uses a fixed charge in an insulating film to change the type and concentration of carriers in the substrate, instead of using a conventional diffusion layer as a shallow impurity layer essential for preventing short channel effects. This is the main focus.

The present invention will be explained in principle using the example shown in FIGS. 1A to 1C. 1 is a gate electrode, 2 is a gate insulating film made of S i O2, and 3 is Aj! Injected insulating film, 4 is Al ion, 5 is S
The i-substrate (N type) 6 is an induced inversion layer. Here, the Al ions introduced into the Sin have a negative fixed charge, and the charge does not easily move even at a considerably high temperature (about 1100° C.).

[Effect]

As mentioned above, the fixed charge of the insulating film into which Al is implanted in step 3 does not move easily even when heat treatment is applied, so the inversion layer 6 induced on the substrate surface remains stable even after subsequent heat treatment. A sagging, shallow semiconductor region can be formed. As a result, it becomes possible to prevent short channel effects.

〔Example〕

A first embodiment of the present invention will be described with reference to FIGS. 1A to 1C. This is a P-channel type MOS (MOS) transistor in which the source/drain is formed using an inversion layer created on the substrate by fixed charges in the insulating film, and Al in SiO2 is used as the fixed charge. It's a method.

In FIG. 1A, 100 to 1
After forming the gate insulating film 2 made of 50 SiOz,
Approximately 4,000 pieces of polysilicon 8, which will become the gate electrode, are grown.

In FIG. 1B, a gate electrode 1 is formed by patterning polysilicon by a photolithography process.

The above steps are similar to the normal MOS manufacturing process.

Next, in FIG. 1C, Al ions are implanted. The conditions need to be low acceleration so that the Al ions do not reach the substrate, for example, I x 10"cm-" 4
0 kev to 30 kev.

As another method of introducing this Al into the insulating film, Al2
After soaking in an aqueous solution containing 11,000 pp or more of
The above heat treatment may be applied, and according to this method, it is easy to keep Al only in the insulating film.

For example, polyaluminum chloride may be used as the A2 compound, immersed in an aqueous solution of 11,000 PP or more for about 15 to 20 seconds, and then heat treated at 600° C. or more for about 30 minutes.

Through the above steps, an Al-implanted insulating film 3 is formed adjacent to the gate insulating film 2 as shown in FIG. 1C.

In this insulating film, Al ions 4 act as negative fixed charges, and this fixed charge induces an inversion layer 6 in the St substrate. This inversion layer 6 can be provided with suitable electrodes and used as a source and a drain. In this case, for example, the wiring itself connected to the source and drain can be formed by forming an insulating film having fixed charges on the substrate, and forming an induced inversion layer directly under the insulating film.

Figures 2A-G show a second embodiment of the invention.

This is a P-channel MO in which the LDD region is formed using an inversion layer created on the substrate by charges in the insulating film.
3) It is a transistor.

The steps up to FIG. 2A-C are the same as those in FIG. 1A-C, and as shown in FIG. 2C, the gate electrode 1 is placed on the Si substrate 5.
, a gate insulating film 2, an insulating film 3 into which A6 is implanted, and an inversion layer 6 induced by negative fixed charges caused by Aff ions 4 in the insulating film.

However, when implanting An ions into the insulating film 2, Al2
The dose of
0"cm-40kev to 30kev. Furthermore,
Preventing Al2 from being introduced into the Si substrate 5 is the same as in the previous embodiment.

Next, in the second plan, 2000 CvDSiO□
Grow 9.

Thereafter, as shown in FIG. 2E, the entire surface is etched (anisotropic etching), leaving the sidewall 10. At this time, only the AJ injection insulating film 3 directly under the sidewall 10 is left, and accordingly, the region of the induced inversion layer 6 is also limited.

In FIG.
An oxide film 11 without l ions is formed.

In FIG. 2G, a second ion implantation of A/ is performed.

The conditions are that the dose is larger than that of the first ion implantation (
and I X 1015am-240kev ~30k
Let it be ev.

By the above method, the low concentration portion 12 corresponding to the conventional L D De Jf region can also be formed without performing impurity diffusion. As a modification of this embodiment, the source and drain are formed by B ion implantation as usual without performing the second AA ion implantation, and only the low concentration portion 12 corresponding to the LDD region is formed directly under the sidewall. It may also be formed of a charge inversion layer.

A third embodiment of the present invention is shown in FIGS. 3A-3G.

This is a MO3I-transistor in which the charge in the insulating film destroys the carrier concentration in the inversion layer of the substrate to form an LDDel region. In this example, Si
The substrate 5' is of P type, and Aff ions in 5iOz act to form an accumulation layer. Others are shown in Figure 2 A-F above.
By a process similar to that shown in FIG. 3F, a gate electrode 1, a gate insulating film 2, an Al implanted insulating film 3, a sidewall insulating film 10, and a strong accumulation layer 6' made of An ion charges are formed on a Si substrate 5'. An insulating film 11 without Al is formed. After that, in FIG. 3G, As ion implantation was performed for 7
0 kev, 4 x 10 "cm-". Through subsequent heat treatment, the n゛diffusion layer 1 is formed just below the sidewall IO.
3 is formed. At that time, A right below the side wall! The part of the strong accumulation layer 6 due to ionic charges is the n-type region 14.
becomes.

As described above, according to the present invention, a region having the same function as a diffusion layer can be easily formed by the action of charges in the insulating film.

Since impurities are not implanted into Si, there is no need to worry about the spread of the diffusion layer.

Note that the present invention can be modified in various ways within the scope of the claims, and can generally be applied to the formation of shallow impurity regions such as source/drain regions other than directly under the gate. Further, it goes without saying that the present invention can generally use fixed charges formed in an insulating film.

〔Effect of the invention〕

As described above, according to the present invention, a shallow junction can be formed through simple steps. Therefore, this is an effective measure to avoid the short channel effect.

Moreover, since impurities are not implanted into the substrate, ion implantation damage is not induced. High-temperature heat treatment (activation annealing) is also unnecessary, making it possible to achieve a low-temperature process.

[Brief explanation of the drawing]

Figures 1A-C are cross-sectional views of the process of the first embodiment of the present invention, Figures 2A-G are cross-sectional views of the process of the second embodiment of the present invention, and Figures 3A-G are the cross-sectional views of the process of the second embodiment of the present invention. A cross-sectional view of the process of the third embodiment, and FIG. 4 is a cross-sectional view of a conventional semiconductor device. 1 is a gate electrode 2 is a gate insulating film 3 is an Al implanted insulating film 4 is an Aβ ion 5.5° is 81 substrate 6 is an inversion layer 6' is a strong accumulation layer due to Aff ion charge 7 is an impurity region layer of the opposite conductivity type 8 The polysilicon 9 is a CVD SiOz 10, the sidewall 11 is an insulating film 12 without Aβ ions, the low concentration portion 13 corresponds to the LDD region, the n+ diffusion layer 14 is an n- state region

Claims (1)

[Claims] 1. A semiconductor device comprising a gate electrode and semiconductor regions constituting a source and a drain on a semiconductor substrate of one conductivity type, which has a fixed charge on the semiconductor substrate adjacent to the gate electrode. A semiconductor device characterized in that an insulating film is formed, and the carrier concentration directly under the fixed charge is changed. 2. The semiconductor device according to claim 1, wherein an inversion layer is induced by the insulating film having fixed charges;
A semiconductor device characterized in that the source and drain are formed of the inversion layer. 3. The semiconductor device according to claim 1, wherein the insulating film having fixed charges is formed between the source and gate electrodes and between the drain and gate electrodes, and an inversion layer induced by the fixed charges in the insulating film. has a carrier concentration lower than that of the source and drain. 4. The semiconductor device according to claim 1, wherein the insulating film having a fixed charge is formed between the source and the gate electrode and between the drain and the gate electrode, and the fixed charge in the insulating film causes the source and the drain to By reducing the carrier concentration of the constituting semiconductor region,
A semiconductor device characterized by forming a region of low carrier concentration. 5. The semiconductor device according to claim 1, wherein the wiring connected to the source and drain is formed by an inversion layer induced in the semiconductor substrate by an insulating film having fixed charges.