JP3687776B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
In recent years, with higher integration and higher speed operation of semiconductor integrated circuits, MOSFETs (metal-oxide semiconductor field effect transistors) have been miniaturized, gate lengths have become shorter (for example, less than 500 nm), and gate oxide film thickness has increased. The thickness tends to be thin (for example, 10 nm or less). Further, the pn junction depth of the source / drain regions is made shallower (for example, 100 nm or less).
[0003]
In JP-A-61-90431, ions containing fluorine atoms are ion-implanted in a predetermined region (a region on both sides of a gate electrode and forming a source / drain) on a silicon substrate. It is described that an n-type dopant or a p-type dopant is ion-implanted to form a source / drain region, and then an activation treatment of the dopant is performed. According to this method, the silicon crystal is made amorphous by ion implantation of ions containing fluorine atoms, and dechanneling phenomenon (a phenomenon in which impurity atoms are scattered by interaction with the crystal lattice and enter the channel direction). ) Is prevented, a source / drain region having a shallow junction can be formed.
[0004]
In Japanese Patent Laid-Open No. 4-287332, after an amorphous layer is formed by ion implantation of silicon or the like into a predetermined region on the silicon substrate (on both sides of the gate electrode and forming the source / drain). Describes a method for reducing a crystal defect layer caused by the formation of the amorphous layer. That is, as a method for reducing the crystal defect layer, after ion implantation of an n-type dopant (P ⁺ , As ⁺ ) or a p-type dopant (BF ₂ ⁺ ), one of carbon, nitrogen, oxygen, or fluorine is added to the crystal defect layer. It is described that two or more kinds of impurities are ion-implanted and then heat treatment (for example, at 1000 ° C. for 15 seconds) is performed.
[0005]
Further, it is described that this crystal defect layer is generated on the silicon substrate side from the interface between the amorphous layer and the silicon substrate, and n-type or p-type dopant is implanted into the amorphous layer. That is, in this method, ion implantation of carbon or the like is performed on a region below the region where the dopant is ion-implanted.
[0006]
[Problems to be solved by the invention]
However, the MOSFET obtained by the above-described conventional technique particularly reduces the pn junction leakage at low voltage (leakage current due to a pn junction defect between the source / drain region and the silicon substrate) in the case of an n-channel MOSFET. There is room for improvement.
[0007]
The present invention has been made paying attention to such problems of the prior art, and in a MOSFET having a short gate length, a thin gate oxide film, and a shallow pn junction depth in the source / drain region, It is an object to reduce pn junction leakage at a low voltage.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a gate electrode forming step of forming a gate electrode on a single crystal silicon doped to a first conductivity type via a gate insulating film, and a gate electrode of the single crystal silicon. A first doping step of ion-implanting a dopant of the second conductivity type into the regions on both sides, a step of forming sidewall spacers on both sides of the gate electrode, and a region doped in the first doping step, which is a sidewall And a second doping step of further ion-implanting a second conductivity type impurity in a region outside the spacer, wherein the sidewall is after ion implantation of the dopant in the first doping step. Before the spacer formation process, fluorine ions are implanted in the same region where the dopant is ion-implanted. After, to provide a method of manufacturing a semiconductor device characterized by performing heat treatment to hold the seven hundred to seven hundred twenty ° C. under an inert gas atmosphere.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device corresponding to one embodiment of the present invention. Here, a C (complementary) MOSFET composed of an n-channel MOSFET (hereinafter abbreviated as “NMOS”) and a p-channel MOSFET (hereinafter abbreviated as “PMOS”) will be described as an example.
[0011]
First, as shown in FIG. 1A, an n-well 2 and a p-well 3 are formed on a p-type silicon substrate 1. Next, a gate electrode 5 is formed on each of the n well 2 and the p well 3 with a gate oxide film 4 interposed therebetween. The gate electrode 5 is a gate electrode 5 having a two-layer structure including a polysilicon layer 51 doped with an n-type dopant and a WSi layer 52. The thickness of the gate oxide film 4 is 8 nm (80 mm), the thickness of the polysilicon layer 51 is 2000 mm, the WSi layer 52 is 1500 mm, and the gate length is 0.5 μm.
[0012]
This gate electrode formation step is performed by a conventionally known method. Reference numeral 11 denotes a LOCOS (Local Oxidation Of Silicon) film provided for element isolation.
Next, as shown in FIG. 1B, BF ₂ ⁺ is ion-implanted as a p-type dopant into the region 6 on both sides of the gate electrode 5 of the n-well 2 and forming the source / drain. Next, P ⁺ or As ⁺ is ion-implanted as an n-type dopant into regions 7 on both sides of the gate electrode 5 of the p-well 3 where the source and drain are formed.
[0013]
These ion implantations correspond to the first doping step of the present invention. This first doping step is a step of adding an n-type dopant or a p-type dopant to the predetermined regions 6 and 7 of single crystal silicon at a concentration of LDD (Lightly Doped Drain) level. The ion implantation conditions for the region 6 on the n-well 2 side are, for example, an implantation energy of 40 keV and an implantation amount of 1 × 10 ¹⁴ ions / cm ² . The ion implantation conditions for the region 7 on the p-well 3 side are, for example, an implantation energy of 40 keV and an implantation amount of 5 × 10 ¹⁴ ions / cm ² . The depth of each region 6 and 7 is about 500 mm, for example.
[0014]
Next, F ⁺ ions are implanted into the region 7 on the p-well 3 side. This ion implantation is performed, for example, under conditions of an implantation energy of 15 keV and an implantation amount of 2 × 10 ¹⁴ ions / cm ² . Next, in this state, the wafer is placed in a normal heat diffusion furnace and held at 700 to 720 ° C. for 20 minutes in an atmosphere of 100% nitrogen gas.
Next, as shown in FIG. 1C, sidewall spacers 8 are formed on both side surfaces of the gate electrode 5. This side wall spacer forming step is performed by a conventionally known method. For example, after forming a TEOS (tetraethylorthosilicate) film with a film thickness of 2500 mm, the sidewall spacer 8 is formed by performing anisotropic dry etching. The width of the sidewall spacer 8 at the positions of the regions 6 and 7 is, for example, 0.2 μm.
[0015]
Next, BF ₂ ⁺ is further ion-implanted as a p-type dopant into the region 61 outside the sidewall spacer 8 in the region 6 on the n-well 2 side. Next, As ⁺ is ion-implanted as an n-type dopant into the region 71 outside the sidewall spacer 8 in the region 7 on the p-well 3 side.
These ion implantations correspond to the second doping step of the present invention. This second doping step is a step of further adding an n-type dopant or a p-type dopant in order to increase the dopant concentration of the regions 61 and 71 to the source / drain level. The ion implantation conditions for the region 61 on the n-well 2 side are, for example, an implantation energy of 35 keV and an implantation amount of 2.0 × 10 ¹⁵ ions / cm ² . The ion implantation conditions for the region 71 on the p-well 3 side are, for example, an implantation energy of 35 keV and an implantation amount of 2.0 × 10 ¹⁵ ions / cm ² . The depth of each region 61, 71 is about 300 mm, for example.
[0016]
As a result, as shown in FIG. 1D, a PMOS having a structure having an LDD region 62 inside the source / drain region 61 is formed in the n well 2, and the source / drain region 71 is formed in the p well 3. An NMOS having a structure having an LDD region 72 inside is formed.
Next, after forming a BPSG film (Boro-phospho silicate glass film: SiO ₂ film added with B ₂ O ₃ and P ₂ O ₅ ) on the surface of the wafer, the wafer is heated at 850 ° C. for 20 minutes in a nitrogen atmosphere. Heat treatment is performed. Then, CMOSFET is obtained by performing each process, such as metal wiring formation, by a conventionally well-known method.
[0017]
The above-described F ⁺ ion implantation process and the heat treatment process held at 700 to 720 ° C. for 20 minutes in an atmosphere of 100% nitrogen gas are not performed. %, A pn junction leak occurred at a low voltage (drain voltage of 0.1 V or less). On the other hand, the pn junction leakage at a low voltage did not occur in the NMOS of the CMOSFET obtained by the above method. That is, by the method of this embodiment, a CMOSFET in which pn junction leakage at a low voltage is reduced can be obtained.
[0018]
The reason will be described with reference to FIG.
The pn junction leakage is caused by silicon crystal defects. That is, when dangling bonds (bonds of unbonded bonds: Si-) generated by crystal dislocations and the like are arranged in a line, carrier conduction occurs along this line by the hopping mechanism. Leakage current is generated.
[0019]
For example, ion implantation of an n-type dopant into the p-well 3 generates a silicon dangling bond 31 at the pn junction position of the p-well 3. The dangling bond 31 reacts with and bonds to the fluorine atoms 9 by an F ⁺ ion implantation process and a heat treatment process held at 700 to 720 ° C. in an atmosphere of 100% nitrogen gas. As a result, crystal defects are repaired and pn junction leakage is reduced.
[0020]
When the heat treatment temperature in this heat treatment step is less than 700 ° C., the reaction between the dangling bonds 31 and the fluorine atoms 9 hardly occurs. When the heat treatment temperature exceeds 720 ° C., the ion-implanted F ⁺ is easily evaporated before being bonded to the dangling bond 31 and released to the outside.
On the PMOS side, BF ₂ ⁺ is ion-implanted as a p-type dopant into the n-well 2, so that fluorine atoms are introduced into the region 6 by this doping. Therefore, a crystal defect repairing action can be obtained without performing an F ⁺ ion implantation step and a heat treatment step later. It is presumed that this is the reason why pn junction leakage has been a problem on the NMOS side in the past and not particularly on the PMOS side.
[0021]
Therefore, in this embodiment, the F ⁺ ion implantation step and the heat treatment step after dopant ion implantation are performed only on the NMOS side. However, the present invention is not limited to this, and in the case of implanting ions not containing fluorine atoms as a p-type dopant in a PMOS, an F ⁺ ion implantation step is performed after the ion implantation of the dopant, and then the above-described process is performed. It is preferable to perform a heat treatment step.
[0022]
【The invention's effect】
As described above, according to the method of the present invention, even when the gate length is short, the thickness of the gate oxide film is thin, and the pn junction depth of the source / drain region is shallow, the pn junction at a low voltage of the MOSFET. Leakage can be reduced. As a result, a miniaturized MOSFET can be obtained with a high yield, and the reliability is improved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device corresponding to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the operation of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 n well 3 p well 4 gate oxide film 5 gate electrode 6 area | region (predetermined area | region of single crystal silicon) which forms source / drain
7 Region for forming source / drain (predetermined region of single crystal silicon)
8 Sidewall spacer 9 Fluorine atom 11 LOCOS film 31 Dangling bond 51 Polysilicon layer 52 WSi layer

Claims (1)

A gate electrode forming step of forming a gate electrode on the single-crystal silicon doped with the first conductivity type via a gate insulating film; and a second-conductivity-type dopant in regions on both sides of the gate electrode of the single-crystal silicon. A first doping step of ion implantation, a step of forming sidewall spacers on both side surfaces of the gate electrode, and a region doped in the first doping step and outside the sidewall spacer; And a second doping step of further ion-implanting the impurities of the semiconductor device,
After ion implantation of the dopant in the first doping step and before the sidewall spacer formation step, fluorine ions are implanted in the same region as the region where the dopant is ion-implanted, and then in an inert gas atmosphere. A method for manufacturing a semiconductor device, wherein heat treatment is performed at 700 to 720 ° C.

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