JP2570292B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for forming an impurity diffusion layer in silicon in the manufacture of a semiconductor, and is particularly effective in the manufacture of a CMOS LSI.

[Conventional technology]

When manufacturing a structure in which conventional Ti silicide is selectively lined with a silicon diffusion layer, after forming P and N high-concentration impurity layers on silicon, Ti is accumulated, and heat treatment is performed.
Ti silicide was formed. However, in the prior art,
The formation of Ti silicide depends on the impurity concentration in silicon, and the formation of Ti silicide is slower in the As implanted layer than in the B implanted layer. Even if it accumulates on polycrystalline silicon and heat-treats, Ti silicide is not formed on polycrystalline silicon. For this reason, it has been difficult to stably selectively form Ti silicide in the Pch region, the Nch region, and the polycrystalline silicon region by the conventional manufacturing method.

[Problems to be solved by the invention]

The present invention overcomes the disadvantages of the prior art, and provides stable and uniform T
i-silicide is selectively formed.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, there are provided (a) an element isolation insulating film for separating a P-channel transistor region and an N-channel transistor region on a silicon substrate, a gate insulating film of a P-channel transistor, and a gate electrode made of polycrystalline silicon. And forming a sidewall insulator of the gate electrode of the P-channel transistor, a gate insulating film of the N-channel transistor, a gate electrode made of polycrystalline silicon, and a sidewall insulator of the gate electrode of the N-channel transistor; (B) selectively ion-implanting boron or boron fluoride into the P-channel transistor region and forming an impurity layer of the P-channel transistor by heat treatment; (c) forming titanium on the silicon substrate; d) the P channel and the N channel The silicon substrate on which the gate electrode of the P-channel transistor, the sidewall insulator of the P-channel and the N-channel transistor and the element isolation insulating film are not formed, and the gate electrode of the P-channel and the N-channel transistor (D) removing unreacted titanium on the element isolation insulating film, the sidewall insulators of the P-channel and N-channel transistors, and (d) removing titanium silicide. (E) selectively ion-implanting arsenic or phosphorus into the N-channel transistor region; (f) forming an insulating film on the silicon substrate; (g) activating the arsenic or phosphorus by heat treatment; Forming an impurity layer of the N-channel transistor.

[Action]

According to the operation of the present invention, B or BF ₂ before Ti is accumulated.
Forming in the Pch region provides a gate electrode made of P-type silicon in which high-concentration boron is contained in Pch polycrystalline silicon. In addition, Ti silicide formation is processed in the Pch region of the high-concentration boron implanted layer and the Nch region in which the high-concentration impurities are not implanted. Thus, a uniform silicide layer can be formed. Phosphorus and arsenic diffuse very quickly in Ti silicide, and phosphorus or arsenic implanted in the Nch region propagates through the gate electrode silicide in the Pch region and mixes with the gate electrode polycrystalline silicon. For this reason, when B with little diffusion in Ti silicide is implanted into the Pch region after the formation of Ti silicide, the polycrystalline silicon of the gate electrode is changed to the N type not only in the Nch but also in the gate electrode in the Pch region. On the other hand, in the present invention, since high concentration B is implanted into the polycrystalline silicon in the Pch region before forming the Ti silicide, the gate electrode in the Pch region can be formed while maintaining the P-type. Furthermore, in the present invention, since phosphorus or arsenic is implanted so that a peak is formed at the interface between Ti silicide and silicon after Ti silicide formation, a shallow impurity layer activated in silicon by low-temperature heat treatment (for example, 1025 ° C., 20 seconds) Can be formed. Pc for low temperature heat treatment
The junction depth of h can also be kept shallow.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

1 to 4 are sectional views showing the steps of manufacturing the CMOSFET of the present invention. In FIG. 1, an element isolation insulating film 2 on a silicon substrate 1 is shown.
Pch and NchTr separated by are shown. In FIG. 1, the gate film 4, the side wall insulator 5, the gate electrode of the PchTr, the NchTr
After the gate electrode 3 is formed, boron 7 is selectively implanted into the entire Pch region using the resist as a mask. After activating the implanted boron by heat treatment (for example, 1000 ° C, 10 seconds),
FIG. 2 shows that Ti8 is formed on the entire surface of the substrate. Then P
The gate electrode 3-1 of the chTr forms P-type polycrystalline silicon containing high-concentration boron. Thereafter, a heat treatment (for example, 700 ° C., 30 seconds) is performed in an N ₂ atmosphere to selectively form Ti silicide 9 on the silicon substrate, and Ti or TiN on the element isolation insulating film and the side wall insulator is removed by RCA solution. . In FIG. 3, after selectively forming Ti silicide, phosphorus 11 is selectively implanted into the Nch region using the resist 10 as a mask.
In FIG. 4, after forming PSG12 on the entire surface, heat treatment (for example, 1025
(C, 20 seconds) Phosphorus is activated to form a shallow N-type junction 11 and an N-type polysilicon gate 3-2. As described above, on the silicon substrate 1, Ti separated by the insulating film 2
A CMOSFET composed of a Pch MOSFET having a P-type gate electrode 3-1 lined with silicide 9 and an Nch MOSFET having an N-type electrode 3-2 is obtained. According to the present invention, Ti silicide 9
Are formed stably and uniformly on the gate electrode and the source / drain of both the Pch and Nch regions. The gate electrodes of Pch and Nch can be controlled to P-type and N-type, respectively. Further, a shallow junction is formed for both Pch and Nch. Also, instead of PSG12, SiO ₂
A film or a BPSG film may be formed.

〔The invention's effect〕

As described above, according to the present invention, a stable and uniform
CMOSLS with Ti silicide selectively backed and Pch and NchTr with P-type and N-type gate electrodes and shallow junctions respectively
I can be manufactured.

[Brief description of the drawings]

1 to 4 are cross-sectional views showing a manufacturing process of a CMOSFET according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Insulating film 3 ... Gate electrode 3-1 ... P-type polycrystalline silicon 3-2 ... N-type polycrystalline silicon 4 ... Gate film, 5 ... Side wall insulator 6 ... ... resist, 7 ... boron 8 ... Ti, 9 ... Ti silicide 10 ... resist, 11 ... phosphorus 12 ... PSG

Claims (1)

(57) [Claims] (A) An element isolation insulating film for isolating a P-channel transistor region and an N-channel transistor region on a silicon substrate, a gate insulating film of a P-channel transistor, a gate electrode made of polycrystalline silicon, and the P-channel transistor A sidewall insulator of the gate electrode;
Forming a gate insulating film of an N-channel transistor, a gate electrode made of polycrystalline silicon, and a sidewall insulator of the gate electrode of the N-channel transistor; (b) selectively forming boron or fluorine in the P-channel transistor region; (C) forming titanium on the silicon substrate by heat-treating the impurity layer of the P-channel transistor, and (d) forming the impurity layer of the P-channel transistor by heat treatment. A gate electrode, the sidewall insulators of the P-channel and the N-channel transistors, and the silicon substrate on which the element isolation insulating film is not formed; and a gate electrode of the P-channel and the N-channel transistors. Selectively forming titanium silicide; (e) A) removing the unreacted titanium on the element isolation insulating film and on the sidewall insulator of the P-channel and N-channel transistors; and (f) selectively depositing arsenic or phosphorus in the N-channel transistor region. (G) forming an insulating film on the silicon substrate; (h) activating the arsenic or phosphorus by heat treatment to form an impurity layer of the N-channel transistor. Manufacturing method of a semiconductor device.