JPH065750B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH065750B2 JPH065750B2 JP60106905A JP10690585A JPH065750B2 JP H065750 B2 JPH065750 B2 JP H065750B2 JP 60106905 A JP60106905 A JP 60106905A JP 10690585 A JP10690585 A JP 10690585A JP H065750 B2 JPH065750 B2 JP H065750B2
- Authority
- JP
- Japan
- Prior art keywords
- silicide layer
- layer
- silicon substrate
- silicide
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- -1 silicon ions Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、シリコン半導体装置の製造方法に係り、特に
シリサイド層を備え、ＬＳＩの高集積化に好適な半導体
装置の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon semiconductor device, and more particularly to a method for manufacturing a semiconductor device which includes a silicide layer and is suitable for high integration of LSI.
ＬＳＩの集積度を増すためには、接合を浅くし、かつ拡
散層の低抵抗化が必要になるが、このためには、拡散層
の表面内にシリサイド層を設けるのが最も有効である。In order to increase the integration degree of the LSI, it is necessary to make the junction shallow and reduce the resistance of the diffusion layer. For this purpose, it is most effective to provide a silicide layer in the surface of the diffusion layer.
ところで、このシリサイド層を形成する方法としては、
従来からシリコンの表面に金属層を形成し、ついで熱処
理によりこの金属とシリコンを反応させ、シリサイド化
する方法が用いられていた。By the way, as a method of forming this silicide layer,
Conventionally, a method has been used in which a metal layer is formed on the surface of silicon and then this metal is reacted with silicon by heat treatment to form a silicide.
しかしながら、この方法では、シリコンの表面に僅かで
も酸化膜が残つていると、これによつて反応が阻止さ
れ、均一なシリサイド化が得られないという問題があ
る。However, this method has a problem that even if a small amount of an oxide film remains on the surface of silicon, the reaction is blocked thereby, and uniform silicidation cannot be obtained.
そこで、このような問題に対処するため、′84VLSIシン
ポジウムにおける、エム，カクム及びケイ．ハシモトに
よる“ハイ パーフオーマンス シリサイド ソース／
ドレイン ＣＭＯＳＦＥＴウイズアウト パラシテイツ
ク エフエクツ”（High Performance Silicides Sourc
e／Drain CMOSFET without Parasitic Effect）と題す
る論文に記載されているような、第２図に示す工程から
なる方法がある。Therefore, in order to deal with such a problem, M, Kakum and Kay. Hashimoto's “High-Performance Silicide Source /
Drain CMOSFET with out parasitic performance "(High Performance Silicides Sourc
There is a method consisting of the steps shown in FIG. 2 as described in a paper entitled e / Drain CMOSFET without Parasitic Effect).
この第２図において、10はシリコン基板，11は拡散層，
20はゲート絶縁膜，25はサイドウオール，30はゲート電
極，45は金属膜，50はシリサイド層であり、シリコン基
板10に拡散層11とゲート絶縁膜20，それにゲート電極30
を形成したあと、サイドウオール25を設け、ついでモリ
ブデンなどの高融点金属膜45を形成する。その後、今度
はシリコンのイオンを金属膜45とシリコン基体10の界面
にまで注入し、熱処理してシリサイド層50を形成する。In FIG. 2, 10 is a silicon substrate, 11 is a diffusion layer,
20 is a gate insulating film, 25 is a side wall, 30 is a gate electrode, 45 is a metal film, and 50 is a silicide layer. The diffusion layer 11 and the gate insulating film 20 are formed on the silicon substrate 10, and the gate electrode 30
After forming, the side wall 25 is provided, and then the refractory metal film 45 such as molybdenum is formed. Then, this time, silicon ions are injected even to the interface between the metal film 45 and the silicon substrate 10 and heat treatment is performed to form a silicide layer 50.
しかしながら、この第２図の方法でも、シリサイド層50
を均一な厚さに形成するのが難しく、かつ、シリサイド
層50とシリコン基板10との界面に凹凸が形成され易く、
このため、接合のリーク電流が増加したり、電極形成
後、接合耐圧が低下したりすることが多くなり、製品の
歩留りが悪く、しかも、シリサイド化のための工程が複
雑であるという問題がある。However, even with the method of FIG.
Is difficult to form to a uniform thickness, and unevenness is likely to be formed at the interface between the silicide layer 50 and the silicon substrate 10,
For this reason, there are problems that the leak current of the junction increases and the junction breakdown voltage often decreases after the electrodes are formed, the yield of products is low, and the process for silicidation is complicated. .
本発明の目的は、上記した従来技術の問題点を解決し、
シリコン基体の表面状態に無関係に、常に均一なシリサ
イド層を安定して容易に形成することができる製造方法
を提供するにある。The object of the present invention is to solve the above-mentioned problems of the prior art,
Another object of the present invention is to provide a manufacturing method capable of stably and easily forming a uniform silicide layer regardless of the surface condition of a silicon substrate.
この目的を達成するため、本発明は、シリサイド形成の
ための金属を、シリコン基体の表面ではなくて、シリコ
ン基体の表面から中にイオン注入しておき、その後の熱
処理によりシリサイド化するようにした点を特徴とする
もので、この結果、シリサイド層の界面はシリコン基体
の表面状態と無関係に極めて清浄な状態になり、シリサ
イド化が均一に行なわれ、良好なシリサイド層を容易に
得ることができるのである。In order to achieve this object, in the present invention, a metal for forming a silicide is ion-implanted into the surface of the silicon substrate instead of the surface of the silicon substrate, and is silicified by the subsequent heat treatment. As a result, the interface of the silicide layer becomes an extremely clean state regardless of the surface state of the silicon substrate, silicidation is uniformly performed, and a good silicide layer can be easily obtained. Of.
以下、本発明による半導体装置の製造方法について、図
示の実施例により詳細に説明する。Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to illustrated embodiments.
まず、本発明の実施例についての説明に先立って、本発
明にいたるまでの過程でなされた先行例について、第１
図により説明すると、まず、ｎ型シリコン基板10の表面
にフオトエツチングによりゲート絶縁膜20及びゲート電
極30を作り、ゲート・パターンを形成する。ついでゲー
ト電極30をマスクにしてボロンをイオン注入し、熱処理
してｐ型拡散層11を形成する。First, prior to the description of the embodiments of the present invention, the first example of the preceding examples made in the process leading to the present invention will be described.
Explaining with reference to the drawing, first, a gate insulating film 20 and a gate electrode 30 are formed on the surface of the n-type silicon substrate 10 by photo-etching to form a gate pattern. Then, boron is ion-implanted using the gate electrode 30 as a mask and heat treatment is performed to form the p-type diffusion layer 11.
次に、同じくゲート電極30をマスクとして拡散層11の中
にモリブデン・イオンを所定の深さに注入し、モリブデ
ン・イオン打込み層40を形成する。Next, similarly using the gate electrode 30 as a mask, molybdenum ions are implanted into the diffusion layer 11 to a predetermined depth to form a molybdenum ion implantation layer 40.
その後、熱処理してモリブデンとシリコンを反応させ、
モリブデン・シリサイド層50を形成する。After that, heat treatment is performed to react molybdenum and silicon,
A molybdenum silicide layer 50 is formed.
なお、このとき、予じめ拡散層11が形成されたシリコン
基板10を用意し、これから出発するようにしてもよい。At this time, the silicon substrate 10 on which the preliminary diffusion layer 11 has been formed may be prepared and started from this.
この先行例によれば、シリサイド層50が均一に形成で
き、接合のリーク電流が従来法では10-8〜10-6Ａであつ
たものが、10-10Ａ以下に低減できる。更に、シリサイ
ド層50の表面にAl電極形成後、Alが接合をつき抜け接合
が破壊されることによる耐圧不良も発生しなかつた。ま
た、従来法の様にサイドウオール25を形成せずに、ゲー
ト電極30とソース，ドレイン上のシリサイド層50との分
離ができるので、接合の横方向の抵抗が下げられ、か
つ、ソース，ドレイン領域の面積を狭くでき、高集積化
が可能となる 次に、第３図は、本発明の一実施例を示したもので、ま
ず、ポリシリコンのゲート電極30及びゲード絶縁膜20を
ホトエツチングにより(a)の如く加工する。次いで、金
属Moをシリコン基板10の中に注入し、Moイオン打込み層
40を形成する(b)。その後、９５０℃の熱処理を施し、
(c)の如くモリブデンシリサイド層50を形成する。次
に、ボロンをモリブデン・シリサイド層50中にイオン注
入する。続いて、950℃の熱処理を施してボロンを活性
化させ、ｐ型拡散層１１を、(d)に示す如く形成するの
である。According to this prior art example, the silicide layer 50 can be formed uniformly, and the leak current of the junction, which was 10 -8 to 10 -6 A in the conventional method, can be reduced to 10 -10 A or less. Further, after the Al electrode was formed on the surface of the silicide layer 50, Al did not pass through the junction and the junction was broken, so that no withstand voltage failure occurred. Further, since the gate electrode 30 and the silicide layer 50 on the source / drain can be separated without forming the sidewall 25 unlike the conventional method, the lateral resistance of the junction can be reduced and the source / drain can be reduced. Next, FIG. 3 shows an embodiment of the present invention. First, the polysilicon gate electrode 30 and the gate insulating film 20 are photoetched. Process as in (a). Then, the metal M o injected into the silicon substrate 10, M o ion implanted layer
Form 40 (b). After that, heat treatment at 950 ° C is performed,
A molybdenum silicide layer 50 is formed as shown in (c). Next, boron is ion-implanted into the molybdenum silicide layer 50. Then, heat treatment at 950 ° C. is performed to activate boron, and the p-type diffusion layer 11 is formed as shown in (d).
従つて、この実施例によれば、均一な厚さのｐ型拡散層
１１を容易に得ることができ、接合（ｐｎ接合）でのリ
ーク電流を充分に少なく抑え、且つ、逆耐圧の向上を充
分に得ることができるのであるが、その理由について以
下に説明する。Therefore, according to this embodiment, the p-type diffusion layer 11 having a uniform thickness can be easily obtained, the leak current at the junction (pn junction) can be sufficiently suppressed, and the reverse breakdown voltage can be improved. The reason why it can be sufficiently obtained is explained below.
一般に、金属シリサイド中でのボロン、リンなどの不純
物の拡散係数は、シリコン中での拡散係数よりも格段に
大きい（３桁以上）ことが知られている。It is generally known that the diffusion coefficient of impurities such as boron and phosphorus in metal silicide is significantly larger (three digits or more) than the diffusion coefficient in silicon.
このため、上記実施例のように、シリサイド層５０を形
成した後、この中にボロンなどの不純物をイオン注入
し、これによりｐ型拡散層１１を形成するようにしてや
れば、この不純物がシリコン基板１０中に、実質的に拡
散して行く面(フロント)は、このシリサイド層５０とシ
リコン基板１０の界面になり、この結果、シリサイド層
５０の厚みが部分的にばらついて下側の面の形状がばら
ついても、これから拡散されるｐ型拡散層１１の下側の
面の形状が同じくばらついたものとなるので、結果とし
てｐ型拡散層１１の厚みは、シリサイド層５０の厚みの
ばらつきにも関らず、均一に得られるのである。Therefore, as in the above embodiment, if the silicide layer 50 is formed and then impurities such as boron are ion-implanted into the silicide layer 50 to form the p-type diffusion layer 11, the impurities are removed from the silicon substrate. The surface (front) that substantially diffuses in 10 becomes the interface between the silicide layer 50 and the silicon substrate 10, and as a result, the thickness of the silicide layer 50 partially varies and the shape of the lower surface. , The shape of the lower surface of the p-type diffusion layer 11 that is diffused from now on will also vary, and as a result, the thickness of the p-type diffusion layer 11 will also vary depending on the variation in the thickness of the silicide layer 50. Regardless, it can be obtained uniformly.
これに対して、拡散層を形成してから、シリサイド層を
形成する方法では、シリサイド層の厚みがばらついて、
その下面がばらついても、それとは無関係に拡散層が形
成されているので、シリサイド層の厚みのばらつきに対
応して、その厚みが変化してしまうのである。On the other hand, in the method of forming the diffusion layer and then the silicide layer, the thickness of the silicide layer varies,
Even if the lower surface varies, the diffusion layer is formed irrespective of the variation, so that the thickness of the silicide layer changes corresponding to the variation in the thickness of the silicide layer.
なお、このとき、モリブデンのイオン注入に続いて、ボ
ロンをイオン注入した後、熱処理を施し、シリサイド層
の形成とＰ型拡散層の形成を同時に行なつても良い。At this time, following the ion implantation of molybdenum, after ion implantation of boron, heat treatment may be performed to simultaneously form the silicide layer and the P-type diffusion layer.
ところで、イオン注入後シリサイド化する金属として
は、上記実施例におけるモリブデンのほか、Ｗ，Ti，Ta
などの高融点金属が好ましいが、シリサイド化以降のプ
ロセス温度が下げられるならば低抵抗のシリサイドを形
成する金属であれば高融点金属に限らず、どのような金
属でも良い。By the way, as the metal to be silicidized after the ion implantation, in addition to molybdenum in the above embodiment, W, Ti, Ta
A high-melting point metal such as, but not limited to a high-melting point metal, may be used as long as the process temperature after silicidation can be lowered so long as it forms a low-resistance silicide.
以上説明したように、本発明によればシリサイド層が均
一に形成されるので、接合のリーク電流の低減，耐圧の
低下防止などの効果がある。さらに、工程の簡略化も達
成できる。As described above, according to the present invention, since the silicide layer is uniformly formed, there are effects such as reduction of junction leak current and prevention of breakdown voltage reduction. Furthermore, simplification of the process can be achieved.
第１図は本発明による半導体装置の製造方法の先行例を
示す説明図，第２図は従来の製造方法の一例を示す説明
図，第３図(a)〜(d)は本発明の他の一実施例を示す説明
図である。 10……半導体基板，11……拡散層，20……ゲート絶縁
膜，30……ゲート電極，40……金属イオン注入層，50…
…シリサイド層。FIG. 1 is an explanatory view showing a prior example of a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is an explanatory view showing an example of a conventional manufacturing method, and FIGS. 3 (a) to (d) are other drawings of the present invention. It is explanatory drawing which shows one Example. 10 ... Semiconductor substrate, 11 ... Diffusion layer, 20 ... Gate insulating film, 30 ... Gate electrode, 40 ... Metal ion implantation layer, 50 ...
… Silicide layer.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/336 (56)参考文献 特開 昭57−99775（ＪＰ，Ａ) 特開 昭59−210642（ＪＰ，Ａ) 特開 昭60−37169（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical indication H01L 21/336 (56) Reference JP-A-57-99775 (JP, A) JP-A-59- 210642 (JP, A) JP-A-60-37169 (JP, A)
Claims (1)
少なくとも一部の領域にシリサイド層を有し、該シリサ
イド層から所定の深さまでの少なくとも一部の領域に不
純物層を有する半導体装置の製造方法において、上記シ
リコン基体の領域で所定の深さの中間領域に所定の金属
をイオン注入する工程と、このイオン注入された金属を
シリサイド化して上記シリサイド層を形成するため上記
シリコン基体を加熱する熱処理工程と、こうして形成さ
れたシリサイド層に所定の不純物をイオン注入する工程
と、このイオン注入された不純物を拡散及び活性化して
上記不純物層を形成するため上記シリコン基体を加熱す
る熱処理工程とを備えていることを特徴とする半導体装
置の製造方法。1. Manufacturing of a semiconductor device having a silicide layer in at least a part of a region from a surface of a silicon substrate to a predetermined depth and having an impurity layer in at least a part of the silicide layer to a predetermined depth. In the method, a step of ion-implanting a predetermined metal into an intermediate region having a predetermined depth in the region of the silicon substrate, and heating the silicon substrate to silicide the ion-implanted metal to form the silicide layer. A heat treatment step, a step of ion-implanting a predetermined impurity into the silicide layer thus formed, and a heat treatment step of heating the silicon substrate to diffuse and activate the ion-implanted impurity to form the impurity layer. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60106905A JPH065750B2 (en) | 1985-05-21 | 1985-05-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60106905A JPH065750B2 (en) | 1985-05-21 | 1985-05-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61265868A JPS61265868A (en) | 1986-11-25 |
| JPH065750B2 true JPH065750B2 (en) | 1994-01-19 |
Family
ID=14445467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60106905A Expired - Lifetime JPH065750B2 (en) | 1985-05-21 | 1985-05-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065750B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666331B2 (en) * | 1986-03-26 | 1994-08-24 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPS6486560A (en) * | 1987-09-29 | 1989-03-31 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799775A (en) * | 1980-12-12 | 1982-06-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPS59210642A (en) * | 1983-05-16 | 1984-11-29 | Hitachi Ltd | Manufacture of semiconductor device |
-
1985
- 1985-05-21 JP JP60106905A patent/JPH065750B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61265868A (en) | 1986-11-25 |
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