KR100336766B1 - Manufacturing method for mos transistor - Google Patents
Manufacturing method for mos transistor Download PDFInfo
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- KR100336766B1 KR100336766B1 KR1019990046876A KR19990046876A KR100336766B1 KR 100336766 B1 KR100336766 B1 KR 100336766B1 KR 1019990046876 A KR1019990046876 A KR 1019990046876A KR 19990046876 A KR19990046876 A KR 19990046876A KR 100336766 B1 KR100336766 B1 KR 100336766B1
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- ion implantation
- substrate
- halo
- gate
- photoresist
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- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 238000005468 ion implantation Methods 0.000 claims abstract description 35
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 28
- 230000002265 prevention Effects 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 종래 모스 트랜지스터 제조방법은 게이트를 형성한 후, 할로이온주입을 실시하여, 상기 게이트에 의해 이온주입의 경사각 확보가 어려워 원하는 할로방지영역을 형성할 수 없는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판의 상부에 포토레지스트를 도포하고, 이를 노광 및 현상하여 기판의 일부를 노출시키는 게이트 패턴을 형성한 후, 그 노출된 기판에 경사이온주입공정을 통해 할로방지영역을 형성하는 단계와; 상기 포토레지스트를 제거하고, 상기 할로방지영역이 형성된 기판의 상부전면에 게이트산화막, 다결정실리콘, 절연막을 순차적으로 증착한 후, 상기 포토레지스트의 형성시 사용한 마스크를 이용하는 사진식각공정으로, 상기 절연막, 다결정실리콘, 게이트산화막을 식각하여 게이트를 형성하는 단계와; 상기 잔존하는 절연막을 이온주입 마스크로 사용하는 이온주입공정으로 상기 할로방지영역 상부측의 기판에 소스 및 드레인을 형성하는 단계로 구성되어 게이트의 형성위치에 포토레지스트 패턴을 형성하고, 그 단차가 낮은 포토레지스트 패턴을 이온주입마스크로 사용하는 경사이온주입공정으로 원하는 형태의 할로이온주입영역을 용이하게 형성함으로써, 집적도의 저하 없이 모스 트랜지스터의 할로현상을 방지할 수 있는 효과가 있다.The present invention relates to a MOS transistor manufacturing method, the conventional MOS transistor manufacturing method is a halo ion implantation after the gate is formed, it is difficult to secure the inclination angle of the ion implantation by the gate to form a desired halo prevention region There was a problem. In view of the above problems, the present invention applies a photoresist to an upper portion of a substrate, exposes and develops a gate pattern to expose a portion of the substrate, and then exposes the substrate to a halo prevention region through a gradient ion implantation process. Forming a; The photoresist is removed, a gate oxide film, a polysilicon layer, and an insulating film are sequentially deposited on the upper surface of the substrate on which the halo-protection region is formed, and then a photolithography process using a mask used to form the photoresist, wherein the insulating film, Etching the polysilicon and gate oxide film to form a gate; In the ion implantation process using the remaining insulating film as an ion implantation mask, a source and a drain are formed on the substrate on the upper side of the halo-protection region to form a photoresist pattern at a gate formation position, and the step is low. The halo phenomenon of the MOS transistor can be prevented by easily forming a halo ion implantation region having a desired shape in a gradient ion implantation process using a photoresist pattern as an ion implantation mask.
Description
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 단채널효과의 방지를 위한 할로 이온주입공정에서 게이트의 높이에 의해 할로영역이 정확히 형성되지 않는 것을 방지할 수 있는 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor manufacturing method, and more particularly, to a MOS transistor manufacturing method capable of preventing the halo region from being accurately formed by the height of a gate in a halo ion implantation process for preventing short channel effects.
도1a 내지 도1c는 종래 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트산화막(2), 다결정실리콘(3), 절연막(4)을 순차적으로 증착하는 단계(도1a)와; 상기 증착된 절연막(4), 다결정실리콘(3), 게이트산화막(2)의 일부를 패터닝하여 게이트를 형성하는 단계(도1b)와; 상기 절연막(4)을 이온주입마스크로 사용하는 경사이온주입으로 상기 게이트 사이에 노출된 기판(1)에 불순물 이온을 이온주입하여 할로방지영역(5)을 형성하고, 다시 불순물 이온주입을 통해 상기 할로방지영역(5)의 상부측 기판에 소스 및 드레인(6)을 형성하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views illustrating a manufacturing process of a conventional MOS transistor. As shown in the drawing, the steps of sequentially depositing a gate oxide film 2, a polysilicon 3, and an insulating film 4 on the substrate 1 are shown. (FIG. 1A); Patterning a portion of the deposited insulating film (4), polysilicon (3), and gate oxide film (2) to form a gate (FIG. 1B); In the ion implantation using the insulating film 4 as an ion implantation mask, impurity ions are implanted into the substrate 1 exposed between the gates to form a halo prevention region 5, and then the impurity ion implantation Forming a source and a drain 6 on the substrate on the upper side of the halo prevention region 5 (FIG. 1C).
이하, 상기와 같은 종래 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the conventional MOS transistor as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 게이트산화막(2)과, 다결정실리콘(3), 절연막(4)을 순차적으로 증착한다.First, as shown in FIG. 1A, the gate oxide film 2, the polysilicon 3, and the insulating film 4 are sequentially deposited on the substrate 1.
그 다음, 도1b에 도시한 바와 같이 상기 절연막(4)의 상부에 포토레지스트(도면미도시)를 도포하고, 노광 및 현상하여 상기 절연막(4)의 일부를 노출시키는 게이트 패턴을 형성한다.Next, as shown in FIG. 1B, a photoresist (not shown) is applied over the insulating film 4, and exposed and developed to form a gate pattern exposing a part of the insulating film 4.
그 다음, 상기 패턴이 형성된 포토레지스트를 식각마스크로 사용하는 식각공정으로 상기 절연막(4), 다결정실리콘(3), 게이트산화막(2)을 순차적으로 식각하여 상기 기판(1) 상에 게이트와 그 게이트의 상부에 위치하는 절연막(4)을 형성한다.Next, the insulating film 4, the polysilicon 3, and the gate oxide film 2 are sequentially etched in an etching process using the photoresist on which the pattern is formed as an etching mask to form a gate and the same on the substrate 1. An insulating film 4 located above the gate is formed.
그 다음, 도1c에 도시한 바와 같이 상기 절연막(4)을 이온주입 마스크로 사용하는 경사이온주입으로 상기 게이트 측면에 노출된 기판(1)의 하부에 할로방지영역(5)을 형성한다.Next, as shown in FIG. 1C, a halo prevention region 5 is formed under the substrate 1 exposed on the side of the gate by the inclined ion implantation using the insulating film 4 as an ion implantation mask.
이때, 경사이온주입의 경사각(θ)은 상기 게이트와 절연막(4)의 단차에 의해 그 값이 충분히 크지 못하며, 이에 따라 형성되는 할로방지영역(5)은 게이트의 하부측, 즉 채널영역측 까지 형성되지 못한다.At this time, the inclination angle θ of the inclined ion implantation is not large enough due to the step difference between the gate and the insulating film 4, and thus the halo prevention region 5 is formed to the lower side of the gate, that is, to the channel region side. Not formed
이와 같은 이유로 할로방지영역(5)의 역할을 수행할 수 없으므로, 그 할로방지영역(5)을 게이트의 하부일부 기판영역까지 형성하려면 게이트 사이의 기판영역을 넓게하여 상기 경사이온주입의 경사각(θ)이 어느정도 유지될 수 있게해야 하며, 이는 또다른 문제점인 집적도의 저하를 유발한다.For this reason, since the halo prevention region 5 cannot serve as a role, in order to form the halo prevention region 5 up to a portion of the lower substrate region of the gate, the inclination angle θ of the inclined ion implantation is increased by widening the substrate region between the gates. ) Should be maintained to a certain extent, which causes another problem, a decrease in density.
상기한 바와 같이 종래 모스 트랜지스터 제조방법은 게이트를 형성한 후, 할로이온주입을 실시하여, 상기 게이트에 의해 이온주입의 경사각 확보가 어려워 원하는 할로방지영역을 형성할 수 없으며, 이를 해결하기 위해 게이트 사이의 기판영역을 넓게 설정하는 경우 집적도가 감소하는 문제점이 있었다.As described above, in the conventional MOS transistor manufacturing method, after forming a gate, halo ion implantation is performed, and thus it is difficult to secure an inclination angle of ion implantation by the gate, so that a desired halo prevention region cannot be formed. There was a problem that the degree of integration decreases when the substrate area of the substrate is set wide.
이와 같은 문제점을 감안한 본 발명은 게이트의 사이 기판영역이 좁은 경우에도 할로이온주입을 위한 경사이온주입의 경사각을 충분히 확보할 수 있는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a MOS transistor manufacturing method capable of sufficiently securing the inclination angle of the inclined ion implantation for the halo ion implantation even when the substrate region between the gates is narrow.
도1a 내지 도1c는 종래 모스 트랜지스터의 제조공정 수순단면도.1A to 1C are cross-sectional views illustrating a manufacturing process of a conventional MOS transistor.
도2a 내지 도2c는 본 발명 모스 트랜지스터의 제조공정 수순단면도.2A to 2C are cross-sectional views of a manufacturing process of the MOS transistor of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:게이트산화막1: Substrate 2: Gate Oxide
3:다결정실리콘 4:절연막3: polycrystalline silicon 4: insulating film
5:할로방지영역 6:소스 및 드레인5: halo protection area 6: source and drain
상기와 같은 목적은 기판의 상부에 포토레지스트를 도포하고, 이를 노광 및 현상하여 기판의 일부를 노출시키는 게이트 패턴을 형성한 후, 그 노출된 기판에 경사이온주입공정을 통해 할로방지영역을 형성하는 단계와; 상기 포토레지스트를 제거하고, 상기 할로방지영역이 형성된 기판의 상부전면에 게이트산화막, 다결정실리콘, 절연막을 순차적으로 증착한 후, 상기 포토레지스트의 형성시 사용한 마스크를 이용하는 사진식각공정으로, 상기 절연막, 다결정실리콘, 게이트산화막을 식각하여 게이트를 형성하는 단계와; 상기 잔존하는 절연막을 이온주입 마스크로 사용하는 이온주입공정으로 상기 할로방지영역 상부측의 기판에 소스 및 드레인을 형성하는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to apply a photoresist on top of the substrate, and to expose and develop a gate pattern to expose a portion of the substrate, and then to form a halo prevention region through the inclined ion implantation process on the exposed substrate Steps; The photoresist is removed, a gate oxide film, a polysilicon layer, and an insulating film are sequentially deposited on the upper surface of the substrate on which the halo-protection region is formed, and then a photolithography process using a mask used to form the photoresist, wherein the insulating film, Etching the polysilicon and gate oxide film to form a gate; It is achieved by forming a source and a drain on the substrate on the upper side of the halo prevention region by an ion implantation process using the remaining insulating film as an ion implantation mask, which is described in detail with reference to the accompanying drawings. The explanation is as follows.
도2a 내지 도2c는 본 발명 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 포토레지스트(PR)를 도포하고, 이를 노광 및 현상하여 기판(1)의 일부를 노출시키는 게이트 패턴을 형성한 후, 그 노출된 기판(1)에 경사이온주입공정을 통해 할로방지영역(5)을 형성하는 단계(도2a)와; 상기 포토레지스트(PR)를 제거하고, 상기 할로방지영역(5)이 형성된 기판(1)의 상부전면에 게이트산화막(2), 다결정실리콘(3), 절연막(4)을 순차적으로 증착한 후, 상기 포토레지스트(PR)의 형성시 사용한 마스크를 이용하는 사진식각공정으로, 상기절연막(4), 다결정실리콘(3), 게이트산화막(2)을 식각하여 게이트를 형성하는 단계(도2b)와; 상기 잔존하는 절연막(4)을 이온주입 마스크로 사용하는 이온주입공정으로 상기 할로방지영역(5) 상부측의 기판(1)에 소스 및 드레인(6)을 형성하는 단계(도2c)로 구성된다.2A to 2C are cross-sectional views illustrating a manufacturing process of the MOS transistor according to the present invention. As shown therein, a photoresist PR is coated on an upper portion of the substrate 1, and a part of the substrate 1 is exposed and developed. Forming a gate pattern for exposing and then forming a halo prevention region 5 on the exposed substrate 1 through a gradient ion implantation process (FIG. 2A); After removing the photoresist PR and sequentially depositing a gate oxide film 2, a polysilicon 3, and an insulating film 4 on the upper surface of the substrate 1 on which the halo-protection region 5 is formed, Forming a gate by etching the insulating film 4, the polysilicon 3, and the gate oxide film 2 by a photolithography process using a mask used to form the photoresist PR (FIG. 2B); In the ion implantation process using the remaining insulating film 4 as an ion implantation mask, a source and a drain 6 are formed on the substrate 1 on the upper side of the halo prevention region 5 (FIG. 2C). .
이하, 상기와 같은 본 발명을 좀 더 상세히 설명한다.Hereinafter, the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부전면에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 기판(1)의 상부일부를 노출시키는 패턴을 형성한다.First, as shown in FIG. 2A, a photoresist PR is applied to the upper front surface of the substrate 1, and exposed and developed to form a pattern for exposing a portion of the upper portion of the substrate 1.
그 다음, 경사이온주입을 통해 상기 노출된 기판(1)의 하부영역과 상기 포토레지스트(PR) 패턴의 하부측면부의 기판(1)영역에 할로방지영역(5)을 형성한다.Next, a halo prevention region 5 is formed in the lower region of the exposed substrate 1 and the substrate 1 region of the lower side portion of the photoresist PR pattern through the inclination ion implantation.
이때, 상기 할로방지영역(5)을 형성하기 위한 경사이온주입의 경사각(θ)은 종래에 비해 포토레지스트(PR) 패턴 하나의 층으로 그 단차가 낮아지기 때문에 동일한 이온주입영역을 갖는 경우 선택범위를 확대할 수 있다. 이에 따라 상기 포토레지스트(PR) 패턴의 하부측 기판영역에도 용이하게 할로방지영역(5)을 형성할 수 있게 된다.At this time, the inclination angle θ of the inclined ion implantation for forming the halo prevention region 5 is a single layer of photoresist (PR) pattern as compared with the prior art, so that the step is lowered, so that the same ion implantation region has a selection range. You can zoom in. Accordingly, the halo prevention region 5 can be easily formed in the lower substrate region of the photoresist PR pattern.
그 다음, 도2b에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 제거하여, 상기 기판(1)의 상부전면을 노출시킨 후, 그 할로방지영역(5)이 형성된 기판(1)의 상부전면에 게이트산화막(2), 다결정실리콘(3), 절연막(4)을 순차적으로 증착한다.Next, as shown in FIG. 2B, the photoresist PR pattern is removed to expose the upper front surface of the substrate 1, and then the upper front surface of the substrate 1 on which the halo-protection region 5 is formed. The gate oxide film 2, the polysilicon 3, and the insulating film 4 are deposited sequentially.
그 다음, 상기 포토레지스트(PR)를 형성한 마스크를 이용하는 사진식각공정으로 상기 절연막(4), 다결정실리콘(3), 게이트산화막(2)을 순차적으로 식각하여 상기포토레지스트(PR) 패턴이 위치하던 자리에 게이트를 형성한다.Next, the photoresist PR pattern is positioned by sequentially etching the insulating film 4, the polysilicon 3, and the gate oxide film 2 by a photolithography process using a mask on which the photoresist PR is formed. Form a gate in place.
그 다음, 도2c에 도시한 바와 같이 상기 게이트의 측면 기판(1)하부에 불순물 이온을 이온주입하여 소스 및 드레인(6)을 형성한다.Then, as shown in FIG. 2C, impurity ions are implanted into the lower side of the side substrate 1 of the gate to form a source and a drain 6.
상기한 바와 같이 본 발명은 게이트의 형성위치에 포토레지스트 패턴을 형성하고, 그 단차가 낮은 포토레지스트 패턴을 이온주입마스크로 사용하는 경사이온주입공정으로 원하는 형태의 할로이온주입영역을 용이하게 형성함으로써, 집적도의 저하 없이 모스 트랜지스터의 할로현상을 방지할 수 있는 효과가 있다.As described above, in the present invention, a photoresist pattern is formed at a gate formation position, and a halo ion implantation region having a desired shape is easily formed by a gradient ion implantation process using a photoresist pattern having a low level as an ion implantation mask. In addition, the halo phenomenon of the MOS transistor can be prevented without degrading the degree of integration.
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