KR100244470B1 - A fabrication method of dual gate oxide film for semiconductor device - Google Patents

A fabrication method of dual gate oxide film for semiconductor device Download PDF

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KR100244470B1
KR100244470B1 KR1019970018534A KR19970018534A KR100244470B1 KR 100244470 B1 KR100244470 B1 KR 100244470B1 KR 1019970018534 A KR1019970018534 A KR 1019970018534A KR 19970018534 A KR19970018534 A KR 19970018534A KR 100244470 B1 KR100244470 B1 KR 100244470B1
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gate oxide
polysilicon
oxide film
photoresist
semiconductor device
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KR1019970018534A
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KR19980083286A (en
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이계남
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체소자의 듀얼 게이트산화막 제조방법에 관한 것으로, 종래에는 제2폴리실리콘을 식각할때 제1폴리실리콘이 손상을 입는 문제점과, 상기의 문제점을 해결하기 위하여 제2폴리실리콘을 완전히 식각하지 않을 경우는 그 제2폴리실리콘의 미식각영역이 형성되는 문제점과, 제2산화막을 증착할때 제1폴리실리콘의 원자배열이 비정질에서 결정화 됨에 따라 후속 이온주입공정에서 이온이 기판으로 침투되는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 기판의 좌우측상부에 포토레지스트를 도포한후, 그 포토레지스트가 도포되지 않은 영역에 Si 이온을 주입하는 단계와, 상기 포토레지스트를 제거한후, 산화공정을 실시하여 두께가 상이한 제1,제2게이트산화막을 형성하는 단계와, 상기 제1,제2게이트산화막의 상부에 폴리실리콘을 증착하는 단계와, 상기 제1,제2게이트산화막 상부의 폴리실리콘의 상부에 각각 포토레지스트를 도포한후, 상기 폴리실리콘을 식각하는 단계와, 상기 각 포토레지스트를 제거하는 단계로 반도체소자의 듀얼 게이트산화막을 제조하여 제2게이트산화막이 형성되는 영역에 미리 Si 이온을 주입함으로써, 두께가 상이한 게이트산화막의 형성이 용이한 효과와, 산화공정에 의해 게이트산화막을 형성함으로써, 공정중에 발생할 수 있는 불량발생을 최소화할 수 있는 효과가 있다.The present invention relates to a method for manufacturing a dual gate oxide film of a semiconductor device, and in the related art, the first polysilicon is damaged when the second polysilicon is etched, and the second polysilicon is completely etched to solve the above problem. If not, the problem of the formation of the embossed region of the second polysilicon and the deposition of the second oxide film causes the ions to penetrate into the substrate in the subsequent ion implantation process as the atomic arrangement of the first polysilicon crystallizes in amorphous form. There was a problem. In view of the above problems, the present invention applies a photoresist to the upper left and right sides of a substrate, and then implants Si ions into a region where the photoresist is not applied, and removes the photoresist, and then performs an oxidation process to perform a thickness. Forming first and second gate oxide films different from each other, depositing polysilicon on top of the first and second gate oxide films, and forming polysilicon on top of the first and second gate oxide films, respectively. After the photoresist is applied, the polysilicon is etched and the photoresist is removed to prepare a dual gate oxide film of a semiconductor device and to inject Si ions into a region where a second gate oxide film is formed. The effect of easily forming a gate oxide film having a different thickness and forming a gate oxide film by an oxidation process can cause defects that may occur during the process. It is effective to minimize life.

Description

반도체소자의 듀얼 게이트산화막 제조방법Method of manufacturing dual gate oxide film of semiconductor device

본 발명은 반도체소자의 듀얼(dual) 게이트산화막 제조방법에 관한 것으로, 특히 듀얼 게이트산화막의 형성이 용이하면서도 결함발생을 줄이기에 적당하도록 한 반도체소자의 듀얼 게이트산화막 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a dual gate oxide film of a semiconductor device, and more particularly, to a method of manufacturing a dual gate oxide film of a semiconductor device which is suitable for easily forming a dual gate oxide film and reducing defects.

일반적으로, 모스트랜지스터는 게이트에 인가되는 전압의 제어에 의해 동작한다. 따라서, 상기 게이트에 인가되는 전압이 복수개인 입출력회로의 경우는 각 전압에 따른 복수개의 모스트랜지스터가 필요하다. 이러한 단점을 극복하기 위하여 최근에는 게이트산화막의 두께를 선택적으로 서로 다르게 형성함으로써, 하나의 모스트랜지스터에 듀얼 게이트를 제조하는 방법이 많이 사용되고 있다. 이와같은 종래 반도체소자의 듀얼 게이트산화막 제조방법을 첨부한 도면을 참조하여 설명하면 다음과 같다.In general, the MOS transistor operates by controlling the voltage applied to the gate. Therefore, in the case of an input / output circuit having a plurality of voltages applied to the gate, a plurality of MOS transistors corresponding to respective voltages are required. In order to overcome these disadvantages, a method of manufacturing a dual gate in one MOS transistor has been widely used in recent years by selectively forming different thicknesses of the gate oxide film. Referring to the accompanying drawings, a method of manufacturing a dual gate oxide film of a conventional semiconductor device is as follows.

도1은 종래 반도체소자의 듀얼 게이트산화막 제조방법의 수순단면도로서, 이에 도시한 바와같이 기판(1)의 상부에 제1게이트산화막(2)과 제1폴리실리콘(3)을 순차적으로 증착하는 단계(도1a)와, 상기 제1폴리실리콘(3)의 일측상부에 포토레지스트(7)를 도포한후, 그 포토레지스트(7)가 도포되지 않은 제1폴리실리콘(3)의 타측상부를 식각하고, 그 하부의 제1게이트산화막(2)을 식각하여 기판(1)의 일측을 노출시키는 단계(도1b)와, 상기 포토레지스트(7)를 제거한후, 상기 노출된 기판(1)의 상부에 제2게이트산화막(4)을 증착하는 단계(도1c)와, 상기 제1폴리실리콘(3) 및 제2게이트산화막(4)의 상부에 제2폴리실리콘(5)을 증착하는 단계(도1d)와, 상기 제2게이트산화막(4)의 상부에 증착된 제2폴리실리콘(5)의 상부에 포토레지스트(7`)를 도포한후, 그 포토레지스트(7`)가 도포되지 않은 제2폴리실리콘(5) 및 제2게이트산화막(4)을 식각 및 세정하는 단계(도1e)와, 상기 포토레지스트(7`)를 제거하는 단계(도1f)로 이루어진다.FIG. 1 is a process cross-sectional view of a method of manufacturing a dual gate oxide film of a conventional semiconductor device, and the steps of sequentially depositing the first gate oxide film 2 and the first polysilicon 3 on the substrate 1 as shown in FIG. (A) and after the photoresist 7 is applied on the upper side of the first polysilicon 3, the upper part of the first polysilicon 3 on which the photoresist 7 is not applied is etched. Etching the lower first gate oxide layer 2 to expose one side of the substrate 1 (FIG. 1B), removing the photoresist 7, and then removing the upper portion of the exposed substrate 1 Depositing a second gate oxide film 4 on the second polysilicon layer 5 (FIG. 1C), and depositing a second polysilicon 5 on the first polysilicon 3 and the second gate oxide film 4 (FIG. 1C). 1d) and the photoresist 7` on the second polysilicon 5 deposited on the second gate oxide film 4, and then the photoresist 7` is applied. Four non comprises a second polysilicon 5 and the second gate oxide film 4 and the etching step of cleaning (Fig. 1e), and a step (Fig. 1f) of removing the photoresist (7`) a.

여기서, 제1,제2게이트산화막(2),(4)은 게이트에 인가되는 전압에 따라 선택적으로 두께를 서로 다르게 형성하고, 미설명부호 '6'은 상기 제2폴리실리콘(5)의 미식각영역이다.Here, the first and second gate oxide films 2 and 4 may be formed to have different thicknesses selectively according to the voltage applied to the gate, and reference numeral '6' denotes the taste of the second polysilicon 5. Each area.

그러나, 상기한 바와같이 제조되는 종래 반도체소자의 듀얼 게이트산화막 제조방법은 제2폴리실리콘을 식각할때 제1폴리실리콘이 손상을 입는 문제점과, 상기의 문제점을 해결하기 위하여 제2폴리실리콘을 완전히 식각하지 않을 경우는 그 제2폴리실리콘의 미식각영역이 형성되는 문제점과, 제2산화막을 증착할때 제1폴리실리콘의 원자배열이 비정질(amorphous)에서 결정(crystal)화 됨에 따라 후속 이온주입공정에서 이온이 기판으로 침투되는 문제점이 있었다.However, in the method of manufacturing a dual gate oxide film of a conventional semiconductor device manufactured as described above, the first polysilicon is damaged when the second polysilicon is etched, and the second polysilicon is completely removed to solve the above problem. If not etched, the second polysilicon is formed in the etched region, and the subsequent ion implantation as the atomic arrangement of the first polysilicon crystallizes amorphous in the deposition of the second oxide film. There was a problem that ions penetrate into the substrate in the process.

상기한 문제점들은 반도체소자의 제조시 그 특성열화의 원인이 되었다.The above problems have caused the deterioration of characteristics in the manufacture of semiconductor devices.

따라서, 본 발명은 상기한 바와같은 문제점들을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 듀얼(dual) 게이트산화막의 형성이 용이하면서도 결함발생을 줄일수 있는 반도체소자의 듀얼 게이트산화막 제조방법을 제공하는 데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a dual gate oxide film of a semiconductor device that can easily form a dual gate oxide film and reduce defects. There is.

도1은 종래 반도체소자의 듀얼 게이트산화막 제조방법의 수순단면도.1 is a cross-sectional view of a conventional method for manufacturing a dual gate oxide film of a semiconductor device.

도2는 본 발명에 의한 반도체소자의 듀얼 게이트산화막 제조방법의 수순단면도.2 is a cross-sectional view of a method for manufacturing a dual gate oxide film of a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판2,4:게이트산화막1: substrate 2, 4: gate oxide film

3:폴리실리콘7,7`:포토레지스트3: polysilicon 7,7`: photoresist

상기한 바와같은 목적을 달성하기 위한 본 발명에 의한 반도체소자의 듀얼 게이트산화막 제조방법은 기판의 상부에 제2게이트산화막이 형성될 영역을 정의하고, 그 영역에 Si 이온을 주입하는 단계와, 상기 기판의 상부전면에 산화공정을 실시하여 두께가 상이한 제1,제2게이트산화막을 형성하는 단계와, 상기 제1,제2게이트산화막의 상부에 폴리실리콘을 증착하는 단계와, 상기 폴리실리콘을 부분적으로 식각하는 단계로 이루어지는 것을 특징으로 한다. 이하, 본 발명에 의한 반도체소자의 듀얼 게이트산화막 제조방법을 실시예를 들어 설명하면 다음과 같다.A method of manufacturing a dual gate oxide film of a semiconductor device according to the present invention for achieving the above object includes defining a region where a second gate oxide film is to be formed on an upper portion of a substrate, and implanting Si ions into the region; Performing an oxidation process on the upper surface of the substrate to form first and second gate oxide films having different thicknesses, depositing polysilicon on the first and second gate oxide films, and partially depositing the polysilicon. It characterized in that the step consisting of etching. Hereinafter, a method for manufacturing a dual gate oxide film of a semiconductor device according to the present invention will be described with reference to Examples.

도2는 본 발명에 의한 반도체소자의 듀얼 게이트산화막 제조방법의 수순단면도로서, 이에 도시한 바와같이 기판(1)의 좌우측상부에 포토레지스트(7)를 도포한후, 그 포토레지스트(7)가 도포되지 않은 영역에 Si 이온을 주입하는 단계(도2a)와, 상기 포토레지스트(7)를 제거한후, 산화공정(oxidation)을 실시하여 두께가 상이한 게이트산화막(2),(4)을 형성하는 단계(도2b)와, 상기 게이트산화막(2),(4)의 상부에 폴리실리콘(3)을 증착하는 단계(도2c)와, 상기 게이트산화막(2),(4) 상부의 폴리실리콘(3)의 상부에 각각 포토레지스트(7`)를 도포하는 단계(도2d)와, 상기 폴리실리콘(3)을 식각하는 단계(도2e)와, 상기 각 포토레지스트(7`)를 제거하는 단계(도2f)로 이루어진다.FIG. 2 is a cross sectional view of a method for manufacturing a dual gate oxide film of a semiconductor device according to the present invention. After the photoresist 7 is applied to the upper left and right sides of the substrate 1 as shown in FIG. Implanting Si ions into the uncoated region (FIG. 2A), removing the photoresist 7, and then performing oxidation to form gate oxide films 2 and 4 having different thicknesses. 2B), depositing polysilicon 3 on the gate oxide films 2 and 4 (FIG. 2C), and polysilicon on the gate oxide films 2 and 4 3) applying photoresist 7 'on top of each other (FIG. 2D), etching the polysilicon 3 (FIG. 2E), and removing each photoresist 7'. (FIG. 2F).

여기서, 산화공정을 실시하여 두께가 상이한 게이트산화막(2),(4)을 형성하는 단계를 조금더 상세히 설명하면 다음과 같다.Here, the steps of forming the gate oxide films 2 and 4 having different thicknesses by performing the oxidation process will be described in more detail as follows.

도2a에 도시한 바와같이 상기 기판(1)에 Si 이온을 주입하면, 그 이온주입으로 인해 기판(1)의 Si 원자배열이 손상을 입게되고, 이후 도2b에 도시한 바와같이 산화공정에서 Si 원자는 산소와 반응이 용이해진다. 따라서, 그 Si 이온이 주입된 영역에서 Si 이온이 주입되지 않은 영역보다 두께가 더 두꺼운 게이트산화막(4)이 형성된다.As shown in FIG. 2A, when Si ions are implanted into the substrate 1, the Si implantation of the substrate 1 is damaged due to the ion implantation, and then Si is oxidized in the oxidation process as shown in FIG. 2B. Atoms easily react with oxygen. Thus, in the region in which the Si ions are implanted, the gate oxide film 4 having a thicker thickness than the region in which the Si ions are not implanted is formed.

상기한 바와같은 본 발명에 의한 반도체소자의 듀얼 게이트산화막 제조방법은 두꺼운 게이트산화막이 형성되는 영역에 미리 Si 이온을 주입함으로써, 두께가 상이한 게이트산화막의 형성이 용이한 효과와, 산화공정에 의해 게이트산화막을 형성함으로써, 공정중에 발생할 수 있는 불량발생을 최소화할 수 있는 효과가 있다.In the method for manufacturing a dual gate oxide film of a semiconductor device according to the present invention as described above, by injecting Si ions into a region where a thick gate oxide film is formed in advance, the gate oxide film having a different thickness can be easily formed, and the gate can be formed by an oxidation process. By forming the oxide film, there is an effect that can minimize the occurrence of defects that can occur during the process.

상기한 효과들에 의해 반도체소자의 특성을 향상시킬 수 있다.It is possible to improve the characteristics of the semiconductor device by the above effects.

Claims (1)

기판의 좌우측상부에 포토레지스트를 도포한후, 그 포토레지스트가 도포되지 않은 영역에 Si 이온을 주입하는 단계와, 상기 포토레지스트를 제거한후, 산화공정을 실시하여 두께가 상이한 제1,제2게이트산화막을 형성하는 단계와, 상기 제1,제2게이트산화막의 상부에 폴리실리콘을 증착하는 단계와, 상기 제1,제2게이트산화막 상부의 폴리실리콘의 상부에 각각 포토레지스트를 도포한후, 상기 폴리실리콘을 식각하는 단계와, 상기 각 포토레지스트를 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 듀얼 게이트산화막 제조방법.After the photoresist is applied to the upper left and right sides of the substrate, Si ions are implanted into the region where the photoresist is not applied, and after removing the photoresist, an oxidation process is performed to perform first and second gates having different thicknesses. Forming an oxide film, depositing polysilicon on the first and second gate oxide films, and applying photoresist on top of the polysilicon on the first and second gate oxide films, respectively, And etching the polysilicon and removing each photoresist.
KR1019970018534A 1997-05-13 1997-05-13 A fabrication method of dual gate oxide film for semiconductor device KR100244470B1 (en)

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