KR100796802B1 - Manufacturing method of thin film transistor substrate for liquid crystal display - Google Patents

Abstract

Forming a gate wiring including a gate line and a gate electrode, forming a data wiring including a data line, a source electrode, and a drain electrode that are insulated from and cross the gate line to define a pixel region, and then connect the pixel electrode connected to the drain electrode. Form. In the method of manufacturing a thin film transistor substrate for a liquid crystal display device, at least one of the gate wiring, the data wiring, and the pixel electrode is formed by a photolithography process using a divided exposure region in which a plurality of regions are divided and exposed. The light shielding mask for shielding light so that light is not irradiated to other regions except for the light shielding mask is disposed to have a light shielding margin of 2 μm or more so as to cross the boundary of the exposure region. By forming the wiring in this manner, it is possible to prevent the stitch phenomenon occurring at the boundary of the divided exposure region due to aging of the optical equipment.

Shading mask, shading margin, alignment margin, stitch, split exposure area (shot)

Description

The manufacturing method of the thin-film transistor board | substrate for liquid crystal display devices {MANUFACTURING METHOD OF THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II 'of the thin film transistor substrate for a liquid crystal display device shown in FIG.

3A, 4A, 5A, and 8A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention by a stepper exposure method,

FIG. 3B is a cross sectional view taken along the line IIIb-IIIb 'in FIG. 3A;

4B is a cross sectional view taken along the line IVb-IVb 'in FIG. 4A and showing the next step of FIG. 3B;

5B and 5C are sectional views taken along lines Vb-Vb 'and Vc-Vc', respectively;

6A and 6B are cross-sectional views illustrating a forming step of FIG. 5B;

7A and 7B are cross-sectional views illustrating a forming step of FIG. 5C;

FIG. 8B is a cross sectional view taken along the line DD-D 'in FIG. 8A, showing the next steps of FIGS. 5B and 5C;                 

8C and 8D are cross sectional views taken along lines VII-VIIc 'and VIId-VIId', respectively;

9A and 9B are cross-sectional views illustrating a forming step of FIG. 8C;

10A and 10B are cross-sectional views illustrating the forming step of FIG. 8D;

11A and 11B are cross-sectional views taken along lines Cc-Cc and Dd-Dd, respectively, and are cross-sectional views of pixel electrodes formed by moving to boundary portions of regions different from those of the divisional exposure region regions of FIGS. 8C and 8D;

12A and 12B are cross-sectional views illustrating the forming step of FIG. 11A;

13A and 13B are cross-sectional views illustrating the forming step of FIG. 11B.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the thin film transistor substrate for a liquid crystal display device reduces a stitch phenomenon generated in a stepper exposure method in which the substrate is divided into a plurality of regions and exposed. It relates to a method for producing.

The liquid crystal display is one of the most widely used flat panel display devices, which injects liquid crystals between two substrates on which electrodes are formed and between them, and transmits voltage by applying a voltage to the electrodes to rearrange the liquid crystal molecules of the liquid crystal layer. It is a display device that controls the amount of light.

Each unit pixel of the liquid crystal display device is made of a transparent conductive material, and a pixel electrode for displaying operation is formed. The pixel electrode is driven by a signal applied through a wiring. The wiring includes a gate line and a data line crossing each other to define a unit pixel region, and the wiring is connected to the pixel electrode through a switching element such as a thin film transistor. At this time, the switching element controls the image signal from the data line transmitted to the pixel electrode through the scan signal from the gate line.

In this case, there is a stepper method in which one substrate is separated and exposed to a plurality of regions among one of the exposure methods most commonly used as the exposure apparatus in the photolithography process of the liquid crystal display device.

In the stepper method, since it is impossible to expose the entire photoresist film to the entire substrate by only one process, the pattern is formed on the entire substrate in shot units while replacing a reticle, which is a set of mask patterns. This method has a big disadvantage that the fabrication cost is low and the overall alignment is improved, whereas stitches due to overlap or discontinuity of the alignment occur at each shot boundary.

In particular, when exposing one area, the other area is covered using a light shielding film so that light is not irradiated to the photoresist film. However, due to natural aging of the photo equipment, focusing is unstable and shading becomes unstable. Due to such unstable light shielding, the photosensitive film pattern for forming the data line and the pixel electrode in the shot boundary region is double exposed. As a result, the pixel electrode and the data line are formed to have a narrower width than the wirings of other regions in the shot boundary region, so that the coupling capacitance generated between them differs from the boundary portion of the exposure region shot, and thus the display characteristics. This appears different.

The technical problem to be achieved by the present invention relates to a method of manufacturing a thin film transistor substrate for a liquid crystal display device that can prevent the stitch phenomenon even if the photo equipment used in the stepper method is aged.

In order to solve this problem, in the manufacturing method according to the present invention, the light shielding mask is disposed with a light shielding margin larger than the alignment margin in the exposure process for forming the wiring.

According to the present invention, first, a gate wiring including a gate line and a gate electrode is formed, and then a data wiring including a data line, a source electrode, and a drain electrode, which is insulated from and crosses the gate line to define a pixel region, and then a drain electrode. And a pixel electrode connected to each other.

In the method of manufacturing a thin film transistor substrate for a liquid crystal display device, at least one of the gate wiring, the data wiring, and the pixel electrode is formed by a photolithography process using a divisional exposure method in which the exposure is divided into a plurality of regions, and the exposure during the divisional exposure. A light shielding mask that shields light so that light is not irradiated to other areas except the area is provided with a light shielding margin beyond the boundary of the exposure area.

At this time, it is preferable to keep the light-shielding margin at 2 micrometers or more.                     

In this case, the boundary portions of the exposure regions when forming the gate wirings, the data wirings, and the pixel electrodes may be the same.

Alternatively, the boundary of the exposure area may be different when forming the gate wiring, the data wiring, and the pixel electrode.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention. .

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II 'of the thin film transistor substrate shown in FIG.

The lower layers 220, 240, and 260 made of chromium (Cr) or molybdenum (Mo), which are excellent in contact properties with other materials, on the insulating substrate 10 and aluminum-based conductive materials having low resistance such as Al-Nd. A gate wiring including upper layers 221, 241, and 261 made of a material is formed. The gate wiring is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate lines 22, 24, and 26, and the gate insulating film 30 is formed with a gate pad along with a protective film 70 formed thereafter. It has a contact hole 74 exposing 24, and at the contact hole 74 the aluminum alloy layer 241 is removed to reveal the chromium layer 240.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 of the gate electrode 24, and n + is doped with silicide or n-type impurities at a high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, lower layers 650, 660, and 680 made of chromium (Cr) or molybdenum (Mo), which are materials having excellent contact properties with other materials such as gate wirings, and the like; A data line including upper layers 651, 661, and 681 made of an aluminum-based conductive material such as Al-Nd is formed. The data line is formed in the vertical direction and is connected to the data line 62 and the data line 62 which define the unit pixel by crossing the gate line 22 and extend to the upper portion of the ohmic contact layer 55. 64, a data pad 68 connected to one end of the data line 62 and separated from the source electrode 64 and the source electrode 64 to which an image signal from the outside is applied, and the source electrode 64 with respect to the gate electrode 26; And a drain electrode 66 formed over the opposite ohmic contact layer 56.

The passivation layer 70 is formed on the data lines 62, 64, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. The protective film 70 has contact holes 76 and 78 exposing the drain electrode 66 and the data pad 68. In this case, the upper layers 661 and 681 are removed from the contact holes 76 and 78 to expose the lower layers 660 and 680, respectively. In addition, the passivation layer 70 has a contact hole 74 that exposes only the bottom 240 of the gate pad together with the gate insulating layer 30.

On the passivation layer 70, the pixel electrode 82 and the contact holes 74 and 78 positioned in the pixel are electrically connected to the lower layer 660 of the drain electrode through the contact hole 76, respectively. 240 and an auxiliary gate pad 86 and an auxiliary data pad 88 electrically connected to the data pad lower layer 680, and are made of indium tin oxide (ITO) or indium zinc oxide (IZO). The pattern is formed.

Here, the drain electrodes 66, the gate pads 24, and the upper layers 661, 241, and 681 of the data pads 68, which are made of aluminum-based metals exposed through the contact holes, are removed, respectively, and are in contact with other materials. The lower layers 660, 240 and 680 made of chromium (Cr) or molybdenum (Mo), which are excellent materials, and the conductive film patterns 82, 86 and 88 of ITO or IZO are brought into contact with each other to lower the contact resistance.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Then, FIGS. 1 and 2 and a manufacturing method of the liquid crystal display using a stepper method for separating and exposing the thin film transistor substrate for a liquid crystal display device having a structure according to an embodiment of the present invention into a plurality of areas. It will be described in detail with reference to 3a to 13b. In the figure, shot A and shot B represent regions to be dividedly exposed, and a dotted line is located above the data line as a boundary of the divided exposure.

First, as shown in FIGS. 3A and 3B, the lower layers 220, 240, and 260 are made of chromium and the upper layers 221, 241, and 261 are made of Al-Nd and sequentially stacked on the insulating substrate 10. The photosensitive film pattern (not shown) for gate wiring is formed by dividing into the area | region of shot A and shot B, exposing and developing. Subsequently, the lower layers 220, 240, and 260 and the upper layers 221, 241, and 261 are patterned using a photoresist pattern (not shown) as an etch mask to form a gate line 22, a gate pad 24, and a gate electrode. The horizontal gate wiring including 26 is formed.

Next, as shown in FIGS. 4A and 4B, the three-layer films of the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 are successively stacked, and the shot A and shot B regions are stacked. The photoresist layer is exposed to light and developed to form a semiconductor photoresist pattern, and the semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned using the patterning process using the same to pattern the upper portion of the gate insulating layer 30 facing the gate electrode 26. The semiconductor layer 40 and the ohmic contact layer 50 are formed thereon.

Next, as shown in 5a to 5c, the lower film 600 of chromium and the upper film 601 of Al-Nd are sequentially stacked, dividedly exposed to the short A and short B areas, and developed to develop the data photoresist pattern 110a for data. , 110b, 120a, and 121b, and the upper layer 601 and the lower layer 600 are etched using the etching mask to form the data lines 62a, 62b, 65b, 66b, and 68b. At this time, due to the focusing instability caused by aging of the photo equipment of the stepper, the data wiring photoresist patterns 110a, 110b, 120a, and 121b are double exposed at the boundary of the divided exposure area, and when this part is developed, the data wiring photoresist pattern ( The width of 110a, 110b, 120a, 121b is reduced. In order to solve this problem, a light shielding mask covering the remaining areas other than the exposure area so as not to irradiate light is disposed with a light shielding margin so as to cover part of the exposure area. That is, the shot A area is disposed with a light shielding margin so as to cover part of the shot A area with a light shielding mask covering the remaining area including the shot B area during exposure. This will be described in detail with reference to FIGS. 6A to 7B.

6A and 6B are cross-sectional views taken along the line Vb-Vb 'in FIG. 5A, and FIGS. 7A and 7B are cross-sectional views taken along the line Vc-Vc' in FIG. 5A.

First, as shown in FIGS. 6A and 7A, the lower film 600 of chromium and the upper film 601 of Al-Nd are sequentially stacked, and then the photosensitive film 100 is applied thereon. The data wiring mask having the data line pattern 31b, the source and drain electrode pattern 31'b, and the data pad pattern 31 "b formed on the photoresist film 100 in the B region is aligned with the mask for the data region. The photosensitive film 100 is exposed and the area A is covered using the light shielding mask 31a so that light is not irradiated to the area A. At this time, the light shielding mask 31a covers the margin 35 "in addition to the alignment margin 35 '. The additional shading margin 35 is provided so as to cover a part of the B area beyond the boundary of the shot A area and the shot B area. Here, the alignment margin 35 ′ is about 2 μm, so the light shielding margin 35 is aligned to be 2 μm or more including the alignment margin 35 ′.

6B and 7B, the data wiring mask having the data line pattern 32a formed on the photosensitive film 100 of the shot A region is aligned to expose the photosensitive film 100 of the shot A region. , The B region is covered by the light shielding mask 32b so that light is not irradiated to the short B region.

Next, as shown in FIGS. 5B and 5C, the photoresist film 100 is developed to form photoresist patterns 110a, 110b, 120b, and 121b, and the photoresist patterns 110a, 110b, which are formed in the shot A and shot B regions. The lower layer 600 and the upper layer 601 are patterned by using the 120b and 121b as an etch mask to be connected to the data lines 62a and 62b and the data lines 62a and 62b that intersect the gate line 22. It is connected to the source electrode 65b extending to the upper part of the electrode 26, the drain electrode 66b facing the source electrode centering on the gate electrode 26, and the data lines 62a and 62b so that one end of the data pad ( A data wiring including 68b) is formed.

Next, the doped amorphous silicon layer pattern 50 which is not covered by the data wires 62a, 62b, 65b, 66b, and 68b is etched to separate the doped amorphous silicon layer on both sides of the gate electrode 26. The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform an oxygen plasma.

According to the method for forming the data wirings 62a, 62b, 65b, 66b, and 68b by using such a stepper exposure method, a light shielding mask that covers the shot A area when the light shielding mask 31a is aligned is formed in the exposure area shot. By arranging the shading margin 35 to cover a part, the data wiring photosensitive film pattern may be prevented from being double exposed at the boundary due to the instability of focusing due to the aging of the stepper photo equipment, thereby developing at the boundary. It is possible to prevent the data wiring photoresist pattern from shrinking later.

Next, as shown in FIGS. 8A and 8B, a protective film 70 made of silicon nitride or an organic insulating film is stacked, and the exposure is performed by dividing the light into the shot A region and the shot B region by using the pixel electrode as a boundary, and then performing a gate in a photolithography process. Gate pads 24, drain electrodes 66, and data pads formed through contact holes 74, 76, and 78 that expose the pads 24, the drain electrodes 66, and the data pads 68, respectively. Al-Nd layers 241, 661, and 681 of (68) are continuously removed by dry etching.

Next, as shown in FIGS. 8C and 8D, an indium tin oxide (ITO) or indium zinc oxide (IZO) film 80, which is a transparent conductive material, is deposited on the passivation layer 70, and is divided into shot A and shot B regions. Exposed to form photoresist patterns 130a, 130b, and 131b for pixel electrodes, photoresist pattern 140a for auxiliary gate pads, and photoresist pattern 140b for auxiliary data pads, and the transparent conductive layer 80 is etched using an etching mask. The pixel electrodes 82a and 82b, the auxiliary gate pad 86a and the auxiliary data pad 88b are formed. Even at this time, the pixel electrode photoresist patterns 130a, 130b, and 131b are double exposed at the boundary of the divided exposure region, and after development, the phenomenon that the pixel electrode photoresist patterns 130a, 130b and 131b are reduced is generated. In order to solve this problem, a method of forming the pixel electrode in the divided exposure area will be described in detail with reference to FIGS. 9A to 10B.

9A and 9B are cross-sectional views taken along the line 'b'-'b' 'in FIG. 8A, and FIGS. 10A and 10B are cross-sectional views taken along the line' C '-' C 'in FIG. 8A, and the pixel area boundary of the divided exposure area shot is shown. It is sectional drawing which shows the formation process of a pixel electrode, an auxiliary gate pad, and an auxiliary data pad as a boundary part.

9A and 10A, an indium tin oxide (ITO) or indium zinc oxide (IZO) film 80, which is a transparent conductive material, is deposited on the passivation layer 70, and the photoresist layer 100 is coated thereon. In order to expose the photoresist film 100 of the shot A region on the photoresist film 100, a mask in which the pixel electrode pattern 41a and the auxiliary gate pad pattern 41'a are formed is aligned to form a photoresist film of the shot A region ( 100 is exposed and the shot B area is covered using the light shielding mask 41b so that light is not irradiated to the shot B area. At this time, the light shielding mask 41b is disposed so as to cover up to a part of the shot B region by placing the light shielding margin 45 in which the margins 45 'are added in addition to the alignment margin 45' as in the data wiring forming step.

Next, as shown in FIGS. 9B and 10B, a mask in which the pixel electrode pattern 42b and the auxiliary data pad pattern 42'b are formed on the photosensitive film 100 of the shot B region is aligned and shot. The photosensitive film 100 of the region B is exposed, and the shot A region is covered using the light shielding mask 42a so that light is not irradiated to the shot A region.

8C and 8D, the photoresist patterns 130a, 130b, 131b, 140a, and 140b on which the photoresist 100 is developed are formed, and the photoresist patterns 130a and 130 are formed in the shot A and shot B regions. The transparent conductive film 80 is patterned using the 130b, 131b, 140a, and 140b as an etch mask to form the pixel electrodes 82a and 82b, the auxiliary gate pad 86a, and the auxiliary data pad 88b.

According to the method of forming a pixel electrode using such a stepper exposure method, when the light blocking mask 41a is aligned, the light blocking margin 35 is disposed so as to cover the light blocking mask covering the short A area to a part of the exposure area shot. This arrangement prevents double exposure of the pixel electrode photoresist pattern at the boundary due to instability of focusing due to aging of the photo equipment of the stepper, thereby preventing the photo wiring pattern for data wiring from shrinking after development at the boundary. have. Therefore, the stitch phenomenon which arises in the boundary part of divided exposure area | region shot can be prevented.

In the above, the boundary portion of the divided exposure region when forming the pixel electrode is the same as the boundary portion of the exposure region used when forming the gate wiring and the data wiring. However, as shown in FIGS. 11A and 11B, when forming the pixel electrode, the divided exposure boundary portion is made the same as the boundary portion of the divided exposure region of the gate wiring and the data wiring so that the photosensitive film patterns 130a, 130b, and 131b for the pixel electrode are formed on the exposure boundary portion. ), The shrinkage of the gate wiring photoresist pattern, the data wiring photoresist pattern, and the pixel electrode photoresist pattern is concentrated in one place due to instability of focusing due to aging of the optical equipment at the exposure boundary. In order to prevent such a phenomenon, the pixel electrodes 82a and 82b are formed to move the boundary portions of the divided exposures to the boundary portions of other pixel regions so as not to overlap the boundary portions of the gate lines and the data lines.

Next, a method of forming the pixel electrode will be described in detail with reference to FIGS. 12A to 13B.

12A and 12B are cross-sectional views taken along the line 'b'-'b' in Fig. 8A, and Figs. 13A and 13B are cross-sectional views taken along the line 'c'-'C' in Fig. 8A, and the boundary of the divided exposure area shot is another pixel area. It is sectional drawing which shows the formation process of a pixel electrode as a boundary part.

12A and 13A, an indium tin oxide (ITO) or indium zinc oxide (IZO) film 80 is deposited on the protective film 70, and a photosensitive film 100 is applied thereon. The pixel electrode pattern 51a and the auxiliary gate pad pattern 51'a are formed on the photoresist film 100 in the shot A region so that the boundary portion of the divided exposure region does not overlap with the boundary portion of the data line. The photomask film 100 of the shot A region is exposed by aligning the masks, and the shot B region is covered using the light shielding mask 51b so that light is not irradiated to the shot B region.

12B and 13B, the light is not irradiated to the shot A region by using the light shielding mask 52a disposed up to a part of the shot B region, and the pixel electrode disposed in the shot B region is used. The photosensitive film 100 is exposed using a mask on which the pattern 52b and the auxiliary data pad pattern 52'b are formed. At this time, the light shielding mask 52b is disposed so as to cover up to a part of the shot B region by placing the light shielding margin 55 in which the margins 55 'are added to the alignment margin 55' as in the data wiring forming step.

11A and 11B, the photoresist film 100 is developed to form a photoresist pattern, and the photoresist patterns 150a, 151a, 150b, 160a, and 160b formed in the shot A and shot B regions are etch masks. The transparent conductive film 80 is patterned to form the pixel electrodes 82a and 82b, the auxiliary gate pad 86a, and the auxiliary data pad 88b.

When the pixel electrode is formed, the boundary portion of the divided exposure region shot is moved to the boundary portion of another exposure region so as not to overlap the boundary portion of the gate wiring and the data wiring, so that the gate wiring, The reduction of the data wiring and the photosensitive film pattern for the pixel electrode can be prevented from being concentrated in one place.

As described above, according to the present invention, in the exposure process for forming the wiring, the light shielding mask is disposed with a light shielding margin larger than the alignment margin so that the wiring photoresist pattern is doubled at the boundary due to instability of focusing due to aging of the stepper photo equipment. Can be prevented from being exposed, thereby preventing the data wiring photoresist pattern from shrinking after development at the boundary portion. Further, when forming the pixel electrode, the pattern at the boundary due to instability of focusing due to aging of optical equipment is moved by moving the boundary of the divided exposure region to the boundary of another exposure region so as not to overlap the boundary of the gate wiring and the data wiring. Can be concentrated in one place. Thus, it is possible to prevent the unevenness of the entire screen on the photo mask without replacing the optical equipment.

Claims (4)

Forming a gate wiring including a gate line and a gate electrode, Forming a data line including a data line, a source electrode, and a drain electrode to insulate and cross the gate line to define a pixel area; A method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising the step of forming a pixel electrode connected to the drain electrode. At least one of the gate wiring, the data wiring, and the pixel electrode is formed by a photolithography process using a divisional exposure method in which a plurality of areas are divided and exposed. An exposure mask corresponding to an area to which light is irradiated and including a pattern of any one of the gate line, data line, and pixel electrode and a light blocking mask corresponding to an area where light is blocked and do not include the pattern may be divided and exposed. When the boundary line of the light blocking mask is disposed inside the boundary line of the exposure mask with a light blocking margin. In claim 1, The said light shielding margin is 2 micrometers or more, The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 1, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein a boundary portion of the exposure area is the same when the gate wiring, the data wiring, and the pixel electrode are formed. The method according to any one of claims 1 to 3, The method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the boundary of the exposure area is different when the gate wiring, the data wiring, and the pixel electrode are formed.

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