KR101320651B1 - Method of Fabricating Liquid Crystal Display Panel Of Horizontal Electronic Fileld Applying Type - Google Patents

Abstract

The present invention relates to a method for manufacturing a horizontal field applied liquid crystal display panel, wherein the forming of the pixel electrode includes forming a molybdenum alloy on a protective film; Forming a photoresist pattern on the molybdenum alloy; Patterning the molybdenum alloy by a dry etching process using the photoresist pattern as a mask; And removing the photoresist pattern by a dry strip process. The etching gas used in the dry etching process is any one of SF ₆ and CF ₄ , and the strip gas used in the dry strip process is a mixed gas of SF ₆ and O ₂ .

Description

Method for manufacturing horizontal field-applied liquid crystal display panel {Method of Fabricating Liquid Crystal Display Panel Of Horizontal Electronic Fileld Applying Type}

1 is a plan view illustrating a thin film transistor array substrate of a conventional horizontal field application liquid crystal display panel.

FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II ′ in FIG. 1.

3A through 3D are cross-sectional views illustrating a step of manufacturing a thin film transistor array substrate of the horizontal field application type liquid crystal display panel illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to a first embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the thin film transistor array substrate taken along the line II-II ′ of FIG. 4.

6A through 6D are cross-sectional views illustrating a step of manufacturing a thin film transistor array substrate of the horizontal field application type liquid crystal display panel illustrated in FIG. 5.

7A and 7B are cross-sectional views illustrating the steps of FIG. 6D in more detail.

      <Explanation of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10 source electrode 12, 112 drain electrode

14, 114: pixel electrodes 16, 116: common line

18, 118: common electrode 52, 152: protective film

46,146: gate insulating film 17, 117: first contact hole

27,127: second contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a method for manufacturing a horizontal field application type liquid crystal display panel, in which a contrast ratio can be improved and a rework process can be normally performed.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal display devices are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field application type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. . Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is as narrow as 90 degrees.

In the horizontal field application type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. Such a horizontal field application liquid crystal display device has an advantage that a viewing angle is about 160 degrees. Hereinafter, the horizontal field application liquid crystal display will be described in detail.

The horizontal field application type liquid crystal display device includes a thin film transistor array substrate (lower substrate) and a color filter array substrate (upper substrate) bonded to each other, a spacer for keeping a cell gap constant between the two substrates, and a spacer provided by the spacer. A liquid crystal filled in the liquid crystal space is provided.

The thin film transistor array substrate is composed of a plurality of signal lines and thin film transistors for forming a horizontal electric field in pixels, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

FIG. 1 is a plan view illustrating a thin film transistor array substrate of a conventional horizontal field applied liquid crystal display panel, and FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II ′ in FIG. 1.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect on the lower substrate 45, a thin film transistor 6 formed at each intersection thereof, and an intersection thereof. A pixel electrode 14 and a common electrode 18 formed to form a horizontal electric field in the pixel region 5 having a structure, and a common line 16 to which the common electrodes 18 are commonly connected are provided.

The gate line 2 supplies a gate signal to the gate electrode 8 of the thin film transistor 6. The data line 4 supplies the pixel signal to the pixel electrode 14 through the drain electrode 12 of the thin film transistor 6. The gate line 2 and the data line 4 are formed in an intersecting structure to define the pixel region 5.

The common line 16 is formed in parallel with the gate line 2 with the pixel region 5 therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 18.

The thin film transistor 6 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 14 in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 includes a semiconductor layer including an active layer 48 overlapping with the gate electrode 8 and the gate insulating layer 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12. The pattern 49 is further provided. The semiconductor pattern 49 further includes an ohmic contact layer 50 positioned on the active layer 48 to make ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12.

The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 17. The pixel electrode 14 is connected to the drain electrode 12 and has a horizontal portion 14a formed in parallel with the adjacent gate line 2, and a finger portion extended from the horizontal portion 14a to be parallel to the common electrode 18. (14b).

The common electrode 18 is connected to the common line 16 through the second contact hole 27 through the gate insulating layer 146 and the passivation layer 152 to expose the common line 116. The common electrode 118 is formed of the same material as the pixel electrode 14 at the same time.

The common electrode 18 may be connected to the common line 16 to be formed of the same metal as the gate line 2 and the gate electrode 8 in the pixel region 5.

In the horizontal field application type liquid crystal display panel having the above-described structure, the pixel electrode 14 supplied with the pixel signal through the thin film transistor 6 and the common electrode 18 supplied with the reference voltage through the common line 16 are provided. A horizontal electric field is formed. In particular, a horizontal electric field is formed between the finger portion 14b of the pixel electrode 14 and the common electrode 18. This horizontal electric field causes the liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate due to the dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region 5 is changed, thereby realizing an image.

Hereinafter, a method of manufacturing a thin film transistor array substrate of a conventional horizontal electric field type liquid crystal display panel will be described with reference to FIGS. 1 and 3A to 3D.

Referring to FIG. 3A, a gate pattern formed by the first mask process is formed.

After the gate metal layer is formed on the lower substrate 45 through a deposition method such as sputtering, the gate metal layer is patterned by a photolithography process and an etching process using a mask. As a result, a gate pattern including the gate electrode 8, the gate line 2, and the common line 16 is formed. As the gate metal, an aluminum alloy such as chromium (Cr) or aluminum neodium (AlNd) is used.

Referring to FIG. 3B, a semiconductor pattern 49 and a source / drain pattern are formed by a second mask process.

In detail, the gate insulating layer 46 is formed by depositing an entire surface of the inorganic insulating material on the lower substrate 45 having the gate pattern through a deposition method such as PECVD. Here, as the material of the gate insulating film 46, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

On the lower substrate 45 on which the gate insulating layer 46 is formed, an amorphous silicon layer, an n + amorphous silicon layer, and a source / drain metal layer are sequentially formed by a deposition method such as PECVD or sputtering. As the source / drain metal, copper (Cu) having high conductivity is used.

Thereafter, a photoresist pattern is formed by a photolithography process using a second mask. In this case, the photoresist pattern of the channel portion has a lower height than the source / drain pattern portion by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the source / drain includes the data line 4, the source electrode 10, and the drain electrode 12 integrated with the source electrode 10. Patterns are formed.

Then, the ohmic contact layer 50 and the active layer 48 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

Then, the photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 50 of the channel portion are etched by a dry etching process. Accordingly, the active layer 48 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12. As a result, the thin film transistor 6 including the gate electrode 8, the semiconductor pattern 49, the source electrode 10, and the drain electrode 12 is formed.

Then, the photoresist pattern remaining on the source / drain pattern portion in the strip process is removed.

Referring to FIG. 3C, after the insulating material is deposited on the lower substrate 45 on which the source / drain pattern and the semiconductor pattern 49 are formed, the insulating material is patterned by a photolithography process and an etching process using a third mask. The protective film 52 including the first and second contact holes 17 and 27 is formed.

The first contact hole 17 penetrates the passivation layer 52 to expose the drain electrode 12 of the thin film transistor 6, and the second contact hole 27 penetrates the passivation layer 52 and the gate insulating layer 46. To expose the common line 16.

Here, as the material of the protective film 152, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

Referring to FIG. 3D, the pixel electrode 14 and the common electrode 18 are formed on the passivation layer 52.

After the transparent electrode material is deposited on the lower substrate 45 on which the passivation layer 52 is formed by a deposition method such as sputtering, a photoresist pattern is formed by a photolithography process using a fourth mask.

Thereafter, an etching process using the photoresist pattern as a mask is performed to form the pixel electrode 14 contacting the drain electrode 12 of the thin film transistor 6 through the first contact hole 17. At the same time, the common electrode 18 contacting the common line 16 through the second contact hole 27 is formed.

The pixel electrode 14 is in contact with the drain electrode 14 and extends from the horizontal portion 14a parallel to the gate line 2, the common line 16, and the horizontal portion 14a and is parallel to the common electrode 18. Denial 14b.

The material of the transparent electrode pattern is indium tin oxide (hereinafter referred to as "ITO"), tin oxide (hereinafter referred to as "TO"), and indium zinc oxide (hereinafter referred to as "IZO"). Or indium tin zinc oxide (hereinafter referred to as "ITZO").

The contrast ratio of the horizontal field application type liquid crystal display panel formed by the above-described manufacturing method depends on black rather than white. Therefore, research is being conducted to improve the overall contrast ratio by improving black implementation rather than white.

In addition, ITO, which is a material of the common electrode 18 and the pixel electrode 14, is a material having low conductivity, and thus has a disadvantage in that the horizontal electric field force is somewhat decreased.

The present invention provides a method of manufacturing a horizontal field application type liquid crystal display panel in which a contrast ratio can be improved and a rework process can be normally performed.

A method of manufacturing a horizontal field application type liquid crystal display panel according to an exemplary embodiment of the present invention includes forming a gate pattern including a gate line and a common line parallel to the gate line on a substrate; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode; Forming a protective film having a first contact hole exposing the drain electrode; And forming a pixel electrode made of molybdenum alloy and in contact with the drain electrode through the first contact hole.
The forming of the pixel electrode may include forming the molybdenum alloy on the passivation layer; Forming a photoresist pattern on the molybdenum alloy; Patterning the molybdenum alloy by a dry etching process using the photoresist pattern as a mask; And removing the photoresist pattern by a dry strip process.
The etching gas used in the dry etching process is any one of SF ₆ and CF ₄ , and the strip gas used in the dry strip process is a mixed gas of SF ₆ and O ₂ .

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Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7B.

4 is a plan view illustrating a thin film transistor array substrate of a horizontal field applied liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II-II ′ of FIG. 4. .

The thin film transistor array substrate shown in FIGS. 4 and 5 has a gate line 102 and a data line 104 formed to intersect on the lower substrate 145, a thin film transistor 106 formed at each intersection thereof, and a cross structure thereof. A pixel electrode 114 and a common electrode 118 formed to form a horizontal electric field in the pixel region 105 provided as a second electrode, and a common line 116 to which the common electrodes 118 are commonly connected.

The gate line 102 supplies a gate signal to the gate electrode 108 of the thin film transistor 106. The data line 104 supplies a pixel signal to the pixel electrode 114 through the drain electrode 112 of the thin film transistor 106. The gate line 102 and the data line 104 are formed in an intersecting structure to define the pixel region 105.

The common line 116 is formed in parallel with the gate line 102 with the pixel region 105 interposed therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 118.

The thin film transistor 106 keeps the pixel signal of the data line 104 charged and held in the pixel electrode 114 in response to the gate signal of the gate line 102. To this end, the thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode connected to the pixel electrode 114. 112). In addition, the thin film transistor 106 includes a semiconductor including an active layer 148 overlapping with the gate electrode 108 and the gate insulating layer 146 therebetween to form a channel between the source electrode 110 and the drain electrode 112. The pattern 149 is further provided. The semiconductor pattern 149 further includes an ohmic contact layer 150 positioned on the active layer 148 and for ohmic contact with the data line 104, the source electrode 110, and the drain electrode 112.

The pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor 106 through the first contact hole 117. The pixel electrode 114 is connected to the drain electrode 112 and is formed in parallel with the adjacent gate line 102, and a finger part extended from the horizontal part 114a and formed in parallel with the common electrode 18. 114b.

The common electrode 118 is connected to the common line 116 through the second contact hole 127 through the gate insulating layer 146 and the passivation layer 152 to expose the common line 116. The common electrode 118 is simultaneously formed of the same material as the pixel electrode 114.

The pixel electrode 114 and the common electrode 118 are formed of an opaque conductive material. Accordingly, it is possible to improve the black implementation characteristics, thereby improving the overall contrast ratio.

In more detail, in the horizontal field application type liquid crystal display panel, even if the common electrode and the pixel electrode are formed of a transparent electrode material such as ITO, all of the common electrode 18 and the pixel electrode 14 in the pixel region 5 are formed. As it is positioned, the aperture ratio is reduced. Therefore, even if the pixel electrode 114 and the common electrode 118 are formed of an opaque conductive material, the white luminance is not significantly reduced as compared with the conventional art.

On the other hand, when the pixel electrode 114 and the common electrode 118 are formed of an opaque conductive material, light leakage and the like do not appear when the black is implemented, and thus the black implementation characteristic may be improved. As a result, the overall contrast ratio can be improved.

In addition, a molybdenum alloy (Mo alloy) is used as the opaque conductive material. For example, tungsten (W), zirconium (Zr), titanium (Ti), neodium (Nd), nitride (Nx), and the like may be added to molybdenum (Mo).

In particular, molybdenum (Mo) has improved conductivity than ITO, thereby improving the horizontal electric field force between the common electrode and the pixel electrode.

Hereinafter, a method of manufacturing a thin film transistor array substrate of a conventional horizontal field application type liquid crystal display panel will be described with reference to FIGS. 4 and 6A to 7B.

Referring to FIG. 6A, a gate pattern formed by the first mask process is formed.

After the gate metal layer is formed on the lower substrate 145 through a deposition method such as sputtering, the gate metal layer is patterned by a photolithography process and an etching process using a mask. As a result, a gate pattern including the gate electrode 108, the gate line 102, and the common line 116 is formed. As the gate metal, an aluminum alloy such as chromium (Cr) or aluminum neodium (AlNd) is used.

Referring to FIG. 6B, a semiconductor pattern 149 and a source / drain pattern are formed by a second mask process.

Specifically, the gate insulating film 146 is formed by depositing an entire surface of the inorganic insulating material on the lower substrate 145 on which the gate pattern is formed by a deposition method such as PECVD. Here, as the material of the gate insulating film 146, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

On the lower substrate 145 on which the gate insulating layer 146 is formed, an amorphous silicon layer, an n + amorphous silicon layer, and a source / drain metal layer are sequentially formed by a deposition method such as PECVD or sputtering. As the source / drain metal, copper (Cu) having high conductivity is used.

Thereafter, a photoresist pattern is formed by a photolithography process using a second mask. In this case, the photoresist pattern 71b of the channel portion has a lower height than the source / drain pattern portion by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the source / drain includes a data line 104, a source electrode 110, and a drain electrode 112 integrated with the source electrode 110. Patterns are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 150 and the active layer 148.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 150 are etched by the dry etching process. Accordingly, the active layer 148 of the channel part is exposed to separate the source electrode 110 and the drain electrode 112. Accordingly, the thin film transistor 106 including the gate electrode 108, the semiconductor pattern 149, the source electrode 110, and the drain electrode 112 is formed.

Then, the photoresist pattern remaining on the source / drain pattern portion in the strip process is removed.

Referring to FIG. 6C, after the insulating material is deposited on the lower substrate 145 on which the source / drain pattern and the semiconductor pattern 149 are formed, the insulating material is patterned by a photolithography process and an etching process using a third mask. The passivation layer 152 including the first and second contact holes 117 and 127 is formed.

The first contact hole 117 penetrates the passivation layer 152 to expose the drain electrode 112 of the thin film transistor 106, and the second contact hole 127 penetrates the passivation layer 152 and the gate insulating layer 146. To expose the common line 116.

Here, as the material of the protective film 152, silicon nitride (SiNx), silicon oxide (SiOx), or the like, which is an inorganic insulating material, is used.

Referring to FIG. 6D, a pixel electrode 114 and a common electrode 118 of an opaque material are formed on the passivation layer 152.

After the opaque electrode material is deposited on the lower substrate 145 on which the passivation layer 152 is formed by sputtering or the like, a photoresist pattern is formed by a photolithography process using a fourth mask. As the opaque conductive material, molybdenum alloy (Mo alloy) is used. For example, tungsten (W), zirconium (Zr), titanium (Ti), neodium (Nd), nitride (Nx), and the like may be added to molybdenum (Mo).

Thereafter, as shown in FIG. 7A, a dry etch process using the photoresist pattern 180 as a mask is performed.

Here, the opaque conductive material 118a is SF ₆ , CF ₄ It is patterned by the dry etching process using the etching gas, such as these. If the opaque conductive material 118a is patterned using a wet etching process, the source / drain pattern made of copper (Cu) may be damaged by the etching solution. That is, the etchant penetrates into the source / drain metal, thereby damaging the data line, the source electrode, and the drain electrode.

Then, SF ₆ as shown in Figure 7b With O ₂ plasma or by using a mixed gas of O ₂ The strip process using plasma is performed. O ₂ even in the strip process Dry strip processes using plasma or the like should be carried out. If the wet strip process is performed, the source / drain pattern made of copper (Cu) is damaged by the strip liquid.

Accordingly, as the photoresist pattern 180 is removed, the common line 116 through the pixel electrode 114 and the second contact hole 127 contacting the drain electrode 112 through the first contact hole 117. A common electrode 118 is formed in contact with the. The pixel electrode 114 is in contact with the drain electrode 114 and extends in the horizontal portion 114a parallel to the gate line 102, the common line 116, and the horizontal portion 114a and parallel to the common electrode 118. A finger portion 114b is located.

As described above, in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention, only the dry etching process is performed instead of the wet etching process in the fourth mask process, thereby protecting the source / drain patterns made of copper (Cu). do.

On the other hand, in the process of forming the pixel electrode 114 or the like by the fourth mask process, when the process deviation or defect occurs, the pixel electrode 114 is formed again after removing the formed pixel electrode 114 or the like. A rework process is performed.

In this case, the pixel electrode 114, which is abnormally formed by the dry etching process, is removed. Accordingly, damage to the source / drain pattern made of copper (Cu) can be prevented.

In the present invention, only the case in which the common electrode 118 is formed on the passivation layer 52 and simultaneously formed of the same material as the pixel electrode 114 is shown. However, the common electrode 118 may be formed at the same time when the gate pattern is formed of a gate metal such as the gate electrode 108 and the common line 116.

As described above, the structure and manufacturing method for forming the pixel electrode from a highly conductive opaque metal material are also used in a fringe field switching (FFS) type liquid crystal display device operated by a fringe field. Can be.

As described above, in the method of manufacturing the horizontal field application type liquid crystal display panel according to the present invention, the pixel electrode is formed of an opaque metal material having high conductivity. Accordingly, the black implementation characteristic can be improved, thereby improving the overall contrast ratio and improving the horizontal electric field force between the common electrode and the pixel electrode.

In addition, in the method of manufacturing a horizontal field application type liquid crystal display panel according to the present invention, the thin film is patterned by a dry etching process rather than a wet etching process in the fourth mask process. Accordingly, the source / drain pattern formed of copper or the like can be protected, and the rework process can be normally performed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (12)

delete delete delete delete delete Forming a gate pattern including a gate line and a common line parallel to the gate line on the substrate; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode; Forming a passivation layer having a first contact hole exposing the drain electrode; And Forming a pixel electrode made of molybdenum alloy and in contact with the drain electrode through the first contact hole; Forming the pixel electrode Forming the molybdenum alloy on the protective film; Forming a photoresist pattern on the molybdenum alloy; Patterning the molybdenum alloy by a dry etching process using the photoresist pattern as a mask; And Removing the photoresist pattern by a dry strip process, The etching gas used in the dry etching process is any one of SF ₆ and CF ₄ , And a strip gas used in the dry strip process is a mixed gas of SF ₆ and O ₂ . The method of claim 6, Forming the pixel electrode And forming a common electrode in contact with the common line through a second contact hole through the gate insulating layer and the passivation layer to expose the common line. The method of claim 6, Forming the gate pattern And forming a common electrode connected to the common line and forming a horizontal electric field with the pixel electrode. delete delete delete The method of claim 6, And the source / drain pattern comprises copper (Cu).

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