KR101236511B1 - Thin Film Transistor Substrate Of Horizontal Electronic Fileld and Method of Fabricating the same - Google Patents

Abstract

The present invention relates to a horizontal field type thin film transistor substrate and a method of manufacturing the same, the thin film transistor substrate comprising: a gate line and a common line formed in parallel on the substrate; A data line intersecting the gate line with a first insulating layer interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A second insulating layer formed on the first insulating layer and covering the thin film transistor; A pixel electrode connected to the thin film transistor through the second insulating layer; A common electrode connected to the common line through the first insulating layer and the second insulating layer and formed in parallel with the pixel electrode to form a horizontal electric field; And a storage capacitor formed by the gate line and the pixel electrode overlapping each other with the first insulating layer and the second insulating layer interposed therebetween. Each of the pixel electrode and the common electrode includes Ti or a Ti alloy.

Description

Thin Film Transistor Substrate Of Horizontal Electronic Fileld and Method of Fabricating the same

1 is a plan view illustrating a conventional horizontal field type thin film transistor substrate.

FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate taken along line II ′ in FIG. 1.

3 is a view for explaining a light leakage phenomenon generated in the pixel region of a conventional thin film transistor substrate.

4 is a view for explaining the non-uniform line width generated in the pixel electrode and the common electrode of a conventional thin film transistor substrate.

5A through 5E are process diagrams for explaining a process of forming a pixel electrode and a common electrode having non-uniform line widths of FIG. 4;

6 is a plan view illustrating a horizontal field type thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a thin film transistor substrate taken along lines II-II ′, III-III ′, and IV-IV ′ in FIG. 6.

8 is a view illustrating a pixel region in which light leakage is not generated in a thin film transistor substrate according to the present invention.

9 illustrates a pixel electrode and a common electrode having a uniform line width in the thin film transistor substrate according to the present invention.

10A through 10E are process diagrams illustrating a process of forming a pixel electrode and a common electrode having a uniform line width of FIG. 9;

11A and 11B are a plan view and a cross-sectional view of a thin film transistor substrate on which a first conductive pattern is formed according to the present invention.

12A and 12B are a plan view and a cross-sectional view of a thin film transistor substrate having a second conductive pattern according to the present invention.

13A to 13F are manufacturing process diagrams of a thin film transistor substrate having a second conductive pattern according to the present invention.

14A and 14B are a plan view and a cross-sectional view of a thin film transistor substrate having a protective film according to the present invention.

15A and 15B are a plan view and a cross-sectional view of a thin film transistor substrate having a third conductive pattern according to the present invention.

         <Explanation of symbols for the main parts of the drawings>

100: lower substrate 110: gate line

111 gate electrode 120 common line

121: common electrode 130: gate insulating film

140: data line 141: source electrode

142: drain electrode 143: active layer

144: ohmic contact layer 150: thin film transistor

160: protective film 161: first contact hole

162: second contact hole 163: third contact hole

164: fourth contact hole 170: pixel electrode

170a: horizontal portion 170b: finger portion

180: common electrode

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal display devices are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. The vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In a horizontal field type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field type liquid crystal display device has an advantage that a viewing angle is about 160 degrees.

Hereinafter, a thin film transistor substrate constituting a conventional horizontal field type liquid crystal display device will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a plan view illustrating a thin film transistor substrate of a conventional horizontal field application type liquid crystal display panel, and FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate taken along line II ′ in FIG. 1.

As shown in FIGS. 1 and 2, a conventional thin film transistor substrate includes a gate line 2 and a data line 4 intersected on the lower substrate 1, and a thin film transistor 30 formed at each intersection thereof. And a pixel electrode 22 and a common electrode 24 formed to form a horizontal electric field in the pixel region provided in a cross-sectional structure thereof, and a common line 26 to which the common electrodes 24 are commonly connected.

The gate line 2 transfers a gate signal supplied from a gate driver (not shown) connected to the gate pad to the gate electrode 6 constituting the thin film transistor 30.

The data line 4 transfers a data signal supplied from a data driver (not shown) connected to the data pad to the pixel electrode 22 through the drain electrode 10 constituting the thin film transistor 30. .

In this case, the gate line 2 and the data line 4 are formed in an intersecting structure to define the pixel region 5.

The common line 26 is formed in parallel with the gate line 2 with the pixel region 5 interposed therebetween, and supplies a common voltage Vcom, which is a reference voltage, to the common electrode 24.

The thin film transistor 30 switches so that the pixel signal of the data line 4 is charged to the pixel electrode 22 in response to the gate signal of the gate line 2. The thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. Equipped. In addition, the thin film transistor 30 includes a semiconductor including an active layer 14 overlapping with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 10. The layer is further provided.

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The semiconductor layer further includes an ohmic contact layer 16 positioned on the active layer 14 and for ohmic contact with the data line 4, the source electrode 8, and the drain electrode 10.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the contact hole 20 and is formed in the pixel region 5. In particular, the pixel electrode 22 is connected to the drain electrode 10 and has a horizontal portion 22a formed in parallel with the adjacent gate line 2 and a common electrode connected to the common line 26 at the horizontal portion 22a. And a finger portion 22b that protrudes in parallel to 24 to form a horizontal electric field.

The common electrode 24 is connected to the common line 26 through the gate insulating layer 12 and the passivation layer 18, and is formed in parallel with the finger portion 22b of the pixel electrode 22 to form a horizontal electric field. The common electrode 24 is formed of the same transparent conductive film as the finger portion 22b of the pixel electrode 22 formed in the pixel region 5.

Liquid crystal between the finger portion 22b of the pixel electrode 22 through which the pixel signal is supplied through the drain electrode 10 of the thin film transistor 30 and the common electrode 24 through which the reference voltage is supplied through the common line 26. A horizontal electric field is formed for orientation.

As described above, as the horizontal electric field is formed between the finger portion 22b of the pixel electrode 22 and the common electrode 24, the liquid crystal molecules oriented in the horizontal direction in the pixel region 5 are formed in a predetermined direction by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing an image.

In the conventional thin film transistor substrate, the pixel electrode 22 and the common electrode 24 formed in the pixel region 5 may be a transparent conductive film, more specifically, indium tin oxide (ITO) or tin oxide (Tin Oxide). : TO), Indium Zinc Oxide (IZO) or Indium Tin Zinc Oxide (ITZO).

When light is incident through the backlight formed on the rear surface of the thin film transistor, as shown in FIG. 3, light leakage occurs through the pixel electrode 22 or 22b and the common electrode 24, which are regions other than the opening formed in the pixel region 5. There was a problem that the phenomenon occurs and the contrast ratio (contrast ratio) is lowered.

In the conventional thin film transistor substrate, the pixel electrode and the common electrode are made of a transparent conductive film (ITO) and an alloy thereof having a high resistance value of about 129 cm ² Ω, thereby lowering the electrical conductivity of the pixel electrode and the common electrode. Had a problem.

In the case of performing a photolithography process on a transparent conductive film to form a pixel electrode and a common electrode of a conventional thin film transistor substrate, UV light diffused from a vacuum chuck fixing a glass substrate is formed on a transparent conductive film. Upon exposure again, a photoresist pattern having a non-uniform size was formed.

In the case of forming the pixel electrode and the common electrode by etching the transparent conductive film exposed by the photoresist pattern having a non-uniform size, as shown in FIG. 4, the pixel electrode and the common electrode are nonuniform unlike the pattern formed in the mask. There was a problem of having a critical depth (CD).

More specifically, as shown in FIG. 5A, the pixel electrode and the common electrode are formed in the state where the gate insulating film 12 and the protective film 18 are formed on the glass substrate 1 fixed by the vacuum chuck. A transparent conductive film ITO is formed.

Subsequently, as shown in FIG. 5B, the photoresist PR is coated on the transparent conductive film ITO, and then the photoresist is exposed using a mask having a predetermined circuit pattern.

In this case, as shown in FIG. 5C, the UV light penetrating the glass substrate 1 is reflected by the vacuum chuck to expose the portion (a) which should not be exposed in the photoresist.

As described above, as the development process for the photoresist is performed in the state where the photoresist is exposed by the UV light reflected from the vacuum chuck as described above, as shown in FIG. 5D, the liner does not have a uniform line width on the transparent conductive film. Photoresist pattern is formed.

Subsequently, when the wet etching process is performed on the transparent conductive film exposed through the photoresist pattern, as shown in FIG. 5E, the common electrode 24 and the pixel electrode having a non-uniform critical width (CD) are formed. 22b) is formed, and thus, the voltage applied between the common electrode 24 and the pixel electrode 22b becomes uneven, so that a uniform horizontal electric field cannot be formed in the pixel region 5.

The present invention provides a horizontal field type thin film transistor substrate having a good contrast ratio, electrical conductivity and corrosion resistance, and a method of manufacturing the same.

The thin film transistor substrate of the present invention includes a gate line and a common line formed in parallel on the substrate; A data line intersecting the gate line with a first insulating layer interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A second insulating layer formed on the first insulating layer and covering the thin film transistor; A pixel electrode connected to the thin film transistor through the second insulating layer; A common electrode connected to the common line through the first insulating layer and the second insulating layer and formed in parallel with the pixel electrode to form a horizontal electric field; A storage capacitor formed by the gate line and the pixel electrode overlapping each other with the first insulating layer and the second insulating layer interposed therebetween; A gate pad connected to the gate line; And a data pad connected to the data line.
The gate pad may include a gate pad lower electrode connected to the gate line, a gate contact hole penetrating the second insulating layer and the first insulating layer to expose the gate pad lower electrode, and the gate pad through the gate contact hole. And a gate pad upper electrode connected to the lower electrode.
The data pad includes a data pad lower electrode connected to the data line, a data contact hole penetrating the second insulating layer to expose the data pad lower electrode, and a data pad lower electrode connected to the data pad lower electrode. And a data pad upper electrode.
Each of the pixel electrode, the common electrode, the gate pad upper electrode, and the data pad upper electrode includes Ti or a Ti alloy.
In the method of manufacturing the thin film transistor substrate, after forming a first conductive pattern including a gate line, a common line, and a gate electrode of the thin film transistor connected to the gate line, a first insulating layer covering the first conductive pattern Forming a; A semiconductor layer of the thin film transistor, the data line intersecting the gate line with the first insulating layer interposed therebetween, a source electrode of the thin film transistor connected to the data line, and a drain electrode of the thin film transistor; Forming a second conductive pattern; Forming a second insulating layer on the first insulating layer to cover the second conductive pattern and the thin film transistor; A pixel electrode penetrating the second insulating layer and connected to the drain electrode of the thin film transistor is formed, and the gate line and the pixel electrode are overlapped with each other with the first insulating layer and the second insulating layer interposed therebetween. Forming a capacitor; And forming a common electrode connected to the common line through the first insulating layer and the second insulating layer and formed in parallel with the pixel electrode to form a horizontal electric field.

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Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, the structure and operation of the horizontal field type thin film transistor substrate according to the present invention will be described with reference to FIGS. 6 and 7.

6 is a plan view illustrating a thin film transistor substrate of a horizontal field type liquid crystal display panel according to the present invention, and FIG. 7 is a thin film taken along lines II-II ', III-III', and IV-IV 'of FIG. 6. A cross-sectional view showing a transistor substrate.

6 and 7, the horizontal field type thin film transistor substrate according to the present invention includes a gate line 110 formed on the substrate 100, a common line 120 formed in parallel with the gate line 110, A data line 140 and a gate line 110 intersecting with the gate line 110 and the common line 120 with the gate insulating layer 130 serving as the first insulating layer to define the pixel region 171. The thin film transistor 150 formed at the intersection of the data line 140, the passivation layer 160 formed on the gate insulating layer and covering the thin film transistor 150, and the gate insulating layer 130 and the passivation layer 160. ), The common electrode 121 connected to the common line 120 and the pixel electrode 170, the gate line 110, and the pixel electrode 170 connected to the thin film transistor 150 through the passivation layer 160. It includes a storage capacitor 180 formed in the overlapping portion of.

The thin film transistor substrate according to the present invention further includes a gate pad 190 connected to the gate line 110 and a data pad 195 connected to the data line 140.

Here, the gate line 110 transmits a gate signal supplied from a gate driver (not shown) connected to the gate pad 190 to the gate electrode 111 constituting the thin film transistor 150.

The common line 120 is formed at the same time as the gate line 110 on the substrate 100 and transfers a reference voltage supplied through a common pad (not shown) to the common electrode 121. The common electrode 121 is connected to the common line 120 through the fourth contact hole 164 penetrating the gate insulating layer 130 and the passivation layer 160.

The common electrode 121 protrudes from the common line 120 and is formed in parallel with the finger portions 170b between the finger portions 170b of the pixel electrode 170, and a reference voltage is supplied from the common line 120. Accordingly, a horizontal electric field is generated in the pixel region 171 together with the finger portion 170b of the pixel electrode 170 formed in parallel on the passivation layer 160.

The data line 140 connects a data signal supplied from a data driver (not shown) connected to the data pad 195 to on / off of the gate electrode 111 to form the source electrode 141 constituting the thin film transistor 150. ) And the drain electrode 142.

The gate line 110 and the data line 140 are formed in a cross structure on the lower substrate 100 via the gate insulating layer 130 to define a pixel region 171 in which the pixel electrode 170 is located.

The thin film transistor 150 charges the pixel electrode 170 of the data line to the pixel electrode 170 in response to the gate signal of the gate line 110, and the gate electrode 111 connected to the gate line 110. The source electrode 141 and the channel connected to the data line 140 face the source electrode 141 with the channel interposed therebetween, and the drain electrode 142 connected to the pixel electrode 170 through the first contact hole 161. ).

The thin film transistor 150 includes an active layer 143 and an active layer 143 overlapping each other with the gate electrode 111 and the gate insulating layer 130 interposed therebetween, and forming a channel between the source electrode 141 and the drain electrode 142. And an ohmic contact layer 144 for ohmic contact with the data line 140, the source electrode 141, and the drain electrode 142.

A passivation layer 160 is formed on the gate insulating layer 130 to generate an active layer 143 and a pixel region 171 which form a channel of the thin film transistor 150 in a subsequent process, for example, It serves to protect from moisture or scratches. The passivation layer 160 may be formed of an inorganic insulating material such as silicon nitride, or an organic insulating material such as acryl-based organic compound, BCB (benzocyclobutene), or PFCB (perfluorocyclobutane), for example, deposition temperature, RF power, and gas flow rate. Under the conditions, it is deposited on the gate insulating film 130 by PECVD.

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The passivation layer 160 has a first contact hole 161 for exposing the drain electrode 142 of the thin film transistor 150 and a second contact hole (or gate) for exposing the lower electrode 191 of the gate pad 190. The fourth contact hole 164 for exposing the third contact hole (or data contact hole 163) and the common line 120 to expose the contact hole 162 and the lower electrode 196 of the data pad 195. Is formed.

The pixel electrode 170 is connected to the drain electrode 142 of the thin film transistor 150 through the first contact hole 161 penetrating the passivation layer 160. The pixel electrode 170 is formed on the passivation layer 160 by overlapping with the gate line 110 and formed in parallel with the horizontal portion 170a, and protrudes from the horizontal portion 170a to be parallel to the common electrode 121. A finger portion 170b for generating a horizontal electric field is provided at 171. The horizontal portion 170a of the pixel electrode 170 overlaps the gate line 110 with the gate insulating layer 130 and the passivation layer 160 therebetween to form the storage capacitor 180.

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The pixel electrode 170 and the common electrode 121 constituting the thin film transistor substrate according to the present invention are composed of an opaque conductive film having low electrical resistance and corrosion resistance, for example, an opaque conductive film formed of Ti or Ti alloy. do.

As described above, by forming the pixel electrode and the common electrode constituting the thin film transistor substrate according to the present invention using an opaque conductive film, as shown in FIG. 8, the pixel electrode 170b and the common except for the opening of the pixel region are shown. The light leakage phenomenon generated through the electrode 121 may be prevented to obtain a high contrast ratio for the LCD screen.

The pixel electrode and the common electrode is formed of a non-transparent conductive film, the resistance value having a lower resistance of about ² Ω 60㎝ 100㎝ ~ ² Ω has a high electrical conductivity.

As the opaque conductive film blocks UV light that is diffusely reflected from the vacuum chuck fixing the glass substrate 100 to form a photoresist pattern having a uniform line width, as shown in FIG. 9, the pixel electrode 170b and the common electrode ( 121 has a uniform line width (CD).

More specifically, as illustrated in FIG. 10A, the pixel electrode 170 and the common electrode 121 are formed on the substrate 100 fixed by the vacuum chuck with the gate insulating layer 130 and the protective layer 160 formed thereon. An opaque conductive film is formed to form). Subsequently, as shown in FIG. 10B, the photoresist is coated on the opaque conductive film, and then the photoresist is exposed and developed using a mask having a predetermined circuit pattern.

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As shown in FIG. 10C, the opaque conductive film blocks UV light reflected by the vacuum chuck from UV light passing through the substrate 100 to prevent the photoresist from being exposed again. Therefore, as the development process is performed in a state where the photoresist formed on the opaque conductive film is patterned in the same shape as the pattern formed on the mask, as shown in FIG. 10D, the photoresist pattern having a uniform line width on the opaque conductive film Is formed.

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Subsequently, by performing a wet etching process on the opaque conductive film exposed through the photoresist pattern, a common electrode 121 and a pixel electrode 170 having a uniform line width are formed as shown in FIG. 10E.

The storage capacitor 180 is formed by the gate line 110 and the horizontal portion 170a of the pixel electrode 170 overlapping each other with the gate insulating layer 130 and the passivation layer 160 interposed therebetween. The storage capacitor 180 serves to stably maintain the pixel signal charged in the pixel electrode 170 until the next pixel signal is charged, and is preferably designed to have a large capacitance value.

The gate pad 190 is connected to a gate driver (not shown) and supplies a gate signal to the gate line 110. The gate pad 190 extends from the gate line 110 to be connected to an end of the gate line 110. 191 and the gate pad upper electrode 192 connected to the gate pad lower electrode 191 through the second contact hole 162 penetrating through the gate insulating layer 130 and the passivation layer 160.

The gate pad upper electrode 192 is formed of an opaque conductive film composed of Ti or a Ti alloy having excellent electrical conductivity and corrosion resistance, and thus is not corroded or eroded by moisture present in the air, and is formed with the output terminal of the gate driver. Reduce contact resistance

The data pad 195 is connected to a data driver (not shown) and supplies a data signal to the data line 140. The data pad 195 extends from the data line 140 and the passivation layer 160. The data pad upper electrode 196 is connected to the data pad lower electrode 196 through a third contact hole 163 penetrating the gap.

The data pad upper electrode 196 is formed of an opaque conductive film made of Ti or a Ti alloy having excellent electrical conductivity and corrosion resistance, so that the data pad upper electrode 196 is not corroded or eroded by moisture present in the air, and has an output terminal of the data driver. Reduce contact resistance

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

A process of forming the first conductive pattern of the thin film transistor substrate according to the present invention will be described with reference to FIGS. 11A and 11B. 11A and 11B are a plan view and a cross-sectional view illustrating a method of manufacturing a first conductive pattern of a thin film transistor substrate according to the present invention.

11A and 11B, a gate line 110, a gate electrode 111, a gate pad lower electrode 191, and a common line 120 are included on a lower substrate 100 using a first mask process. A first conductive pattern is formed.

In detail, the gate metal layer is formed on the substrate 100 through a deposition method such as sputtering. The gate metal layer is composed of at least one metal of aluminum (Al) -based metal, copper (Cu), chromium (Cr), and molybdenum (Mo).

By patterning the gate metal layer through a photolithography process and an etching process using a first mask, the gate electrode 110 and the gate pad lower electrode connected to the gate line 110 and the gate line 110 on the lower substrate 100. A first conductive pattern including the 191 and the common line 120 is formed.

After the first conductive pattern is formed on the lower substrate as described above, as shown in FIGS. 12A and 12B, the second conductive pattern and the semiconductor layer are formed on the gate insulating layer 130 using the second mask process. Form. 12A and 12B are plan and cross-sectional views illustrating a method of manufacturing a second conductive pattern and a semiconductor pattern of a thin film transistor substrate according to the present invention.

12A and 12B, a gate insulating layer 130 is coated on the lower substrate 100 on which the first conductive pattern is formed. A semiconductor pattern including an active layer 143 and an ohmic contact layer 144 on the gate insulating layer 130 using a second mask process; Second conductive pattern including a data line 140, a source electrode 141 connected to the data line 140, a drain electrode 142 facing the source electrode with a channel interposed therebetween, and a lower data pad electrode 196. To form.

In detail, as illustrated in FIG. 13A, the first semiconductor layer 143, the second semiconductor layer 144, and the data metal layer 140 may be formed on the gate insulating layer 130 by a deposition method such as PECVD or sputtering. Form sequentially. As the first semiconductor layer 143, amorphous silicon without doping impurities is used, and for the second semiconductor layer 144, amorphous silicon doped with N-type or P-type impurities is used. The data metal layer 140 is made of at least one metal of molybdenum (Mo) and copper (Cu).

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After the photoresist is applied on the data metal layer 140, a photolithography process and an etching process are performed on the photoresist using the second mask 200, as shown in FIG. 13B, on the data metal layer 140. The photoresist pattern 250 having a step is formed in correspondence to the blocking portion 220 and the diffraction exposure portion 240 of the second mask 200. In this case, the height h1 of the photoresist pattern 250 formed by the diffraction exposure unit 240 is formed to be lower than the height h2 of the photoresist pattern 250 formed in the blocking region. The second mask 200 is a mask substrate 210 made of a transparent material, a blocking portion 220 formed in the blocking region of the mask substrate 210, an exposure portion 230 formed in the exposure region of the mask substrate 210, and a mask. The diffraction exposure part 240 (or semi-transmissive part) formed in the partial exposure area | region of the board | substrate 210 is provided.

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As described above, after the photoresist pattern 250 having the step difference is formed on the data metal layer 130, as shown in FIG. 13C, the data metal layer 130 exposed by the photoresist pattern 250 is exposed. An etching process is performed to remove the exposed data metal layer 130.

By removing the photoresist pattern 250 of the partial exposure region through the ashing process using an oxygen (O ₂ ) plasma and lowering the height of the photoresist pattern 250 of the blocking region, as shown in FIG. 13D. Likewise, the data metal layer 140 formed on the channel region is exposed.

As described above, by performing an etching process on the data metal layer 140 exposed on the channel region and then an ashing process on the second semiconductor layer 144, as shown in FIG. While the first semiconductor layer 144 is exposed, the data metal layer 140 is separated into the source electrode 141 and the drain electrode 142, respectively.

By removing the photoresist pattern 250 remaining in the data metal layer 140 through the strip process, as shown in FIG. 13F, a source formed of data metal and connected to the data line 140 and the data line 140. An active layer 143 and an ohmic contact forming a channel with a second conductive pattern including an electrode 141, a drain electrode 142 facing the source electrode 141 with the channel interposed therebetween, and a data pad lower electrode 196. A semiconductor layer comprising a layer 144 is formed.

After forming the second conductive pattern and the semiconductor layer on the gate insulating film as described above, as shown in Figure 14a and 14b, the first to fourth on the gate insulating film 130 using a third mask process A passivation layer 160 having contact holes 161, 162, 163, and 164 is formed. 14A and 14B are plan views and cross-sectional views illustrating a method of forming the passivation layer 160 of the thin film transistor substrate according to the present invention.

14A and 14B, a passivation layer 160 is formed on the gate insulating layer 130 on which the first conductive pattern is formed to protect the active layer 143 and the pixel region 171 from a subsequent process. The passivation layer 160 covers the thin film transistor and the second conductive pattern. As the material of the passivation layer 160, an inorganic insulating material such as the gate insulating layer 130 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

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After applying the photoresist (PR) on the protective film 160 to form a photoresist pattern used for forming the first to fourth contact holes (161, 162, 163, 164) through a photolithography process and an etching process using a third mask do.

As described above, after the photoresist pattern is formed on the passivation layer 160, the first to fourth contact holes 161, 162, 163 and 164 are formed by performing an etching process on the passivation layer 160 exposed through the photoresist pattern.

The first contact hole 161 penetrates through the passivation layer 160 to expose the drain electrode 142, and the second contact hole 162 penetrates through the passivation layer 160 and the gate insulating layer 130. 191 is exposed, the third contact hole 163 penetrates the passivation layer 160 to expose the data pad lower electrode 191, and the fourth contact hole 164 is the passivation layer 160 and the gate insulating layer 130. Through it to expose the common line 120.

By removing the photoresist pattern remaining in the passivation layer 160 through the strip process, the passivation layer 160 having the first to fourth contact holes 161, 162, 163, and 164 is formed on the gate insulating layer 130 while the thin film transistor is covered. do.

After forming the passivation layer 160 having a plurality of contact holes formed on the gate insulating layer as described above, as shown in FIGS. 15A and 15B, a third conductive pattern is formed on the passivation layer 150 using a fourth mask process. Form. 15A and 15B are a plan view and a cross-sectional view illustrating a method of forming a third conductive pattern of a thin film transistor substrate according to the present invention.

15A and 15B, the pixel electrode 170, the gate pad upper electrode 192, and the data pad upper electrode are formed on the passivation layer 160 where the first to fourth contact holes 161, 162, and 163 are formed through the fourth mask process. A third conductive pattern including the first electrode 196 and the common electrode 121 is formed.

In detail, an opaque conductive film is formed on the passivation layer 160 on which the first to fourth contact holes 161, 162, 163 and 164 are formed by sputtering or the like. Ti or Ti alloys can be used. Here, the material of the opaque conductive film used to form the third conductive pattern is not limited to Ti or Ti alloy, and it is preferable that various kinds of opaque metals can be used.

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Subsequently, after the photoresist is coated on the opaque conductive metal film, a photoresist pattern and an etching process using the fourth mask 400 are performed to form a photoresist pattern.

After forming the photoresist pattern on the opaque conductive film as described above, by etching the opaque conductive film exposed through the photoresist pattern, the pixel electrode 170, the gate pad upper electrode 192, the data pad upper electrode A third conductive pattern including the first electrode 197 and the common electrode 121 is formed.

The pixel electrode 170 is formed on the passivation layer 160 by overlapping with the gate line 110 and formed in parallel with the horizontal portion 170a, and protrudes from the horizontal portion 170a to be parallel to the common electrode 121. A finger portion 170b for generating a horizontal electric field is provided at 171. The finger portion 170b and the common electrode 121 of the pixel electrode 170 are formed on the same layer on the passivation layer 16 to form a horizontal electric field.

The horizontal portion 170a of the pixel electrode 170 is connected to the drain electrode 142 of the thin film transistor 150 through the first contact hole 161 passing through the gate insulating layer 130 and the passivation layer 160. Overlapping with line 110 forms a storage capacitor 180. In this case, the storage capacitor 180 stably maintains the pixel signal charged in the pixel electrode 160 until the next pixel signal is charged.

The gate pad upper electrode 192 constituting the gate pad 190 is connected to the gate pad lower electrode 192 through the second contact hole 162 penetrating through the passivation layer 160 and the gate insulating layer 130.

The data pad upper electrode 197 constituting the data pad 195 is connected to the data pad lower electrode 197 through a third contact hole 163 penetrating the passivation layer 160.

The common electrode 121 is connected to the common line 120 through the fourth contact hole 164 penetrating through the passivation layer 160 and the gate insulating layer 130 and simultaneously pings the pixel electrode 170 on the passivation layer 160. It is formed parallel to the reject 170b.

As the reference voltage is applied through the common line 120, the common electrode 121 forms a horizontal electric field together with the finger 170b of the pixel electrode 170 positioned in parallel on the passivation layer 160. An image is realized on the screen by rotating the liquid crystal molecules oriented in the horizontal direction at 171 in a predetermined direction.

As described above, the horizontal field type thin film transistor substrate and the method of manufacturing the same according to the present invention can provide a high contrast ratio by preventing light leakage on the pixel region by forming a pixel electrode and a common electrode using an opaque conductive film. Has an effect.

In addition, the present invention has an effect that a pixel electrode and a common electrode having good electrical conductivity can be formed by forming a pixel electrode and a common electrode using an opaque conductive film having a low resistance value.

In addition, the present invention has the effect of preventing the electrode from being corroded by moisture or the like contained in the air by forming the pixel electrode and the common electrode using an opaque conductive film having high corrosion resistance.

In addition, the present invention forms a pixel electrode and a common electrode using an opaque conductive film, thereby preventing the UV reflected light reflected from the vacuum chuck fixing the glass substrate during the photolithography process to form a pixel electrode and a common electrode having a uniform line width. Has the effect that it can.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (20)

A gate line and a common line formed in parallel on the substrate; A data line intersecting the gate line with a first insulating layer interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A second insulating layer formed on the first insulating layer and covering the thin film transistor; A pixel electrode connected to the thin film transistor through the second insulating layer; A common electrode connected to the common line through the first insulating layer and the second insulating layer and formed in parallel with the pixel electrode to form a horizontal electric field; A storage capacitor formed by the gate line and the pixel electrode overlapping each other with the first insulating layer and the second insulating layer interposed therebetween; A gate pad connected to the gate line; And A data pad connected to the data line, The gate pad may include a gate pad lower electrode connected to the gate line, a gate contact hole penetrating the second insulating layer and the first insulating layer to expose the gate pad lower electrode, and the gate pad through the gate contact hole. A gate pad upper electrode connected to the lower electrode, The data pad includes a data pad lower electrode connected to the data line, a data contact hole penetrating the second insulating layer to expose the data pad lower electrode, and a data pad lower electrode connected to the data pad lower electrode. A data pad upper electrode, The pixel electrode, the common electrode, the gate pad upper electrode, and the data pad upper electrode each include Ti or a Ti alloy. delete delete delete The method of claim 1, Each of the gate line, the gate electrode of the thin film transistor connected to the gate line, the gate pad lower electrode, and the common line is formed of aluminum (Al) -based metal, copper (Cu), chromium (Cr), and molybdenum (Mo). A horizontal field type thin film transistor substrate comprising at least one metal. delete The method of claim 1, Each of the data line, the source electrode of the thin film transistor connected to the data line, the drain electrode of the thin film transistor, and the lower data pad lower electrode may include at least one of molybdenum (Mo) and copper (Cu). Horizontal field type thin film transistor substrate. delete After forming a first conductive pattern including a gate line, a common line, and a gate electrode of a thin film transistor connected to the gate line, forming a first insulating layer covering the first conductive pattern on the substrate; A semiconductor layer of the thin film transistor, the data line intersecting the gate line with the first insulating layer interposed therebetween, a source electrode of the thin film transistor connected to the data line, and a drain electrode of the thin film transistor; Forming a second conductive pattern; Forming a second insulating layer on the first insulating layer to cover the second conductive pattern and the thin film transistor; A pixel electrode penetrating the second insulating layer and connected to the drain electrode of the thin film transistor is formed, and the gate line and the pixel electrode are overlapped with each other with the first insulating layer and the second insulating layer interposed therebetween. Forming a capacitor; And Forming a common electrode connected to the common line through the first insulating layer and the second insulating layer and formed in parallel with the pixel electrode to form a horizontal electric field; The gate pad connected to the gate line may include a gate contact hole exposing the gate pad lower electrode through the gate pad lower electrode connected to the gate line, the second insulating layer and the first insulating layer, and the gate contact hole. A gate pad upper electrode connected to the gate pad lower electrode through the The data pad connected to the data line may include a data pad lower electrode connected to the data line, a data contact hole through the second insulating layer to expose the data pad lower electrode, and a lower portion of the data pad through the data contact hole. A data pad upper electrode connected to the electrode, The pixel electrode, the common electrode, the gate pad upper electrode, and the data pad upper electrode each include Ti or a Ti alloy. delete delete delete The method of claim 9, Each of the gate line, the gate electrode of the thin film transistor connected to the gate line, the gate pad lower electrode, and the common line is formed of aluminum (Al) -based metal, copper (Cu), chromium (Cr), and molybdenum (Mo). A method for manufacturing a horizontal field type thin film transistor substrate comprising at least one metal. delete The method of claim 9, Each of the data line, the source electrode of the thin film transistor connected to the data line, the drain electrode of the thin film transistor, and the lower data pad lower electrode may include at least one of molybdenum (Mo) and copper (Cu). A method of manufacturing a horizontal field type thin film transistor substrate. delete Forming a first conductive pattern including a gate line, a gate electrode of a thin film transistor connected to the gate line, a gate pad lower electrode connected to the gate line, and a common line parallel to the gate line on a substrate; Forming a first insulating layer on the substrate on which the first conductive pattern is formed to cover the first conductive pattern; A semiconductor layer of the thin film transistor is formed on the first insulating layer, and a data line intersecting the gate line and a source electrode and a channel of the thin film transistor connected to the data line are disposed on the first insulating layer. Forming a second conductive pattern including a drain electrode and a data pad lower electrode of the thin film transistor facing the source electrode; Forming a second insulating layer on the first insulating layer to cover the thin film transistor and the second conductive pattern; And A pixel electrode connected to the drain electrode on the second insulating layer, a common electrode connected to the common line to form a horizontal electric field together with the pixel electrode, a gate pad upper electrode connected to the gate pad lower electrode, and the data A storage capacitor is formed by overlapping the gate line and the pixel electrode with the first insulating layer and the second insulating layer interposed therebetween, while forming a third conductive pattern including a data pad upper electrode connected to the pad lower electrode. Forming a step; The pixel electrode, the common electrode, the gate pad upper electrode and the data pad upper electrode each include Ti or a Ti alloy. delete delete delete

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