KR102320186B1 - Organic light emitting display device and method of fabricating the same - Google Patents

Abstract

The organic light emitting display device of the present invention and a manufacturing method thereof, in a top emission type organic light emitting display device, improve productivity by removing a protective film covering data lines, while improving the structure and manufacturing process of the pad area To prevent damage to the pad electrode by the etchant during patterning of the anode by improving a thin film transistor formed on the substrate of the display area; a pad line formed on the substrate in the pad area; a gate pad electrode and a data pad electrode formed in a pad region of the same layer on which the gate wiring of the thin film transistor is formed; an interlayer insulating film formed on the substrate on which the gate pad electrode and the data pad electrode are formed and exposing a portion of the gate pad electrode and the data pad electrode to the outside; a first electrode and an auxiliary electrode formed on the substrate of the display area in which the thin film transistor is formed; a bank surrounding an edge of the first electrode to define an opening while exposing a part of the auxiliary electrode; an organic compound layer formed on the substrate on which the banks are formed; and a second electrode formed on the substrate on which the organic compound layer is formed and in contact with the exposed auxiliary electrode.

Description

Organic light emitting display device and manufacturing method thereof

The present invention relates to an organic light emitting display device and a method for manufacturing the same, and more particularly, to a top emission type organic light emitting display device and a method for manufacturing the same.

Recently, as interest in information display is rising and the demand to use portable information media increases, it has been applied to a lightweight, thin flat panel display (FPD) replacing the conventional display device, a cathode ray tube (CRT). Research and commercialization are focused on.

In such a flat panel display field, a liquid crystal display device (LCD), which is light and low power consumption, has been the most attractive display device until now, but the liquid crystal display device is a light receiving device, not a light emitting device, and is ) and viewing angle, the development of a new display device capable of overcoming these disadvantages is being actively developed.

The organic light emitting display device, one of the new display devices, is a self-luminous type, so it has superior viewing angle and contrast ratio compared to the liquid crystal display device. . In addition, it has the advantage of being able to drive at a low DC voltage and having a fast response speed, and in particular, it has an advantage in terms of manufacturing cost.

Unlike a liquid crystal display or a plasma display panel (PDP), in the manufacturing process of the organic light emitting display device, the deposition and encapsulation processes are all processes, so the manufacturing process is very simple. In addition, when the organic light emitting display device is driven in an active matrix method having a thin film transistor (TFT) as a switching element for each pixel, the same luminance is displayed even when a low current is applied, so that low power consumption, It has the advantage of being able to achieve a fixed price and a large size.

Hereinafter, the basic structure and operation characteristics of the organic light emitting display device will be described in detail with reference to the drawings.

1 is a diagram illustrating a light emitting principle of a general organic light emitting diode.

In general, an organic light emitting display device includes an organic light emitting diode as shown in FIG. 1 .

In this case, the organic light emitting diode includes an anode 18 as a pixel electrode, a cathode 28 as a common electrode, and organic compound layers 31 , 32 , 35 , 36 and 37 formed therebetween.

In addition, the organic compound layers 31 , 32 , 35 , 36 , and 37 include a hole injection layer 31 , a hole transport layer 32 , an emission layer 35 , and an electron transport layer. an electron transport layer 36 and an electron injection layer 37 .

When a driving voltage is applied to the anode 18 and cathode 28, holes passing through the hole transport layer 32 and electrons passing through the electron transport layer 36 are moved to the light emitting layer 35 to form excitons, and as a result, the light emitting layer (35) emits visible light.

The organic light emitting display device displays an image by arranging pixels having the organic light emitting diodes having the above-described structure in a matrix form and selectively controlling the pixels with a data voltage and a scan voltage.

In this case, the organic light emitting display device is divided into a passive matrix method or an active matrix method using a TFT as a switching device. Among them, the active matrix method selects a pixel by selectively turning on the TFT, which is an active element, and maintains the light emission of the pixel with a voltage maintained in a storage capacitor.

The organic light emitting display device driven as described above may be classified into a top emission method, a bottom emission method, and a dual emission method according to a direction in which light is emitted.

The top emission type organic light emitting display device is a method in which light is emitted in the opposite direction to the substrate on which the pixels are arranged, and has the advantage that the aperture ratio can be increased compared to the back emission type in which light is emitted in the direction of the substrate on which the pixels are arranged. It's been used a lot lately.

In such a top emission type organic light emitting display device, an anode is formed under the organic compound layer, and a cathode is formed on the organic compound layer through which light is transmitted.

In this case, the cathode should be formed thinly (~ 100 Å) in order to be implemented as a semi-transmissive layer having a low work function. In this case, the cathode has a high resistance.

As described above, in the front light emitting type organic light emitting display device, a voltage drop (IR drop) occurs in the panel due to the high resistance of the cathode, and thus different levels of voltage are applied to each pixel, resulting in non-uniformity of luminance or image quality. There is a problem that In particular, as the size of the panel increases, the voltage drop may intensify.

An object of the present invention is to provide an organic light emitting display device capable of preventing voltage drop of a cathode in a top light emitting organic light emitting display device, and a method for manufacturing the same.

Another object of the present invention is to provide an organic light emitting display device capable of reducing the number of masks and a manufacturing method thereof.

Another object of the present invention is to provide an organic light emitting display device capable of preventing damage to a pad electrode by an etchant during patterning of an anode and a method for manufacturing the same.

In addition, other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above object, an organic light emitting display device according to an embodiment of the present invention includes a substrate divided into a display area and a pad area; a thin film transistor formed on the substrate of the display area; a pad line formed on the substrate in the pad area; a gate pad electrode and a data pad electrode formed in a pad region of the same layer on which the gate wiring of the thin film transistor is formed; an interlayer insulating film formed on the substrate on which the gate pad electrode and the data pad electrode are formed and exposing a portion of the gate pad electrode and the data pad electrode to the outside; a first electrode and an auxiliary electrode formed on the substrate of the display area in which the thin film transistor is formed; a bank surrounding an edge of the first electrode to define an opening while exposing a part of the auxiliary electrode; an organic compound layer formed on the substrate on which the banks are formed; and a second electrode formed on the substrate on which the organic compound layer is formed and in contact with the exposed auxiliary electrode.

In this case, the gate pad electrode and the data pad electrode may be formed of a double layer structure of Cu/MoTi or a triple layer structure of ITO/Cu/MoTi.

The gate pad electrode and the data pad electrode may have a triple layer structure of Ti/Al/Ti.

The interlayer insulating layer of the pad region may include an open hole exposing a portion of the gate pad electrode and the data pad electrode to the outside, and a jumping hole exposing one end of the data pad electrode.

In this case, the data pad electrode may be electrically connected to the data line of the thin film transistor through the jumping hole.

In the gate pad electrode and the data pad electrode, not only the surface but also the interlayer insulating layer positioned on one side thereof may be removed, so that the side surface may also be exposed to the outside.

An organic light emitting display device according to another embodiment of the present invention includes: a substrate divided into a display area and a pad area; a thin film transistor formed on the substrate of the display area; a pad line formed on the substrate in the pad area; a gate pad line and a data pad line formed in a pad region of the same layer on which the gate wiring of the thin film transistor is formed; a gate pad electrode and a data pad electrode formed in a pad region of the same layer on which the data wiring of the thin film transistor is formed, electrically connected to the gate pad line and the data pad line, and having a triple layer structure of Ti/Al/Ti; a first electrode and an auxiliary electrode formed on the substrate of the display area in which the thin film transistor is formed; a bank surrounding an edge of the first electrode to define an opening while exposing a part of the auxiliary electrode; an organic compound layer formed on the substrate on which the banks are formed; and a second electrode formed on the substrate on which the organic compound layer is formed and in contact with the exposed auxiliary electrode.

A method of manufacturing an organic light emitting display device according to an embodiment of the present invention includes providing a substrate divided into a display area and a pad area; forming a gate line on the substrate of the display area and at the same time forming a gate pad electrode and a data pad electrode on the substrate of the pad area; forming an interlayer insulating layer on the substrate on which the gate wiring, the gate pad electrode, and the data pad electrode are formed; forming a data line on the substrate of the display area on which the interlayer insulating layer is formed; forming a planarization layer on the substrate on which the data lines are formed; after forming a first electrode and an auxiliary electrode on the substrate of the display area on which the planarization layer is formed, selectively removing the interlayer insulating layer of the pad area to expose a portion of the gate pad electrode and the data pad electrode to the outside; forming a bank exposing a portion of the auxiliary electrode on the substrate on which the first electrode and the auxiliary electrode are formed; forming an organic compound layer on the substrate on which the bank is formed; and forming a second electrode on the substrate on which the organic compound layer is formed to be in contact with the exposed auxiliary electrode.

According to another embodiment of the present invention, a method of manufacturing an organic light emitting display device includes: providing a substrate divided into a display area and a pad area; forming a gate line on the substrate of the display area and at the same time forming a gate pad electrode and a data pad electrode on the substrate of the pad area; forming an interlayer insulating layer on the substrate on which the gate wiring, the gate pad electrode, and the data pad electrode are formed; exposing portions of the gate pad electrode and the data pad electrode to the outside by selectively removing the insulating interlayer in the pad region; forming a data line on the substrate of the display area on which the interlayer insulating layer is formed; forming a planarization layer on the substrate on which the data lines are formed; forming a first electrode and an auxiliary electrode on the substrate of the display area on which the planarization layer is formed; forming a bank exposing a portion of the auxiliary electrode on the substrate on which the first electrode and the auxiliary electrode are formed; forming an organic compound layer on the substrate on which the bank is formed; and forming a second electrode on the substrate on which the organic compound layer is formed to be in contact with the exposed auxiliary electrode.

In this case, the method may further include forming a jumping hole exposing one end of the data pad electrode by selectively removing the interlayer insulating layer.

In this case, the gate pad electrode and the data pad electrode may be formed in a double layer structure of Cu/MoTi or a triple layer structure of ITO/Cu/MoTi.

The gate pad electrode and the data pad electrode may be formed in a triple layer structure of Ti/Al/Ti.

An open hole for exposing a portion of the gate pad electrode and the data pad electrode to the outside may be formed by selectively removing the insulating interlayer in the pad region.

By selectively removing the insulating interlayer in the pad region, not only the surfaces of the gate pad electrode and the data pad electrode, but also the side surfaces may be exposed to the outside.

ITO of the gate pad electrode and the data pad electrode may be crystallized by annealing the planarization layer.

As described above, in the organic light emitting display device and the method for manufacturing the same according to an embodiment of the present invention, in the organic light emitting display device of the top light emitting method, the luminance uniformity of the panel is reduced by forming an auxiliary electrode to reduce the resistance of the cathode. provides the effect of enhancing

An organic light emitting display device and a method of manufacturing the same according to an embodiment of the present invention provide an effect of improving productivity by reducing the number of masks by removing a protective film covering data lines.

In addition, by improving the structure and manufacturing process of the pad region, it is possible to prevent damage to the pad electrode due to the etchant during patterning of the anode. As a result, reliability is improved, and defects are reduced and productivity is improved.

1 is a diagram illustrating the light emitting principle of a general organic light emitting diode.
2 is a view for explaining a pixel structure of an organic light emitting display device;
3 is a perspective view exemplarily illustrating a structure of an organic light emitting display device according to a first embodiment of the present invention;
4A and 4B are cross-sectional views schematically illustrating a part of a structure of an organic light emitting display device according to a first embodiment of the present invention;
5A and 5B are photographs showing, for example, damage to the pad electrode due to corrosion and migration of Ag.
6A and 6B are cross-sectional views schematically illustrating a part of a structure of an organic light emitting display device according to a second embodiment of the present invention;
7A to 7I are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to a second embodiment of the present invention shown in FIG. 6A;
8A to 8G are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to a second embodiment of the present invention shown in FIG. 6B;
9A to 9F are cross-sectional views sequentially illustrating another method of manufacturing the organic light emitting display device according to the second embodiment of the present invention shown in FIG. 6B;
10A and 10B are cross-sectional views schematically illustrating a part of a structure of an organic light emitting display device according to a third embodiment of the present invention;
11A to 11I are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to a third embodiment of the present invention shown in FIG. 10A;
12A to 12G are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to a third embodiment of the present invention shown in FIG. 10B;
13A to 13F are cross-sectional views sequentially illustrating another method of manufacturing the organic light emitting display device according to the third embodiment of the present invention shown in FIG. 10B;
14A and 14B are cross-sectional views schematically illustrating a part of a structure of an organic light emitting display device according to a fourth embodiment of the present invention;
15A to 15I are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to a fourth embodiment of the present invention shown in FIG. 14A;
16A to 16D are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to a fourth embodiment of the present invention shown in FIG. 14B;

Hereinafter, preferred embodiments of an organic light emitting display device and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily carry out the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description.

Reference to an element or layer to another element or “on” or “on” includes not only directly on the other element or layer, but also with other layers or other elements interposed therebetween. do. On the other hand, reference to an element "directly on" or "directly on" indicates that there are no intervening elements or layers.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. Spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, if an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above.

The terminology used herein is for the purpose of describing the embodiments, and thus is not intended to limit the present invention. As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprise” and/or “comprising” refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

2 is a view for explaining a pixel structure of an organic light emitting display device.

Referring to FIG. 2 , in the organic light emitting display device, a gate line GL arranged in a first direction, a data line DL arranged spaced apart from each other in a second direction crossing the first direction, and a driving power line VDDL ) defines the pixel area.

A switching thin film transistor ST, a driving thin film transistor DT, a storage capacitor C, and an organic light emitting diode OLED are formed in the pixel region.

The switching thin film transistor ST is switched according to the gate signal supplied to the gate line GL and supplies the data signal supplied to the data line DL to the driving thin film transistor DT.

In addition, the driving thin film transistor DT is switched according to a data signal supplied from the switching thin film transistor ST to control a current flowing from the driving power line VDDL to the organic light emitting diode OLED.

The storage capacitor C is connected between the gate electrode of the driving thin film transistor DT and the base power line VSSL to store a voltage corresponding to a data signal supplied to the gate electrode of the driving thin film transistor DT, and the stored voltage Thus, the turn-on state of the driving transistor DT is constantly maintained for one frame.

The organic light emitting diode OLED is electrically connected between the source electrode or drain electrode of the driving thin film transistor DT and the base power line VSSL and emits light by a current corresponding to a data signal supplied from the driving thin film transistor DT. do.

3 is a perspective view exemplarily showing the structure of an organic light emitting display device according to the first embodiment of the present invention, and is an organic light emitting display in a state in which a flexible printed circuit board (FPCB) is fastened to a pad area. The device is shown as an example.

4A and 4B are cross-sectional views schematically illustrating a part of the structure of the organic light emitting display device according to the first embodiment of the present invention.

In this case, FIG. 4A shows, for example, one sub-pixel including a TFT unit and a capacitor forming unit of an organic light emitting display device, and FIG. 4B shows a gate pad region and a part of the data pad region in order. have.

In particular, FIG. 4A illustrates one sub-pixel of an organic light emitting display device of a top emission type using a TFT having a coplanar structure as an example. However, the present invention is not limited to the TFT having a coplanar structure.

5A and 5B are photographs showing, for example, damage to the pad electrode due to corrosion and migration of Ag, and a Focused Ion Beam (FIB) photograph is shown as an example.

Referring to FIG. 3 , the organic light emitting display device according to the first embodiment of the present invention includes a panel assembly 100 that largely displays an image and a flexible circuit board 140 connected to the panel assembly 100 .

The panel assembly 100 includes a TFT substrate 110 in which an active area AA and a pad area are defined and an encapsulation layer formed on the TFT substrate 110 while covering the display area AA ( 120).

In this case, the pad area may be exposed without being covered by the encapsulation layer 120 .

The TFT substrate 110 including a TFT and an organic light emitting diode may use a polyimide substrate as a base substrate, and at this time, a back plate 105 may be attached to the rear surface thereof.

In addition, a polarizing plate (not shown) for preventing reflection of light incident from the outside may be attached on the encapsulation layer 120 .

At this time, although not shown, sub-pixels are arranged in a matrix form in the display area AA of the TFT substrate 110 , and driving devices such as a scan driver and a data driver for driving the sub-pixels are outside the display area AA. and other parts are located.

When the display area AA of the TFT substrate 110 is described in detail with reference to FIG. 4A , the organic light emitting display device according to the first embodiment of the present invention includes a substrate 110 , a driving thin film transistor DT, It includes an organic light emitting diode and an auxiliary electrode line (VSSLa).

First, the driving thin film transistor DT includes a semiconductor layer 124 , a gate electrode 121 , a source electrode 122 , and a drain electrode 123 .

The semiconductor layer 124 is formed on the substrate 101 made of an insulating material such as a transparent plastic or a polymer film.

The semiconductor layer 124 may be formed of an amorphous silicon film or a polycrystalline silicon film obtained by crystallizing amorphous silicon.

In this case, a buffer layer (not shown) may be further formed between the substrate 110 and the semiconductor layer 124 . The buffer layer may be formed to protect the thin film transistor from impurities such as alkali ions leaking from the substrate 110 when the semiconductor layer 124 is crystallized.

A gate insulating film 115a made of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ) is formed on the semiconductor layer 124 , and the gate line (not shown) including the gate electrode 121 and the first A sustain electrode 109 is formed.

The gate electrode 121, the gate line, and the first storage electrode 109 are formed of a first metal material having a low resistance characteristic, for example, aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), It may be formed as a single layer or multiple layers made of gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy thereof.

On the gate electrode 121, the gate line, and the first storage electrode 109, an inter insulation layer 115b made of a silicon nitride film or a silicon oxide film is formed, and a data line, that is, a data line (not shown) time), a driving voltage line (not shown), source/drain electrodes 122 and 123 , and a second storage electrode 119 are formed.

The source electrode 122 and the drain electrode 123 are formed to be spaced apart from each other by a predetermined interval, and are electrically connected to the semiconductor layer 124 . More specifically, semiconductor layer contact holes exposing the semiconductor layer 124 are formed in the gate insulating layer 115a and the interlayer insulating layer 115b, and the source/drain electrodes 122 and 123 are connected through the semiconductor layer contact hole. It is electrically connected to the semiconductor layer 124 .

In this case, the second storage electrode 119 overlaps a portion of the first storage electrode 109 with the interlayer insulating layer 115b interposed therebetween to form a storage capacitor.

The data line, the driving voltage line, the source/drain electrodes 122 and 123 and the second storage electrode 119 are formed of a second metal material having a low resistance, for example, aluminum (Al), copper (Cu), molybdenum ( Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or may be formed of a single layer or multiple layers made of an alloy thereof.

A passivation layer 115c and a planarization layer 115d are formed on the substrate 110 on which the data line, the driving voltage line, the source/drain electrodes 122 and 123 and the second storage electrode 119 are formed.

Next, the organic light emitting diode includes a first electrode 118 , an organic compound layer 130 , and a second electrode 128 .

The organic light emitting diode is electrically connected to the driving thin film transistor DT. More specifically, in the passivation layer 115c and the planarization layer 115d formed on the driving thin film transistor DT, a drain contact hole exposing the drain electrode 123 of the driving thin film transistor DT is formed. The organic light emitting diode is electrically connected to the drain electrode 123 of the driving thin film transistor DT through a drain contact hole.

That is, the first electrode 118 is formed on the planarization layer 115d and is electrically connected to the drain electrode 123 of the driving thin film transistor DT through a drain contact hole.

The first electrode 118 supplies a current (or voltage) to the organic compound layer 130 , and defines a light emitting region of a predetermined area.

Also, the first electrode 118 serves as an anode. Accordingly, the first electrode 118 is made of a transparent conductive material having a relatively large work function, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). It may include upper and lower first electrodes 118c and 118a made of And, in order to improve the reflection efficiency, the first electrode 118 may further include a reflection layer 118b made of a metal material having high reflection efficiency, for example, aluminum (Al), silver (Ag), gold ( Au), platinum (Pt), chromium (Cr), or an alloy containing these may be included.

As described above, the first electrode 118 according to the first embodiment of the present invention includes upper and lower first electrodes 118c and 118a and a reflective layer 118b between the upper first electrode 118c and the lower first electrode 118a. ) may have a triple layer structure. However, the present invention is not limited thereto.

A bank 115e is formed on the substrate 110 on which the first electrode 118 is formed. At this time, the bank 115e surrounds the edge of the first electrode 118 like a weir to define an opening, and is made of an organic insulating material or an inorganic insulating material. The bank 115e may also be made of a photosensitive material including a black pigment, and in this case, the bank 115e serves as a light blocking member.

In the first embodiment of the present invention, the bank 115e further includes a second opening exposing a part of the auxiliary electrode 125, which will be described later.

The organic compound layer 130 is formed between the first electrode 118 and the second electrode 128 . The organic compound layer 130 emits light by combining holes supplied from the first electrode 118 and electrons supplied from the second electrode 128 .

At this time, although FIG. 4 shows an example in which the organic compound layer 130 is formed on the entire surface of the substrate 110 , the present invention is not limited thereto, and the organic compound layer 130 is formed only on the first electrode 118 . can be

The organic compound layer 130 may have a multilayer structure including, in addition to the emission layer emitting light, an auxiliary layer for improving the luminous efficiency of the emission layer.

The second electrode 128 is formed on the organic compound layer 130 to provide electrons to the organic compound layer 130 .

The second electrode 128 serves as a cathode. Accordingly, the second electrode 128 is made of a transparent conductive material, and may include, for example, ITO or IZO. The second electrode 128 may further include a thin metal film (not shown) made of a metal material having a low work function on the side in contact with the organic compound layer 130 , for example, magnesium (Mg), silver (Ag) and compounds thereof may be included.

In the case of the top light emitting method, the second electrode 128 should be formed thin because it has a low work function and has to satisfy translucency. Accordingly, the resistance of the second electrode 128 is increased, and there is a disadvantage in that a voltage drop (IR drop) occurs due to the high resistance.

Accordingly, in the first embodiment of the present invention, the auxiliary electrode line VSSLa is formed on the same layer as the first electrode 118 in order to reduce the resistance of the second electrode 128 . Here, the auxiliary electrode line VSSLa includes the auxiliary electrode 125 and the barrier rib 135 .

The auxiliary electrode 125 is formed to be spaced apart on the same layer as the first electrode 118 . For example, the auxiliary electrode 125 may be continuously extended in one direction to be connected to an external VSS pad (not shown).

The auxiliary electrode 125 has a triple-layer structure of upper, middle, and lower auxiliary electrodes 125c, 125b, and 125a in substantially the same way as the first electrode 118, so that when the second electrode 128 is deposited, the upper auxiliary electrode ( 125c) can be directly contacted. That is, the second electrode 128 is deposited up to the lower portion of the barrier rib 135 to make contact with the auxiliary electrode 125 . However, the present invention is not limited thereto.

The barrier rib 135 is formed on the auxiliary electrode 125 .

In this case, the partition wall 135 may have a reverse taper shape in which the cross-sectional area becomes smaller from the upper part to the lower part. For example, the angle formed between the side surface of the barrier rib 135 and the auxiliary electrode 125 may be 20 degrees to 80 degrees.

The barrier rib 140 forms an electrode contact hole exposing the auxiliary electrode 125 in the organic compound layer 130 . The organic compound layer 130 is formed on the upper portion of the barrier rib 140 by a shading effect, and is not formed under the upper portion of the barrier rib 140 . That is, the organic compound layer 130 is deposited on the substrate 110 by evaporation having a linearity, but is not formed below the upper portion of the barrier rib 140 by the barrier rib 140 having a reverse tapered shape. Accordingly, an electrode contact hole is formed in the organic compound layer 130 .

In contrast, as the second electrode 128 is deposited through sputtering, the second electrode 128 is deposited on the sidewalls as well as the lower portion of the barrier rib 135 to make contact with the auxiliary electrode 125 .

Referring to FIG. 4B , in the edge region of the TFT substrate 110 constituting the display region as described above, a gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line and the data line are formed, respectively. , a scan signal and a data signal applied from an external driving circuit unit (not shown) are transmitted to the gate line and the data line, respectively.

That is, the gate line and the data line extend toward the driving circuit unit and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively. The gate pad line 116p and the data pad line 117p are electrically connected to the gate pad electrode 126p and the data pad electrode 127p through the gate pad line pattern 116p' and the data pad line pattern 117p', respectively. is connected to Accordingly, the gate line and the data line receive the scan signal and the data signal respectively from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p.

At this time, the gate pad electrode 126p and the data pad electrode 127p according to the first embodiment of the present invention have a triple-layer structure, one substantially the same as the first electrode 118 and the auxiliary electrode 125 of the display area. For example, it is characterized in that it has a triple layer structure of ITO/Ag alloy/ITO.

That is, the gate pad electrode 126p according to the first embodiment of the present invention may be composed of upper, middle, and lower gate pad electrodes 126pc, 126pb, and 126pa, and the data pad electrode 127p includes the upper, middle and lower gate pad electrodes 126pc, 126pb, and 126pa. The lower data pad electrodes 127pc, 127pb, and 127pa may have a triple-layer structure.

In the organic light emitting display device according to the first embodiment of the present invention, when the reflective layer 118b of the first electrode 118 is formed of an Ag alloy in order to improve reflectivity, the pad electrode, that is, the gate pad electrode 126p and the data pad electrode 127p are also made of ITO/Ag alloy/ITO. At this time, there is a possibility that a short circuit with an adjacent wiring may occur due to corrosion and migration of Ag (refer to FIGS. 5A and 5B ). When the pad electrode is corroded, the signal transmission of the driver driving circuit is not smooth, and a defect may occur.

Accordingly, in the second to fourth embodiments of the present invention, damage to the pad electrode due to the etchant can be prevented when the first electrode is patterned by improving the structure and manufacturing process of the pad region.

In addition, in the second to fourth embodiments of the present invention, the number of masks is reduced by removing the protective film covering the data wiring, thereby improving productivity. This will be described in detail with reference to the drawings.

6A and 6B are cross-sectional views schematically illustrating a part of the structure of an organic light emitting display device according to a second exemplary embodiment of the present invention.

In this case, FIG. 6A shows one sub-pixel including a TFT unit and a capacitor forming unit of the organic light emitting display device as an example, and FIG. 6B shows a gate pad region and a part of the data pad region in order. In particular, FIG. 6B illustrates the data pad area including a part of the display area as an example for convenience of description.

In particular, FIG. 6A illustrates one sub-pixel of an organic light emitting display device of a top emission type using a TFT having a coplanar structure as an example. However, the present invention is not limited to the TFT having a coplanar structure.

Referring to FIG. 6A , the top-emission organic light emitting display device according to the second embodiment of the present invention includes a substrate 210 , a driving thin film transistor DT, an organic light emitting diode, and an auxiliary electrode line VSSLa. .

As in the first embodiment, the driving thin film transistor DT includes a semiconductor layer 224 , a gate electrode 221 , a source electrode 222 , and a drain electrode 223 .

The semiconductor layer 224 is formed on the substrate 201 made of an insulating material such as a transparent plastic or a polymer film.

The semiconductor layer 224 may be formed of an amorphous silicon film or a polycrystalline silicon film obtained by crystallizing amorphous silicon.

In this case, a buffer layer (not shown) may be further formed between the substrate 210 and the semiconductor layer 224 . The buffer layer may be formed to protect the thin film transistor from impurities such as alkali ions leaking from the substrate 210 when the semiconductor layer 224 is crystallized.

A gate insulating film 215a made of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ) is formed on the semiconductor layer 224 , and a gate line (not shown) including a gate electrode 221 and the first A sustain electrode 209 is formed.

In this case, the gate wiring according to the second embodiment of the present invention, that is, the gate electrode 221 , the gate line, and the first storage electrode 209 includes a low-resistance material such as Cu.

For example, the gate wiring according to the second embodiment of the present invention may be formed of three or more multi-layers including upper and lower layers for enhancing contact characteristics on upper and lower portions of Cu. However, the present invention is not limited thereto, and the gate wiring according to the second embodiment of the present invention may be configured as a double layer including only a lower layer under Cu.

In this case, the gate electrode 221 may have a triple-layer structure of upper, middle, and lower gate electrodes 221c, 221b, and 221a, and the first storage electrode 209 includes the upper, middle, and lower first storage electrodes 209c. , 209b, 209a) may have a triple-layer structure.

For example, the gate wiring according to the second embodiment of the present invention may have a triple layer structure of ITO/Cu/MoTi.

An interlayer insulating film 215b made of a silicon nitride film or a silicon oxide film is formed on the gate electrode 221, the gate line, and the first storage electrode 209, and a data line (not shown) and a driving voltage line (not shown) are formed thereon. ), source/drain electrodes 222 and 223 and a second storage electrode 219 are formed.

The source electrode 222 and the drain electrode 223 are formed to be spaced apart from each other by a predetermined interval, and are electrically connected to the semiconductor layer 224 . More specifically, semiconductor layer contact holes exposing the semiconductor layer 224 are formed in the gate insulating layer 215a and the interlayer insulating layer 215b, and the source/drain electrodes 222 and 223 are connected through the semiconductor layer contact hole. It is electrically connected to the semiconductor layer 224 .

In this case, the second storage electrode 219 overlaps a portion of the first storage electrode 209 with the interlayer insulating layer 215b interposed therebetween to form a storage capacitor.

At this time, the data wiring according to the second embodiment of the present invention, that is, the data line, the driving voltage line, the source/drain electrodes 222 and 223 and the second storage electrode 219 are formed of a metal material having a low resistance, for example, For example, a single layer or multiple layers made of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or alloys thereof It can be formed in layers.

A planarization layer 215c is formed on the substrate 210 on which the data line, the driving voltage line, the source/drain electrodes 222 and 223 and the second storage electrode 219 are formed.

That is, in the case of the second embodiment of the present invention, unlike the first embodiment of the present invention described above, the planarization film 215c made of an organic insulating material is formed in a state in which the protective film is not formed on the data wiring. . Accordingly, the number of masks can be reduced by one, thereby providing the effect of improving productivity.

Next, the organic light emitting diode includes a first electrode 218 , an organic compound layer 230 , and a second electrode 228 .

The organic light emitting diode is electrically connected to the driving thin film transistor DT. More specifically, in the planarization layer 215c formed on the driving thin film transistor DT, a drain contact hole exposing the drain electrode 223 of the driving thin film transistor DT is formed. The organic light emitting diode is electrically connected to the drain electrode 223 of the driving thin film transistor DT through the drain contact hole.

That is, the first electrode 218 is formed on the planarization layer 215c and is electrically connected to the drain electrode 223 of the driving thin film transistor DT through a drain contact hole.

The first electrode 218 supplies a current (or voltage) to the organic compound layer 230 and defines a light emitting region of a predetermined area.

Also, the first electrode 218 serves as an anode. Accordingly, the first electrode 218 is made of a transparent conductive material having a relatively large work function, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). It may include upper and lower first electrodes 218c and 218a made of And, in order to improve the reflection efficiency, the first electrode 218 may further include a reflection layer 218b made of a metal material having high reflection efficiency, for example, aluminum (Al), silver (Ag), gold ( Au), platinum (Pt), chromium (Cr), or an alloy containing these may be included.

As described above, the first electrode 218 according to the second embodiment of the present invention includes the upper and lower first electrodes 218c and 218a and the reflective layer 218b between the upper first electrode 218c and the lower first electrode 218a. ) may have a triple layer structure. However, the present invention is not limited thereto.

A bank 215e is formed on the substrate 210 on which the first electrode 218 is formed. In this case, the bank 215e defines an opening by enclosing the edge of the first electrode 218 like a weir, and is made of an organic insulating material or an inorganic insulating material. The bank 215e may also be made of a photosensitive material including a black pigment, and in this case, the bank 215e serves as a light blocking member.

In the second embodiment of the present invention, the bank 215e further includes a second opening exposing a part of the auxiliary electrode 225, which will be described later.

The organic compound layer 230 is formed between the first electrode 218 and the second electrode 228 . The organic compound layer 230 emits light by combining holes supplied from the first electrode 218 and electrons supplied from the second electrode 228 .

At this time, although FIG. 6A shows an example in which the organic compound layer 230 is formed on the entire surface of the substrate 210 , the present invention is not limited thereto, and the organic compound layer 230 is formed only on the first electrode 218 . can be

The organic compound layer 230 may have a multi-layered structure including an auxiliary layer for improving the luminous efficiency of the emission layer in addition to the emission layer emitting light.

The second electrode 228 is formed on the organic compound layer 230 to provide electrons to the organic compound layer 230 .

The second electrode 228 serves as a cathode. Accordingly, the second electrode 228 is made of a transparent conductive material, and may include, for example, ITO or IZO. The second electrode 228 may further include a thin metal film (not shown) made of a metal material having a low work function on the side in contact with the organic compound layer 230 , for example, magnesium (Mg), silver (Ag), and compounds thereof may be included.

And, in order to reduce the resistance of the second electrode 228 in the same manner as in the first embodiment of the present invention described above, the auxiliary electrode line VSSLa is formed on the same layer as the first electrode 218 . Here, the auxiliary electrode line VSSLa includes the above-described auxiliary electrode 225 and the barrier rib 235 .

The auxiliary electrode 225 is formed on the same layer as the first electrode 218 to be spaced apart from each other. For example, the auxiliary electrode 225 may be continuously extended in one direction to be connected to an external VSS pad (not shown).

The auxiliary electrode 225 has a triple-layer structure of upper, middle, and lower auxiliary electrodes 225c, 225b, and 225a substantially the same as the first electrode 218, so that when the second electrode 228 is deposited, the upper auxiliary electrode ( 225c) may be contacted directly. That is, the second electrode 228 is deposited up to the lower portion of the barrier rib 235 to make contact with the auxiliary electrode 225 . However, the present invention is not limited thereto.

The barrier rib 235 is formed on the auxiliary electrode 225 .

In this case, the partition wall 235 may have an inverted taper shape in which the cross-sectional area becomes smaller from the upper part to the lower part. For example, an angle between the side surface of the barrier rib 235 and the auxiliary electrode 225 may be 20 degrees to 80 degrees.

The barrier rib 235 forms an electrode contact hole exposing the auxiliary electrode 225 in the organic compound layer 230 . The organic compound layer 230 is formed on the upper portion of the barrier rib 235 due to the shading effect, and is not formed under the upper portion of the barrier rib 235 . That is, the organic compound layer 230 is deposited on the substrate 210 by evaporation having a straightness, but is not formed below the upper portion of the barrier rib 240 by the barrier rib 240 having a reverse tapered shape. Accordingly, an electrode contact hole is formed in the organic compound layer 230 .

In contrast, as the second electrode 228 is deposited through sputtering, the second electrode 228 is deposited on the side surface as well as the lower portion of the barrier rib 235 to make contact with the auxiliary electrode 225 .

Referring to FIG. 6B , in the edge region of the TFT substrate 210 constituting the display region as described above, the gate pad electrode 226p and the data pad electrode electrically connected to the gate line (not shown) and the data line 229, respectively. 227p is formed, and a scan signal and a data signal applied from an external driving circuit unit (not shown) are transmitted to the gate line and the data line 229, respectively.

At this time, in the case of the second embodiment of the present invention, unlike the above-described first embodiment of the present invention, the gate line and the data line 229 extend toward the driving circuit, and the corresponding gate pad electrode 226p and the data pad electrode respectively. (227p). Accordingly, the gate line and the data line 229 directly receive the scan signal and the data signal from the driving circuit unit through the gate pad electrode 226p and the data pad electrode 227p, respectively.

In this case, the data pad electrode 227p may be connected to the data lines 229 formed in different layers using a jumping structure. That is, the data pad electrode 227p is electrically connected to the data line 229 of the display area through the jumping hole.

The pad electrode according to the second embodiment of the present invention, that is, the gate pad electrode 226p and the data pad electrode 227p, is formed on the same layer as the gate wiring of the display area, but has a triple-layer structure substantially identical to that of the gate wiring; For example, it is characterized in that it is formed in a triple layer structure of ITO/Cu/MoTi.

That is, as an example, in the second embodiment of the present invention, a triple-layer structure of ITO/Cu/MoTi is applied to the gate pad electrode 226p and the data pad electrode 227p in the pad region, while the interlayer insulating film 215b is patterned. A portion of the gate pad electrode 226p and the data pad electrode 227p is exposed to the outside by forming an open hole H.

One or a plurality of open holes H may be provided.

In this case, the interlayer insulating layer 215b may be used as an etch stopper of the Ag etchant. That is, by forming the open hole H in the interlayer insulating film 215b of the pad region after the first electrode 218 is patterned, it is possible to fundamentally prevent damage to the pad electrode by the Ag etchant. However, the present invention is not limited thereto, and the upper pad electrode made of ITO is crystallized during heat treatment of the passivation layer 215c to have etch selectivity to the Ag etchant, and in this case, before patterning of the first electrode 218 . An open hole H may be formed.

As a result, reliability is improved, and defects are reduced and productivity is improved.

In this case, the gate pad electrode 226p according to the second embodiment of the present invention may have a triple-layer structure of upper, middle, and lower gate pad electrodes 226pc, 226pb, and 226pa, and the data pad electrode 227p is , may have a triple-layer structure of the middle and lower data pad electrodes 227pc, 227pb, and 227pa.

Hereinafter, a method of manufacturing an organic light emitting display device according to a second embodiment of the present invention configured as described above will be described in detail with reference to the drawings.

7A to 7I are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to the second embodiment of the present invention shown in FIG. 6A, sequentially illustrating a method of manufacturing a TFT substrate in the display area.

8A to 8G are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to the second embodiment of the present invention shown in FIG. 6B, sequentially illustrating a method of manufacturing a TFT substrate in the pad region. .

In this case, the method of manufacturing the TFT substrate of the pad region shown in FIGS. 8A to 8F shows, for example, a case in which an open hole is formed in the interlayer insulating film of the pad region after the first electrode is patterned.

As shown in FIGS. 7A and 8A , a substrate 210 made of an insulating material such as a transparent glass material or a transparent plastic or polymer film having excellent flexibility is prepared.

In addition, although not shown in detail, a TFT and a storage capacitor are formed in each of the red, green, and blue sub-pixels of the substrate 210 .

First, a buffer layer is formed on the substrate 210 .

In this case, the buffer layer may be formed to protect the thin film transistor from impurities such as alkali ions leaking from the substrate 210 during crystallization of the semiconductor layer, and may be formed of a silicon oxide film.

Next, a semiconductor thin film is formed on the substrate 210 on which the buffer layer is formed.

The semiconductor thin film may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

In this case, polycrystalline silicon may be formed by depositing amorphous silicon on the substrate 210 and then using various crystallization methods. When an oxide semiconductor is used as a semiconductor thin film, a predetermined heat treatment process may be performed after depositing the oxide semiconductor. .

Thereafter, the semiconductor layer 224 made of the semiconductor thin film is formed on the substrate 210 of the display area by selectively removing the semiconductor thin film through a photolithography process.

Next, as shown in FIGS. 7B and 8B , a gate insulating layer 215a, a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate 210 on which the semiconductor layer 224 is formed.

In this case, the second conductive layer is formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), A low-resistance opaque conductive material such as neodymium (Nd) or an alloy thereof may be used. However, they may have a multilayer structure comprising two conductive films having different physical properties. In particular, the second embodiment of the present invention is characterized in that Cu is used as the second conductive film.

As the first conductive layer, MoTi may be used to form the lower gate wiring and the pad electrode. However, the present invention is not limited thereto, and as the first conductive layer, other materials may be used as long as the contact characteristics between Cu and the lower layer are enhanced.

As the third conductive layer, ITO may be used to form the upper gate wiring and the pad electrode. However, the present invention is not limited thereto, and the third conductive layer may not be formed.

Thereafter, by selectively removing the first conductive layer, the second conductive layer, and the third conductive layer through a photolithography process, the gate including the first conductive layer, the second conductive layer, and the third conductive layer is formed on the substrate 210 of the display area. A gate line (not shown) including an electrode 221 and a first storage electrode 209 are formed, while a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate 210 in the pad region. A gate pad electrode 226p and a data pad electrode 227p are formed.

However, the present invention is not limited thereto, and the gate line including the semiconductor layer 224 and the gate electrode 221 , the first storage electrode 209 , the gate pad electrode 226p and the data pad electrode 227p are It can also be formed through one photolithography process.

Also, when the gate line including the gate electrode 221, the first storage electrode 209, the gate pad electrode 226p, and the data pad electrode 227p are patterned, the lower gate insulating layer 215a may be patterned together. have.

In this case, the gate electrode 221 may have a triple-layer structure of upper, middle, and lower gate electrodes 221c, 221b, and 221a, and the first storage electrode 209 includes the upper, middle, and lower first storage electrodes 209c. , 209b, 209a) may have a triple-layer structure.

In addition, the gate pad electrode 226p may have a triple-layer structure of upper, middle, and lower gate pad electrodes 226pc, 226pb, and 226pa, and the data pad electrode 227p includes the upper, middle, and lower data pad electrodes 227pc. , 227pb, 227pa) may have a triple-layer structure.

Next, as shown in FIGS. 7C and 8C , a substrate (with a gate line including a gate electrode 221 , a first storage electrode 209 , a gate pad electrode 226p , and a data pad electrode 227p formed thereon) 210) An interlayer insulating film 215b made of a silicon nitride film or a silicon oxide film is formed on the entire surface.

Then, the interlayer insulating layer 215b and the gate insulating layer 215a are selectively patterned through a photolithography process to form a first contact hole 240a exposing the source/drain regions of the semiconductor layer 224 while the data pad A jumping hole 240b exposing one end of the electrode 227p is formed.

Next, as shown in FIGS. 7D and 8D , a fourth conductive film is formed on the entire surface of the substrate 210 on which the interlayer insulating film 215b is formed, and then the fourth conductive film is selectively removed through a photolithography process to form a display area. A data line made of a fourth conductive layer, that is, source/drain electrodes 222 and 223, a driving voltage line (not shown), a data line 229, and a second storage electrode 219 are formed on the substrate 210 of the .

In this case, the fourth conductive layer is formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) to form a data line. ) or a low-resistance opaque conductive material such as an alloy thereof may be used. However, they may have a multilayer structure comprising two conductive films having different physical properties.

The source/drain electrodes 222 and 223 are respectively electrically connected to the source/drain region of the semiconductor layer 224 through the first contact hole, and the second storage electrode 219 has the interlayer insulating layer 215b interposed therebetween. A storage capacitor is formed by overlapping a portion of the lower first storage electrode 209 .

Also, the data pad electrode 227p is electrically connected to the data line 229 of the display area through the jumping hole.

Thereafter, as shown in FIGS. 7E and 8E , the source/drain electrodes 222 and 223 , the driving voltage line, the data line 229 and the second storage electrode 219 are formed on the substrate 210 of the display area. A planarization layer 215c made of an organic insulating material is formed.

In this case, as described above, in the case of the second embodiment of the present invention, the planarization layer 215c is formed in a state in which the protective layer is not formed on the data line. Accordingly, the number of masks can be reduced by one, thereby providing the effect of improving productivity.

Then, the second contact hole 240c exposing the drain electrode 223 is formed by selectively patterning the planarization layer 215c through a photolithography process.

Next, as shown in FIG. 7F , a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer are formed on the entire surface of the substrate 210 on which the planarization layer 215c is formed.

However, the present invention is not limited thereto, and as an example, only a single layer of the fifth conductive film may be formed on the entire surface of the substrate 210 on which the planarization film 215c is formed.

The fifth conductive layer and the seventh conductive layer may be formed of a transparent conductive material such as ITO or IZO.

The sixth conductive layer may be formed of aluminum (Al), silver (Ag), gold (Au), platinum (Pt), chromium (Cr), or an alloy containing these.

Thereafter, the first electrode 218 and the auxiliary electrode composed of the fifth conductive film, the sixth conductive film, and the seventh conductive film are selectively removed through a photolithography process. (225). In this case, in the pad region, the interlayer insulating film 215b acts as an etch stopper for the Ag etchant.

In this case, the first electrode 218 may be composed of a lower first electrode 218a, a reflective layer 218b, and an upper first electrode 218c each of a fifth conductive film, a sixth conductive film, and a seventh conductive film. have.

In addition, the auxiliary electrode 225 may be composed of a lower auxiliary electrode 225a, an intermediate auxiliary electrode 225b, and an upper auxiliary electrode 225c each made of a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer. .

The first electrode 218 as the anode is electrically connected to the drain electrode 223 of the driving TFT through the second contact hole.

Also, the first electrode 218 is formed on the substrate 210 to correspond to each of the red, green, and blue sub-pixels.

Thereafter, as shown in FIG. 8F , the interlayer insulating film 215b in the pad region is selectively removed to form an open hole H exposing a portion of the gate pad electrode 226p and the data pad electrode 227p to the outside. will do

One or a plurality of open holes H may be provided.

In this way, after the first electrode 218 is patterned, an open hole H is formed in the interlayer insulating film 215b of the pad region to fundamentally prevent damage to the pad electrode by the Ag etchant when the first electrode 218 is patterned. be able to do

Next, as shown in FIGS. 7G and 8G , a bank 215e is formed on the substrate 210 in the display area where the first electrode 218 and the auxiliary electrode 225 are formed.

In this case, the bank 215e defines an opening by enclosing the edge of the first electrode 218 like a weir, and is made of an organic insulating material or an inorganic insulating material. The bank 215e may also be made of a photosensitive material including a black pigment, and in this case, the bank 215e serves as a light blocking member.

In addition, the bank 215e further includes a second opening exposing a portion of the auxiliary electrode 225 .

Then, as shown in FIG. 7H , the barrier ribs 235 are formed on the substrate 210 on which the banks 215e are formed.

The barrier rib 235 is formed on the auxiliary electrode 225 .

In this case, the partition wall 235 may have an inverted taper shape in which the cross-sectional area becomes smaller from the upper part to the lower part. For example, an angle between the side surface of the barrier rib 235 and the auxiliary electrode 225 may be 20 degrees to 80 degrees.

Next, as shown in FIG. 7I , the organic compound layer 230 is formed by evaporation on the substrate 210 on which the barrier ribs 235 are formed.

In this case, the barrier rib 235 forms an electrode contact hole exposing the auxiliary electrode 225 in the organic compound layer 230 . The organic compound layer 230 is formed on the upper portion of the barrier rib 235 due to the shading effect, and is not formed under the upper portion of the barrier rib 235 . Accordingly, an electrode contact hole is formed in the organic compound layer 230 .

Although not shown, for this, first, a hole injection layer and a hole transport layer are sequentially formed on the substrate 210 .

In this case, the hole injection layer and the hole transport layer are formed in common in the red, green, and blue sub-pixels, and serve to smoothly inject and transport holes. In this case, any one of the hole injection layer and the hole transport layer may be omitted.

Next, a light emitting layer is formed on the substrate 210 on which the hole transport layer is formed.

In this case, the emission layer may include a red emission layer, a green emission layer, and a blue emission layer corresponding to the red, green, and blue sub-pixels.

Next, an electron transport layer is formed on the substrate 210 on which the light emitting layer is formed.

In this case, the electron transport layer is commonly formed in the red, green, and blue sub-pixels on the light emitting layer, and serves to facilitate electron transport.

In this case, an electron injection layer may be further formed on the electron transport layer to facilitate electron injection.

Then, the second electrode 228 made of the eighth conductive film is formed by sputtering on the substrate 210 on which the electron transport layer is formed.

At this time, an eighth conductive layer is deposited not only on the lower portion of the barrier rib 235 but also on the side surfaces, thereby forming a contact between the auxiliary electrode 225 and the second electrode 228 .

Meanwhile, as described above, an open hole may be formed before patterning of the first electrode, which will be described in detail with reference to the drawings.

9A to 9F are cross-sectional views sequentially illustrating another method of manufacturing the organic light emitting display device according to the second embodiment of the present invention shown in FIG. 6B.

In this case, FIGS. 9A to 9F show, for example, a method of manufacturing a TFT substrate in a pad region when an open hole is formed before patterning of the first electrode. Accordingly, the method of manufacturing the TFT substrate of the display area will be referred to the descriptions shown in FIGS. 7A to 7I.

As shown in FIG. 9A , a semiconductor thin film is formed on the substrate 210 .

Thereafter, the semiconductor layer 224 made of the semiconductor thin film is formed on the substrate 210 of the display area by selectively removing the semiconductor thin film through a photolithography process.

Next, as shown in FIG. 9B , a gate insulating layer 215a, a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate 210 on which the semiconductor layer 224 is formed.

In this case, the second conductive layer is formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), A low-resistance opaque conductive material such as neodymium (Nd) or an alloy thereof may be used. However, they may have a multilayer structure comprising two conductive films having different physical properties. In particular, the second embodiment of the present invention is characterized in that Cu is used as the second conductive film.

As the first conductive layer, MoTi may be used to form the lower gate wiring and the pad electrode. However, the present invention is not limited thereto, and as the first conductive layer, other materials may be used as long as the contact characteristics between Cu and the lower layer are enhanced.

As the third conductive layer, ITO may be used to form the upper gate wiring and the pad electrode.

Thereafter, as described above, the first conductive layer, the second conductive layer, and the third conductive layer are selectively removed from the first conductive layer, the second conductive layer, and the third conductive layer through the photolithography process to form the first conductive layer, the second conductive layer, and the third conductive layer on the substrate 210 of the display area. A gate line including a gate electrode 221 made of a film and a first storage electrode 209 are formed, while a first conductive film, a second conductive film, and a third conductive film are formed on the substrate 210 in the pad region. A gate pad electrode 226p and a data pad electrode 227p are formed.

However, the present invention is not limited thereto, and the gate line including the semiconductor layer 224 and the gate electrode 221 , the first storage electrode 209 , the gate pad electrode 226p and the data pad electrode 227p are It can also be formed through one photolithography process.

Also, when the gate line including the gate electrode 221, the first storage electrode 209, the gate pad electrode 226p, and the data pad electrode 227p are patterned, the lower gate insulating layer 215a may be patterned together. have.

In this case, the gate electrode 221 may have a triple-layer structure of upper, middle, and lower gate electrodes 221c, 221b, and 221a, and the first storage electrode 209 includes the upper, middle, and lower first storage electrodes 209c. , 209b, 209a) may have a triple-layer structure.

In addition, the gate pad electrode 226p may have a triple-layer structure of upper, middle, and lower gate pad electrodes 226pc, 226pb, and 226pa, and the data pad electrode 227p includes the upper, middle, and lower data pad electrodes 227pc. , 227pb, 227pa) may have a triple-layer structure.

Next, as shown in FIG. 9C, the front surface of the substrate 210 on which the gate line including the gate electrode 221, the first storage electrode 209, the gate pad electrode 226p, and the data pad electrode 227p are formed. An interlayer insulating film 215b made of a silicon nitride film or a silicon oxide film is formed thereon.

Then, the first contact hole 240a exposing the source/drain region of the semiconductor layer 224 is formed by selectively patterning the interlayer insulating layer 215b and the gate insulating layer 215a through a photolithography process.

At the same time, an open hole H exposing a portion of the gate pad electrode 226p and the data pad electrode 227p to the outside is formed, and a jumping hole 240b exposing one end of the data pad electrode 227p is formed. do.

One or a plurality of open holes H and jumping holes 240b may be provided.

Next, as shown in FIG. 9D , a fourth conductive film is formed on the entire surface of the substrate 210 on which the interlayer insulating film 215b is formed, and then the fourth conductive film is selectively removed through a photolithography process to form the substrate ( A data line made of a fourth conductive layer, ie, source/drain electrodes 222 and 223 , a driving voltage line, a data line 229 , and a second storage electrode 219 are formed on the 210 .

The source/drain electrodes 222 and 223 are respectively electrically connected to the source/drain region of the semiconductor layer 224 through the first contact hole, and the second storage electrode 219 has the interlayer insulating layer 215b interposed therebetween. A storage capacitor is formed by overlapping a portion of the lower first storage electrode 209 .

Also, the data pad electrode 227p is electrically connected to the data line 229 of the display area through the jumping hole.

Thereafter, as shown in FIG. 9E , the organic insulating material is disposed on the substrate 210 of the display area in which the source/drain electrodes 222 and 223 , the driving voltage line, the data line 229 , and the second storage electrode 219 are formed. A planarization film 215c made of

In this case, a predetermined annealing process is performed on the planarization film 215c made of photoacrylic. At this time, the ITO of the upper gate pad electrode 226pc and the data pad electrode 227pc of the pad region is crystallized.

Then, the second contact hole 240c exposing the drain electrode 223 is formed by selectively patterning the planarization layer 215c through a photolithography process.

Next, as described above, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer are formed on the entire surface of the substrate 210 on which the planarization layer 215c is formed.

However, the present invention is not limited thereto, and as an example, only a single layer of the fifth conductive film may be formed on the entire surface of the substrate 210 on which the planarization film 215c is formed.

The fifth conductive layer and the seventh conductive layer may be formed of a transparent conductive material such as ITO or IZO.

The sixth conductive layer may be formed of aluminum (Al), silver (Ag), gold (Au), platinum (Pt), chromium (Cr), or an alloy containing these.

Thereafter, the first electrode 218 and the auxiliary electrode composed of the fifth conductive film, the sixth conductive film, and the seventh conductive film are selectively removed through a photolithography process. (225).

In this case, the upper gate pad electrode 226pc and the data pad electrode 227pc of the pad region are made of crystallized ITO, and thus have etch selectivity to the Ag etchant, and thus the first electrode 218 and the auxiliary electrode ( 225), damage to the pad electrode by the Ag etchant is prevented.

In this case, the first electrode 218 may be composed of a lower first electrode 218a, a reflective layer 218b, and an upper first electrode 218c each of a fifth conductive film, a sixth conductive film, and a seventh conductive film. have.

In addition, the auxiliary electrode 225 may be composed of a lower auxiliary electrode 225a, an intermediate auxiliary electrode 225b, and an upper auxiliary electrode 225c each made of a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer. .

The first electrode 218 as the anode is electrically connected to the drain electrode 223 of the driving TFT through the second contact hole.

Also, the first electrode 218 is formed on the substrate 210 to correspond to each of the red, green, and blue sub-pixels.

Thereafter, as shown in FIG. 9F , a predetermined bank 215e is formed on the substrate 210 in the display area where the first electrode 218 and the auxiliary electrode 225 are formed.

In this case, the bank 215e further includes a second opening exposing a portion of the auxiliary electrode 225 .

Then, a barrier rib 235 is formed on the substrate 210 on which the bank 215e is formed.

The barrier rib 235 is formed on the auxiliary electrode 225 .

Next, the second electrode 228 including the organic compound layer 230 and the eighth conductive layer is formed on the substrate 210 on which the barrier rib 235 is formed.

At this time, an eighth conductive layer is deposited not only on the lower portion of the barrier rib 235 but also on the side surfaces, thereby forming a contact between the auxiliary electrode 225 and the second electrode 228 .

The organic light emitting diode is sealed with a predetermined thin film encapsulation layer on the thus manufactured organic light emitting diode.

A polarization film may be provided on the upper surface of the thin film encapsulation layer to improve contrast by reducing reflection of external light of the organic light emitting display device. In this case, as the polarizing film, a circular polarizing film prepared by bonding multiple linear polarizing films or retardation films may be used.

10A and 10B are cross-sectional views schematically showing a part of the structure of an organic light emitting display device according to a third embodiment of the present invention, and are substantially the same as the above-described second embodiment of the present invention except for the structure of the pad region. It has the same composition.

In this case, FIG. 10A shows, for example, one sub-pixel including a TFT unit and a capacitor forming unit of the organic light emitting display device, and FIG. 10B shows a gate pad region and a part of the data pad region in order. In particular, FIG. 10B illustrates a data pad area including a part of the display area as an example for convenience of description.

In particular, FIG. 10A illustrates one sub-pixel of an organic light emitting display device of a top emission type using a TFT having a coplanar structure as an example. However, the present invention is not limited to the TFT having a coplanar structure.

Referring to FIG. 10A , a top light emitting organic light emitting display device according to a third embodiment of the present invention includes a substrate 310 , a driving thin film transistor DT, an organic light emitting diode, and an auxiliary electrode line VSSLa. .

As in the first and second embodiments, the driving thin film transistor DT includes a semiconductor layer 324 , a gate electrode 321 , a source electrode 322 , and a drain electrode 323 .

The semiconductor layer 324 may be formed of an amorphous silicon film or a polycrystalline silicon film obtained by crystallizing amorphous silicon.

In this case, a buffer layer (not shown) may be further formed between the substrate 310 and the semiconductor layer 324 .

A gate insulating film 315a made of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ) is formed on the semiconductor layer 324 , and a gate line (not shown) including a gate electrode 321 and the first A sustain electrode 309 is formed.

At this time, the gate wiring according to the third embodiment of the present invention, that is, the gate electrode 321 , the gate line, and the first sustain electrode 309 include a low-resistance material having etch selectivity to the Ag etchant such as Al. characterized.

For example, the gate wiring according to the third embodiment of the present invention may be formed of three or more multi-layers including upper and lower layers for enhancing contact characteristics on the upper and lower parts of Al. However, the present invention is not limited thereto, and the gate wiring according to the third embodiment of the present invention may be configured as a double layer including only a lower layer under Al.

In this case, the gate electrode 321 may have a triple-layer structure of upper, middle, and lower gate electrodes 321c, 321b, and 321a, and the first storage electrode 309 includes the upper, middle, and lower first storage electrodes 309c. , 309b, 309a) may have a triple-layer structure.

For example, the gate wiring according to the third embodiment of the present invention may have a triple-layer structure of Ti/Al/Ti having an etch selectivity to an Ag etchant. In this case, subsequent processes may be performed after the interlayer insulating film in the pad region is opened, but the present invention is not limited thereto.

An interlayer insulating film 315b made of a silicon nitride film or a silicon oxide film is formed on the gate electrode 321, the gate line, and the first storage electrode 309, and a data line (not shown) and a driving voltage line (not shown) are formed thereon. ), source/drain electrodes 322 and 323 , and a second storage electrode 319 are formed.

The source electrode 322 and the drain electrode 323 are formed to be spaced apart from each other by a predetermined interval, and are electrically connected to the semiconductor layer 324 . More specifically, semiconductor layer contact holes exposing the semiconductor layer 324 are formed in the gate insulating layer 315a and the interlayer insulating layer 315b, and the source/drain electrodes 322 and 323 are connected through the semiconductor layer contact hole. It is electrically connected to the semiconductor layer 324 .

In this case, the second storage electrode 319 overlaps a portion of the first storage electrode 309 with the interlayer insulating layer 315b interposed therebetween to form a storage capacitor.

A planarization layer 315c is formed on the substrate 310 on which the data line, the driving voltage line, the source/drain electrodes 322 and 323 and the second storage electrode 319 are formed.

That is, the third embodiment of the present invention is characterized in that the planarization layer 315c made of an organic insulating material is formed in a state in which the protective layer is not formed on the data wiring, as in the second embodiment of the present invention described above. Accordingly, the number of masks can be reduced by one, thereby providing the effect of improving productivity.

Next, the organic light emitting diode includes a first electrode 318 , an organic compound layer 330 , and a second electrode 328 .

The organic light emitting diode is electrically connected to the driving thin film transistor DT. More specifically, in the planarization layer 315c formed on the driving thin film transistor DT, a drain contact hole exposing the drain electrode 323 of the driving thin film transistor DT is formed. The organic light emitting diode is electrically connected to the drain electrode 323 of the driving thin film transistor DT through the drain contact hole.

The first electrode 318 supplies a current (or voltage) to the organic compound layer 330 , and defines a light emitting region of a predetermined area.

Also, the first electrode 318 serves as an anode. For example, the first electrode 318 according to the third embodiment of the present invention includes upper and lower first electrodes 318c and 318a and a reflective layer between the upper first electrode 318c and the lower first electrode 318a ( 318b) may have a triple-layer structure. However, the present invention is not limited thereto.

A bank 315e is formed on the substrate 310 on which the first electrode 318 is formed. In the third embodiment of the present invention, the bank 315e further includes a second opening exposing a part of the auxiliary electrode 325, which will be described later.

The organic compound layer 330 is formed between the first electrode 318 and the second electrode 328 .

At this time, although FIG. 10A illustrates an example in which the organic compound layer 330 is formed on the entire surface of the substrate 310 , the present invention is not limited thereto, and the organic compound layer 330 is formed only on the first electrode 318 . can be

The second electrode 328 serves as a cathode.

In addition, as in the first and second embodiments of the present invention described above, the auxiliary electrode line VSSLa is formed on the same layer as the first electrode 318 in order to reduce the resistance of the second electrode 328 . Here, the auxiliary electrode line VSSLa includes the above-described auxiliary electrode 325 and the barrier rib 335 .

The auxiliary electrode 325 is formed to be spaced apart on the same layer as the first electrode 318 . For example, the auxiliary electrode 325 may be continuously extended in one direction to be connected to an external VSS pad (not shown).

The auxiliary electrode 325 is substantially the same as the first electrode 318 and has a triple-layer structure of upper, middle, and lower auxiliary electrodes 325c, 325b, and 325a. 325c) may be contacted directly. That is, the second electrode 328 is deposited up to the lower portion of the barrier rib 335 to make contact with the auxiliary electrode 325 . However, the present invention is not limited thereto.

The barrier rib 335 is formed on the auxiliary electrode 325 .

An organic compound layer 330 and a second electrode 328 are sequentially stacked on the partition wall 335 .

At this time, as the second electrode 328 is deposited through sputtering, the second electrode 328 is deposited on the side as well as the lower portion of the barrier rib 335 to make contact with the auxiliary electrode 325 .

Referring to FIG. 10B , in the edge region of the TFT substrate 310 constituting the display region as described above, a gate pad electrode 326p and a data pad electrode 327p electrically connected to the gate line and the data line 329, respectively, are formed. is formed, and the scan signal and data signal applied from an external driving circuit unit (not shown) are transmitted to the gate line and the data line 329, respectively.

At this time, in the third embodiment of the present invention, the gate line and the data line 329 are extended toward the driving circuit, and the corresponding gate pad electrode 326p and the data pad electrode ( 327p), characterized in that it is connected. Accordingly, the gate line and the data line 329 directly receive the scan signal and the data signal from the driving circuit unit through the gate pad electrode 326p and the data pad electrode 327p, respectively.

In this case, the data pad electrode 327p may be connected to the data line 329 formed in different layers using a jumping structure. That is, the data pad electrode 327p is electrically connected to the data line 329 of the display area through the jumping hole.

The pad electrode according to the third embodiment of the present invention, that is, the gate pad electrode 326p and the data pad electrode 327p, is formed on the same layer as the gate wiring in the display area, but has a triple-layer structure substantially identical to that of the gate wiring; For example, it is characterized in that it is formed in a triple layer structure of Ti/Al/Ti.

That is, in the third embodiment of the present invention, a tri-layer structure of Ti/Al/Ti having etching selectivity with respect to the Ag alloy etchant is applied to the gate pad electrode 326p and the data pad electrode 327p in the pad region. , when the interlayer insulating layer 315b is patterned, the interlayer insulating layer 315b of the pad region is opened to expose the gate pad electrode 326p and the data pad electrode 327p to the outside.

In this case, not only the surfaces of the gate pad electrode 326p and the data pad electrode 327p, but also the interlayer insulating layer 315b positioned on one side thereof may be removed to expose the side surfaces of the gate pad electrode 326p and the data pad electrode 327p.

However, the present invention is not limited thereto, and after the first electrode is patterned, the interlayer insulating layer 315b of the pad region may be opened through a separate process. In this case, the interlayer insulating layer 315b may be used as an etch stopper of the Ag etchant.

In this case, the gate pad electrode 326p according to the third embodiment of the present invention may have a triple-layer structure of upper, middle, and lower gate pad electrodes 326pc, 326pb, and 326pa, and the data pad electrode 327p is , may have a triple-layer structure of the middle and lower data pad electrodes 327pc, 327pb, and 327pa.

Hereinafter, a method of manufacturing an organic light emitting display device according to a third embodiment of the present invention configured as described above will be described in detail with reference to the drawings.

11A to 11I are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to the third embodiment of the present invention shown in FIG. 10A, sequentially illustrating a method of manufacturing a TFT substrate in the display area.

12A to 12G are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to the third embodiment of the present invention shown in FIG. 10B, sequentially illustrating a method of manufacturing a TFT substrate in the pad region. .

In this case, the method of manufacturing the TFT substrate in the pad region shown in FIGS. 12A to 12F shows, for example, the case in which the interlayer insulating film in the pad region is opened through a separate process after the first electrode is patterned.

11A and 12A , a buffer layer is formed on the substrate 310 .

Next, a semiconductor thin film is formed on the substrate 310 on which the buffer layer is formed.

The semiconductor thin film may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

Thereafter, a semiconductor layer 324 made of a semiconductor thin film is formed on the substrate 310 of the display area by selectively removing the semiconductor thin film through a photolithography process.

Next, as shown in FIGS. 11B and 12B , a gate insulating layer 315a, a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate 310 on which the semiconductor layer 324 is formed.

In this case, the second conductive layer is formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), A low-resistance opaque conductive material such as neodymium (Nd) or an alloy thereof may be used. However, they may have a multilayer structure comprising two conductive films having different physical properties. In particular, the third embodiment of the present invention is characterized in that Al having etch selectivity is used for the Ag etchant as the second conductive film.

As the first conductive layer, Ti may be used to form the lower gate wiring and the pad electrode. However, the present invention is not limited thereto, and other materials may be used for the first conductive layer as long as the contact characteristics between Al and the lower layer are enhanced.

As the third conductive layer, Ti may be used to form the upper gate wiring and the pad electrode. However, the present invention is not limited thereto, and the third conductive layer may not be formed.

Thereafter, by selectively removing the first conductive layer, the second conductive layer, and the third conductive layer through a photolithography process, the gate including the first conductive layer, the second conductive layer, and the third conductive layer is formed on the substrate 310 of the display area. A gate line (not shown) including an electrode 321 and a first storage electrode 309 are formed, while the first conductive layer, the second conductive layer, and the third conductive layer are formed on the substrate 310 in the pad region. A gate pad electrode 326p and a data pad electrode 327p are formed.

In this case, the gate electrode 321 may have a triple-layer structure of upper, middle, and lower gate electrodes 321c, 321b, and 321a, and the first storage electrode 309 includes the upper, middle, and lower first storage electrodes 309c. , 309b, 309a) may have a triple-layer structure.

In addition, the gate pad electrode 326p may have a triple-layer structure of upper, middle, and lower gate pad electrodes 326pc, 326pb, and 326pa, and the data pad electrode 327p includes the upper, middle, and lower data pad electrodes 327pc. , 327pb, 327pa) may have a triple-layer structure.

Next, as shown in FIGS. 11C and 12C , a substrate (with a gate line including a gate electrode 321 , a first sustain electrode 309 , a gate pad electrode 326p , and a data pad electrode 327p formed thereon) 310) An interlayer insulating film 315b made of a silicon nitride film or a silicon oxide film is formed on the entire surface.

Then, the interlayer insulating layer 315b and the gate insulating layer 315a are selectively patterned through a photolithography process to form a first contact hole 340a exposing the source/drain regions of the semiconductor layer 324 while the data pad is formed. A jumping hole 340b exposing one end of the electrode 327p is formed.

Next, as shown in FIGS. 11D and 12D , a fourth conductive film is formed on the entire surface of the substrate 310 on which the interlayer insulating film 315b is formed, and then the fourth conductive film is selectively removed through a photolithography process to form a display area. A data line made of a fourth conductive layer, that is, source/drain electrodes 322 and 323, a driving voltage line (not shown), a data line 329, and a second storage electrode 319 are formed on the substrate 310 of the .

The source/drain electrodes 322 and 323 are respectively electrically connected to the source/drain regions of the semiconductor layer 324 through the first contact hole, and the second storage electrode 319 has the interlayer insulating layer 315b interposed therebetween. A storage capacitor is formed by overlapping a portion of the lower first storage electrode 309 .

Also, the data pad electrode 327p is electrically connected to the data line 329 of the display area through the jumping hole.

Thereafter, as shown in FIGS. 11E and 12E , on the substrate 310 of the display area on which the source/drain electrodes 322 and 323 , the driving voltage line, the data line 329 , and the second storage electrode 319 are formed. A planarization layer 315c made of an organic insulating material is formed.

In this case, as described above, in the case of the third embodiment of the present invention, the planarization layer 315c is formed in a state in which the protective layer is not formed on the data line. Accordingly, the number of masks can be reduced by one, thereby providing the effect of improving productivity.

Then, the second contact hole 340c exposing the drain electrode 323 is formed by selectively patterning the planarization layer 315c through a photolithography process.

Next, as shown in FIG. 11F , a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer are formed on the entire surface of the substrate 310 on which the planarization layer 315c is formed.

However, the present invention is not limited thereto, and as an example, only a single layer of the fifth conductive film may be formed on the entire surface of the substrate 310 on which the planarization film 315c is formed.

The fifth conductive layer and the seventh conductive layer may be formed of a transparent conductive material such as ITO or IZO.

The sixth conductive layer may be formed of aluminum (Al), silver (Ag), gold (Au), platinum (Pt), chromium (Cr), or an alloy containing these.

Thereafter, the first electrode 318 and the auxiliary electrode composed of the fifth conductive film, the sixth conductive film and the seventh conductive film are selectively removed through a photolithography process. (325). In this case, in the pad region, the interlayer insulating film 315b acts as an etch stopper for the Ag etchant.

In this case, the first electrode 318 may be composed of a lower first electrode 318a, a reflective layer 318b, and an upper first electrode 318c, each of a fifth conductive film, a sixth conductive film, and a seventh conductive film. have.

In addition, the auxiliary electrode 325 may be composed of a lower auxiliary electrode 325a, an intermediate auxiliary electrode 325b, and an upper auxiliary electrode 325c each made of a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer. .

The first electrode 318 as the anode is electrically connected to the drain electrode 323 of the driving TFT through the second contact hole.

Thereafter, as shown in FIG. 12F , the interlayer insulating film 315b in the pad region is selectively removed to partially open the gate pad electrode 326p and the data pad electrode 327p to expose them to the outside.

In this case, not only the surfaces of the gate pad electrode 326p and the data pad electrode 327p, but also the interlayer insulating layer 315b positioned on one side thereof may be removed to expose the side surfaces of the gate pad electrode 326p and the data pad electrode 327p.

Next, as shown in FIGS. 11G and 12G , a predetermined bank 315e is formed on the substrate 310 of the display area in which the first electrode 318 and the auxiliary electrode 325 are formed.

In this case, the bank 315e further includes a second opening exposing a part of the auxiliary electrode 325 .

Then, as shown in FIG. 11H , the barrier ribs 335 are formed on the substrate 310 on which the banks 315e are formed.

The barrier rib 335 is formed on the auxiliary electrode 325 .

In this case, the partition wall 335 may have an inverted taper shape in which the cross-sectional area decreases from the upper part to the lower part. For example, an angle between the side surface of the barrier rib 335 and the auxiliary electrode 325 may be formed from 20 degrees to 80 degrees.

Next, as shown in FIG. 11I , the organic compound layer 330 is formed by evaporation on the substrate 310 on which the barrier ribs 335 are formed.

Then, the second electrode 328 made of the eighth conductive layer is formed by sputtering on the substrate 310 on which the organic compound layer 330 is formed.

At this time, the eighth conductive layer is deposited not only on the lower portion of the barrier rib 335 but also on the side surfaces, thereby making contact between the auxiliary electrode 325 and the second electrode 328 .

Meanwhile, as described above, subsequent processes may be performed after the interlayer insulating film in the pad region is opened, which will be described in detail with reference to the drawings.

13A to 13F are cross-sectional views sequentially illustrating another method of manufacturing an organic light emitting display device according to the third embodiment of the present invention shown in FIG. 10B.

At this time, FIGS. 13A to 13F show, for example, a method of manufacturing a TFT substrate in the pad region when subsequent processes are performed after the interlayer insulating film in the pad region is opened. Accordingly, the method of manufacturing the TFT substrate of the display area will be referred to the descriptions shown in FIGS. 11A to 11I.

As shown in FIG. 13A , a semiconductor thin film is formed on the substrate 310 .

Thereafter, a semiconductor layer 324 made of a semiconductor thin film is formed on the substrate 310 of the display area by selectively removing the semiconductor thin film through a photolithography process.

Next, as shown in FIG. 13B , a gate insulating layer 315a, a first conductive layer, a second conductive layer, and a third conductive layer are formed on the substrate 310 on which the semiconductor layer 324 is formed.

In this case, the second conductive layer is formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), A low-resistance opaque conductive material such as neodymium (Nd) or an alloy thereof may be used. However, they may have a multilayer structure comprising two conductive films having different physical properties. In particular, in the second embodiment of the present invention, Al having etch selectivity is used for the Ag etchant as the second conductive film.

As the first conductive layer, Ti may be used to form the lower gate wiring and the pad electrode. However, the present invention is not limited thereto, and other materials may be used for the first conductive layer as long as the contact characteristics between Al and the lower layer are enhanced.

As the third conductive layer, Ti may be used to form the upper gate wiring and the pad electrode. However, the present invention is not limited thereto, and the third conductive layer may not be formed.

Thereafter, as described above, the first conductive layer, the second conductive layer, and the third conductive layer are selectively removed from the first conductive layer, the second conductive layer, and the third conductive layer through the photolithography process to form the first conductive layer, the second conductive layer, and the third conductive layer on the substrate 310 of the display area. A gate line including a gate electrode 321 made of a film and a first sustain electrode 309 are formed, while a first conductive film, a second conductive film, and a third conductive film are formed on the substrate 310 in the pad region. A gate pad electrode 326p and a data pad electrode 327p are formed.

In this case, the gate electrode 321 may have a triple-layer structure of upper, middle, and lower gate electrodes 321c, 321b, and 321a, and the first storage electrode 309 includes the upper, middle, and lower first storage electrodes 309c. , 309b, 309a) may have a triple-layer structure.

In addition, the gate pad electrode 326p may have a triple-layer structure of upper, middle, and lower gate pad electrodes 326pc, 326pb, and 326pa, and the data pad electrode 327p includes the upper, middle, and lower data pad electrodes 327pc. , 327pb, 327pa) may have a triple-layer structure.

Next, as shown in FIG. 13C, the front surface of the substrate 310 on which the gate line including the gate electrode 321, the first sustain electrode 309, the gate pad electrode 326p, and the data pad electrode 327p are formed. An interlayer insulating film 315b made of a silicon nitride film or a silicon oxide film is formed thereon.

Then, the first contact hole 340a exposing the source/drain region of the semiconductor layer 324 is formed by selectively patterning the interlayer insulating layer 315b and the gate insulating layer 315a through a photolithography process.

At the same time, the gate pad electrode 326p and the data pad electrode 327p are opened and exposed to the outside, and a jumping hole 340b exposing one end of the data pad electrode 327p is formed.

In this case, not only the surfaces of the gate pad electrode 326p and the data pad electrode 327p, but also the interlayer insulating layer 315b positioned on one side thereof may be removed to expose the side surfaces of the gate pad electrode 326p and the data pad electrode 327p.

Next, as shown in FIG. 13D , a fourth conductive film is formed on the entire surface of the substrate 310 on which the interlayer insulating film 315b is formed, and then the fourth conductive film is selectively removed through a photolithography process. A data line made of a fourth conductive layer, ie, source/drain electrodes 322 and 323 , a driving voltage line, a data line 329 , and a second storage electrode 319 are formed on the 310 .

The source/drain electrodes 322 and 323 are respectively electrically connected to the source/drain regions of the semiconductor layer 324 through the first contact hole, and the second storage electrode 319 has the interlayer insulating layer 315b interposed therebetween. A storage capacitor is formed by overlapping a portion of the lower first storage electrode 309 .

Also, the data pad electrode 327p is electrically connected to the data line 329 of the display area through the jumping hole.

Thereafter, as shown in FIG. 13E , an organic insulating material is formed on the substrate 310 of the display area in which the source/drain electrodes 322 and 323 , the driving voltage line, the data line 329 , and the second storage electrode 319 are formed. A planarization film 315c made of

Then, the second contact hole 340c exposing the drain electrode 323 is formed by selectively patterning the planarization layer 315c through a photolithography process.

Next, as described above, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer are formed on the entire surface of the substrate 310 on which the planarization layer 315c is formed.

However, the present invention is not limited thereto, and as an example, only a single layer of the fifth conductive film may be formed on the entire surface of the substrate 310 on which the planarization film 315c is formed.

The fifth conductive layer and the seventh conductive layer may be formed of a transparent conductive material such as ITO or IZO.

The sixth conductive layer may be formed of aluminum (Al), silver (Ag), gold (Au), platinum (Pt), chromium (Cr), or an alloy containing these.

Thereafter, the first electrode 318 and the auxiliary electrode composed of the fifth conductive film, the sixth conductive film and the seventh conductive film are selectively removed through a photolithography process. (325).

In this case, the gate pad electrode 326pc and the data pad electrode 327pc in the pad region have a tri-layer structure of Ti/Al/Ti having etch selectivity with respect to the Ag etchant, and thus the first electrode 318 and the auxiliary electrode During the patterning of (325), damage by the Ag etchant is prevented.

In this case, the first electrode 318 may be composed of a lower first electrode 318a, a reflective layer 318b, and an upper first electrode 318c, each of a fifth conductive film, a sixth conductive film, and a seventh conductive film. have.

In addition, the auxiliary electrode 325 may be composed of a lower auxiliary electrode 325a, an intermediate auxiliary electrode 325b, and an upper auxiliary electrode 325c each made of a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer. .

The first electrode 318 as the anode is electrically connected to the drain electrode 323 of the driving TFT through the second contact hole.

Thereafter, as shown in FIG. 13F , a predetermined bank 315e is formed on the substrate 310 of the display area in which the first electrode 318 and the auxiliary electrode 325 are formed.

In this case, the bank 315e further includes a second opening exposing a part of the auxiliary electrode 325 .

Then, a barrier rib 335 is formed on the substrate 310 on which the bank 315e is formed.

The barrier rib 335 is formed on the auxiliary electrode 325 .

Next, the second electrode 328 including the organic compound layer 330 and the eighth conductive layer is formed on the substrate 310 on which the barrier rib 335 is formed.

At this time, the eighth conductive layer is deposited not only on the lower portion of the barrier rib 335 but also on the side surfaces, thereby making contact between the auxiliary electrode 325 and the second electrode 328 .

The organic light emitting diode is sealed with a predetermined thin film encapsulation layer on the thus manufactured organic light emitting diode.

A polarizing film may be provided on the upper surface of the thin film encapsulation layer to improve contrast by reducing reflection of external light of the organic light emitting display device. In this case, as the polarizing film, a circular polarizing film prepared by bonding multiple linear polarizing films or retardation films may be used.

14A and 14B are cross-sectional views schematically illustrating a part of a structure of an organic light emitting display device according to a fourth embodiment of the present invention, except for the structure of the pad region, according to the second and third embodiments of the present invention. has substantially the same configuration as

In this case, FIG. 14A shows, for example, one sub-pixel including a TFT unit and a capacitor forming unit of the organic light emitting display device, and FIG. 14B shows a gate pad region and a part of the data pad region in order.

In particular, FIG. 14A illustrates one sub-pixel of an organic light emitting display device of a top emission type using a TFT having a coplanar structure as an example. However, the present invention is not limited to the TFT having a coplanar structure.

Referring to FIG. 14A , a top light emitting organic light emitting display device according to a fourth embodiment of the present invention includes a substrate 410 , a driving thin film transistor DT, an organic light emitting diode, and an auxiliary electrode line VSSLa. .

As in the first, second, and third embodiments described above, the driving thin film transistor DT includes a semiconductor layer 424 , a gate electrode 421 , a source electrode 422 , and a drain electrode 423 .

The semiconductor layer 424 may be formed of an amorphous silicon film or a polycrystalline silicon film obtained by crystallizing amorphous silicon.

In this case, a buffer layer (not shown) may be further formed between the substrate 410 and the semiconductor layer 424 .

A gate insulating film 415a made of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ) is formed on the semiconductor layer 424 , and a gate line (not shown) including a gate electrode 421 and the first A sustain electrode 409 is formed.

The gate electrode 421, the gate line, and the first storage electrode 409 are formed of a first metal material having a low resistance characteristic, for example, aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), It may be formed as a single layer or multiple layers made of gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy thereof.

An interlayer insulating film 415b made of a silicon nitride film or a silicon oxide film is formed on the gate electrode 421, the gate line, and the first storage electrode 409, and a data line (not shown) and a driving voltage line (not shown) are formed thereon. ), source/drain electrodes 422 and 423 , and a second storage electrode 419 are formed.

The source electrode 422 and the drain electrode 423 are formed to be spaced apart from each other by a predetermined interval, and are electrically connected to the semiconductor layer 424 . More specifically, semiconductor layer contact holes exposing the semiconductor layer 424 are formed in the gate insulating layer 415a and the interlayer insulating layer 415b, and the source/drain electrodes 422 and 423 are connected through the semiconductor layer contact hole. It is electrically connected to the semiconductor layer 424 .

In this case, the second storage electrode 419 overlaps a portion of the first storage electrode 409 with the interlayer insulating layer 415b interposed therebetween to form a storage capacitor.

At this time, the data wiring according to the fourth embodiment of the present invention, that is, the data line, the driving voltage line, the source/drain electrodes 422 and 423 and the second storage electrode 419, exhibits etch selectivity to the Ag etchant like Al. It is characterized in that it comprises a low-resistance material having.

For example, the data line according to the fourth embodiment of the present invention may be formed of three or more multi-layers including upper and lower layers for enhancing contact characteristics on the upper and lower parts of Al. However, the present invention is not limited thereto, and the data line according to the fourth embodiment of the present invention may be configured as a double layer including only a lower layer under Al.

In this case, the source electrode 422 may have a triple-layer structure of upper, middle, and lower source electrodes 422c, 422b, and 422a, and the drain electrode 423 includes the upper, middle, and lower drain electrodes 423c, 423b, and 423a. ) may have a triple layer structure.

Also, the second storage electrode 419 may have a triple-layer structure of upper, middle, and lower second storage electrodes 419c, 419b, and 419a.

For example, the data line according to the fourth exemplary embodiment of the present invention may have a triple-layer structure of Ti/Al/Ti having an etch selectivity to an Ag etchant.

A planarization layer 415c is formed on the substrate 410 on which the data line, the driving voltage line, the source/drain electrodes 422 and 423 and the second storage electrode 419 are formed.

That is, the fourth embodiment of the present invention is characterized in that the planarization film 415c made of an organic insulating material is formed on the data wiring in the same manner as the second and third embodiments of the present invention described above. do it with Accordingly, the number of masks can be reduced by one, thereby providing the effect of improving productivity.

Next, the organic light emitting diode includes a first electrode 418 , an organic compound layer 430 , and a second electrode 428 .

The organic light emitting diode is electrically connected to the driving thin film transistor DT. More specifically, in the planarization layer 415c formed on the driving thin film transistor DT, a drain contact hole exposing the drain electrode 423 of the driving thin film transistor DT is formed. The organic light emitting diode is electrically connected to the drain electrode 423 of the driving thin film transistor DT through the drain contact hole.

The first electrode 418 supplies a current (or voltage) to the organic compound layer 430 and defines a light emitting region of a predetermined area.

Also, the first electrode 418 serves as an anode. For example, the first electrode 418 according to the fourth embodiment of the present invention includes upper and lower first electrodes 418c and 418a and a reflective layer between the upper first electrode 418c and the lower first electrode 418a ( 418b) may have a triple layer structure. However, the present invention is not limited thereto.

A bank 415e is formed on the substrate 410 on which the first electrode 418 is formed. In the fourth embodiment of the present invention, the bank 415e further includes a second opening exposing a part of the auxiliary electrode 425, which will be described later.

The organic compound layer 430 is formed between the first electrode 418 and the second electrode 428 .

At this time, although FIG. 14A illustrates an example in which the organic compound layer 430 is formed on the entire surface of the substrate 410 , as described above, the present invention is not limited thereto.

The second electrode 428 serves as a cathode.

And, in order to reduce the resistance of the second electrode 428 in the same manner as in the first, second, and third embodiments of the present invention described above, the auxiliary electrode line VSSLa is formed on the same layer as the first electrode 418 . has been Here, the auxiliary electrode line VSSLa includes the above-described auxiliary electrode 425 and the barrier rib 435 .

The auxiliary electrode 425 is formed to be spaced apart on the same layer as the first electrode 418 . For example, the auxiliary electrode 425 may be continuously extended in one direction to be connected to an external VSS pad (not shown).

The auxiliary electrode 425 has a triple-layer structure of upper, middle, and lower auxiliary electrodes 425c, 425b, and 425a substantially the same as the first electrode 418, so that the second electrode 428 is deposited as an upper auxiliary electrode ( 425c) can be contacted directly. That is, the second electrode 428 is deposited up to the lower portion of the barrier rib 435 to make contact with the auxiliary electrode 425 . However, the present invention is not limited thereto.

The barrier rib 435 is formed on the auxiliary electrode 425 .

An organic compound layer 430 and a second electrode 428 are sequentially stacked on the barrier rib 435 .

At this time, as the second electrode 428 is deposited through sputtering, it is deposited on the side surface as well as the lower portion of the barrier rib 435 to make contact with the auxiliary electrode 425 .

Referring to FIG. 14B, in the edge region of the TFT substrate 410 on which the display region is configured as described above, the gate pad electrode 426p electrically connected to the gate line and the data line, respectively, in the same manner as in the first embodiment of the present invention. ) and a data pad electrode 427p are formed, and a scan signal and a data signal applied from an external driving circuit unit (not shown) are transmitted to the gate line and the data line, respectively.

That is, the gate line and the data line extend toward the driving circuit unit and are connected to the corresponding gate pad line 416p and the data pad line 417p, respectively. The gate pad line 416p and the data pad line 417p are electrically connected to the gate pad electrode 426p and the data pad electrode 427p, respectively. Accordingly, the gate line and the data line receive the scan signal and the data signal respectively from the driving circuit unit through the gate pad electrode 426p and the data pad electrode 427p.

At this time, the gate pad electrode 426p and the data pad electrode 427p according to the fourth embodiment of the present invention are formed on the same layer as the data line of the display area, but have substantially the same triple-layer structure as the data line, for example, Ti It is characterized in that it is formed in a triple layer structure of /Al/Ti.

That is, in the fourth embodiment of the present invention, the tri-layer structure of Ti/Al/Ti having etching selectivity for the Ag alloy etchant is applied to the gate pad electrode 426p and the data pad electrode 427p in the pad region. characterized.

At this time, the gate pad electrode 426p according to the fourth embodiment of the present invention may be composed of upper, middle, and lower gate pad electrodes 426pc, 426pb, and 426pa, and the data pad electrode 427p includes the upper, middle and lower gate pad electrodes 426pc, 426pb, and 426pa. The lower data pad electrodes 427pc, 427pb, and 427pa may have a triple-layer structure.

Hereinafter, a method of manufacturing an organic light emitting display device according to a fourth embodiment of the present invention configured as described above will be described in detail with reference to the drawings.

15A to 15I are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to the fourth embodiment of the present invention shown in FIG. 14A, sequentially illustrating a method of manufacturing a TFT substrate in the display area.

16A to 16D are cross-sectional views sequentially illustrating a method of manufacturing an organic light emitting display device according to the fourth embodiment of the present invention shown in FIG. 14B, sequentially illustrating a method of manufacturing a TFT substrate in the pad region. .

As shown in FIGS. 15A and 16A , a buffer layer is formed on the substrate 410 .

Next, a semiconductor thin film is formed on the substrate 410 on which the buffer layer is formed.

The semiconductor thin film may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

Thereafter, a semiconductor layer 424 made of a semiconductor thin film is formed on the substrate 410 of the display area by selectively removing the semiconductor thin film through a photolithography process.

Next, as shown in FIGS. 15B and 16B , a gate insulating layer 415a and a first conductive layer are formed on the substrate 410 on which the semiconductor layer 424 is formed.

Thereafter, by selectively removing the first conductive layer through a photolithography process, the gate line (not shown) including the gate electrode 421 made of the first conductive layer on the substrate 410 of the display area and the first storage electrode 409 . ) is formed, and a gate pad line 416p and a data pad line 417p made of a first conductive layer are formed on the substrate 410 in the pad region.

However, the present invention is not limited thereto, and the gate line including the semiconductor layer 424 and the gate electrode 421 , the first storage electrode 409 , the gate pad line 416p and the data pad line 417p are It can also be formed through one photolithography process.

In addition, when the gate line including the gate electrode 421, the first storage electrode 409, the gate pad line 416p, and the data pad line 417p are patterned, the lower gate insulating layer 415a may be patterned together. have.

Next, as shown in FIGS. 15C and 16C , a substrate including a gate line including a gate electrode 421 , a first storage electrode 409 , a gate pad line 416p and a data pad line 417p formed thereon ( 410) An interlayer insulating film 415b made of a silicon nitride film or a silicon oxide film is formed on the entire surface.

Then, a first contact hole 440a exposing the source/drain region of the semiconductor layer 424 is formed by selectively patterning the interlayer insulating layer 415b and the gate insulating layer 415a through a photolithography process, while the gate pad A second contact hole 450b and a third contact hole 450c exposing portions of the line 416p and the data pad line 417p are respectively formed.

Next, as shown in FIGS. 15D and 16D , a second conductive film, a third conductive film, and a fourth conductive film are formed on the entire surface of the substrate 410 on which the interlayer insulating film 415b is formed, and then through a photolithography process. By selectively removing the second conductive layer, the third conductive layer, and the fourth conductive layer, the data line including the second conductive layer, the third conductive layer, and the fourth conductive layer, that is, the source/drain electrode, is formed on the substrate 410 of the display area. 422 and 423 , a driving voltage line (not shown), a data line (not shown), and a second storage electrode 419 are formed.

At the same time, a pad electrode including a second conductive layer, a third conductive layer, and a fourth conductive layer, that is, a gate pad electrode 426p and a data pad electrode 427p is formed on the substrate 410 in the pad region.

The source/drain electrodes 422 and 423 are electrically connected to the source/drain regions of the semiconductor layer 424 through the first contact hole, respectively, and the second storage electrode 419 has the interlayer insulating layer 415b interposed therebetween. A storage capacitor is formed by overlapping a portion of the lower first storage electrode 409 .

In this case, the third conductive layer is formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), and nickel (Ni) to form an intermediate layer data line and a pad electrode. , a low-resistance opaque conductive material such as neodymium (Nd) or an alloy thereof may be used. However, they may have a multilayer structure comprising two conductive films having different physical properties. In particular, the fourth embodiment of the present invention is characterized in that Al having etch selectivity is used for the Ag etchant as the third conductive layer.

In addition, as the second conductive layer, Ti may be used to form the lower data line and the pad electrode. However, the present invention is not limited thereto, and other materials may be used for the second conductive layer as long as the contact characteristics with the lower layer are enhanced.

As the fourth conductive layer, Ti may be used to form an upper data line and a pad electrode. However, the present invention is not limited thereto, and the data line and the pad electrode of the present invention may be formed of a double layer of the second conductive layer and the third conductive layer.

For example, the data line and the pad electrode according to the fourth embodiment of the present invention may have a triple-layer structure of Ti/Al/Ti having etch selectivity to an Ag etchant.

In this case, the source electrode 422 may have a triple-layer structure of upper, middle, and lower source electrodes 422c, 422b, and 422a, and the drain electrode 423 includes the upper, middle, and lower drain electrodes 423c, 423b, and 423a. ) may have a triple layer structure.

Also, the second storage electrode 419 may have a triple-layer structure of upper, middle, and lower second storage electrodes 419c, 419b, and 419a.

The gate pad electrode 426p according to the fourth embodiment of the present invention may include upper, middle, and lower gate pad electrodes 426pc, 426pb, and 426pa, and the data pad electrode 427p includes upper, middle, and lower data layers. The pad electrodes 427pc, 427pb, and 427pa may have a triple-layer structure.

Thereafter, as shown in FIG. 15E , the organic insulating material is disposed on the substrate 410 of the display area in which the source/drain electrodes 422 and 423 , the driving voltage line, the data line 429 , and the second storage electrode 419 are formed. A planarization film 415c made of

At this time, in the same manner as in the second and third embodiments of the present invention, in the fourth embodiment of the present invention, the planarization film 415c is formed on the data line in a state where the protective film is not formed. Accordingly, the number of masks can be reduced by one, thereby providing the effect of improving productivity.

Then, a fourth contact hole 440d exposing the drain electrode 423 is formed by selectively patterning the planarization layer 415c through a photolithography process.

Next, as shown in FIG. 15F , a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer are formed on the entire surface of the substrate 410 on which the planarization layer 415c is formed.

However, the present invention is not limited thereto. For example, only a single layer of the fifth conductive film may be formed on the entire surface of the substrate 410 on which the planarization film 415c is formed.

The fifth conductive layer and the seventh conductive layer may be formed of a transparent conductive material such as ITO or IZO.

The sixth conductive layer may be formed of aluminum (Al), silver (Ag), gold (Au), platinum (Pt), chromium (Cr), or an alloy containing these.

Thereafter, the first electrode 418 and the auxiliary electrode composed of the fifth conductive film, the sixth conductive film, and the seventh conductive film are selectively removed through a photolithography process. (425) is formed.

At this time, the first electrode 418 may be composed of a lower first electrode 418a, a reflective layer 418b, and an upper first electrode 418c each comprising a fifth conductive film, a sixth conductive film, and a seventh conductive film. have.

In addition, the auxiliary electrode 425 may include a lower auxiliary electrode 425a, an intermediate auxiliary electrode 425b, and an upper auxiliary electrode 425c, each comprising a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer. .

The first electrode 418 as the anode is electrically connected to the drain electrode 423 of the driving TFT through the fourth contact hole.

Thereafter, as shown in FIG. 15G , a bank 415e is formed on the substrate 410 in the display area where the first electrode 418 and the auxiliary electrode 425 are formed.

In this case, the bank 415e further includes a second opening exposing a part of the auxiliary electrode 425 .

Then, as shown in FIG. 15H , a barrier rib 435 is formed on the substrate 410 on which the bank 415e is formed.

The barrier rib 435 is formed on the auxiliary electrode 425 .

Next, as shown in FIG. 15I , the organic compound layer 430 is formed by evaporation on the substrate 410 on which the barrier ribs 435 are formed.

Then, the second electrode 428 made of the eighth conductive layer is formed by sputtering on the substrate 410 on which the organic compound layer 430 is formed.

At this time, an eighth conductive layer is deposited not only on the lower portion of the barrier rib 435 , but also on the side surfaces to form a contact between the auxiliary electrode 425 and the second electrode 428 .

The organic light emitting diode is sealed with a predetermined thin film encapsulation layer on the thus manufactured organic light emitting diode.

A polarizing film may be provided on the upper surface of the thin film encapsulation layer to improve contrast by reducing reflection of external light of the organic light emitting display device. In this case, as the polarizing film, a circular polarizing film prepared by bonding multiple linear polarizing films or retardation films may be used.

Although many matters are specifically described in the above description, these should be construed as examples of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention should not be defined by the described embodiments, but should be defined by the claims and equivalents to the claims.

116p, 416p: gate pad line 117p, 417p: data pad line
118,218,318,418: first electrode 125,225,325,425: auxiliary electrode
126p, 226p, 326p, 426p: gate pad electrode
127p, 227p, 327p, 427p: data pad electrode
128,228,328,428: second electrode 130,230,330,430: organic compound layer

Claims (15)

a substrate divided into a display area and a pad area;
a thin film transistor formed on the substrate of the display area;
a gate pad electrode and a data pad electrode formed in a pad region of the same layer on which the gate wiring of the thin film transistor is formed;
an interlayer insulating film formed on the substrate on which the gate pad electrode and the data pad electrode are formed and exposing a portion of the gate pad electrode and the data pad electrode to the outside;
a first electrode and an auxiliary electrode formed on the substrate of the display area in which the thin film transistor is formed;
a bank surrounding an edge of the first electrode to define an opening while exposing a part of the auxiliary electrode;
an organic compound layer formed on the substrate on which the banks are formed; and
a second electrode formed on the substrate on which the organic compound layer is formed and in contact with the exposed auxiliary electrode;
The first electrode and the auxiliary electrode include Ag,
wherein the gate pad electrode and the data pad electrode have a triple layer structure of ITO/Cu/MoTi from above, and the ITO of the gate pad electrode and the data pad electrode is crystallized. The method of claim 1,
The first electrode and the auxiliary electrode have a triple layer structure including an upper first electrode made of a transparent conductive material, a lower first electrode made of a transparent conductive material, and a reflective layer containing Ag between the upper first electrode and the lower first electrode. An organic light emitting display device, characterized in that consisting of. delete The organic layer according to claim 1, wherein the interlayer insulating layer of the pad region comprises an open hole exposing a portion of the gate pad electrode and the data pad electrode to the outside and a jumping hole exposing one end of the data pad electrode. electroluminescent display. 5. The organic light emitting display device of claim 4, wherein the data pad electrode is electrically connected to the data line of the thin film transistor through the jumping hole. The organic light emitting display device according to claim 1, wherein not only the surfaces of the gate pad electrode and the data pad electrode, but also the interlayer insulating film positioned on one side is removed so that the side surfaces are also exposed to the outside. delete providing a substrate divided into a display area and a pad area;
forming a gate line on the substrate of the display area and at the same time forming a gate pad electrode and a data pad electrode on the substrate of the pad area;
forming an interlayer insulating layer on the substrate on which the gate wiring, the gate pad electrode, and the data pad electrode are formed;
forming a data line on the substrate of the display area on which the interlayer insulating layer is formed;
forming a planarization layer on the substrate on which the data lines are formed;
after forming a first electrode and an auxiliary electrode on the substrate of the display area on which the planarization layer is formed, selectively removing the interlayer insulating layer of the pad area to expose a portion of the gate pad electrode and the data pad electrode to the outside;
forming a bank exposing a portion of the auxiliary electrode on the substrate on which the first electrode and the auxiliary electrode are formed;
forming an organic compound layer on the substrate on which the bank is formed; and
forming a second electrode on the substrate on which the organic compound layer is formed so as to be in contact with the exposed auxiliary electrode;
The first electrode and the auxiliary electrode include Ag,
The gate pad electrode and the data pad electrode are formed in a triple layer structure of ITO/Cu/MoTi from above, and the ITO of the gate pad electrode and the data pad electrode is crystallized by annealing the planarization layer. Way. providing a substrate divided into a display area and a pad area;
forming a gate line on the substrate of the display area and at the same time forming a gate pad electrode and a data pad electrode on the substrate of the pad area;
forming an interlayer insulating layer on the substrate on which the gate wiring, the gate pad electrode, and the data pad electrode are formed;
exposing portions of the gate pad electrode and the data pad electrode to the outside by selectively removing the insulating interlayer in the pad region;
forming a data line on the substrate of the display area on which the interlayer insulating layer is formed;
forming a planarization layer on the substrate on which the data lines are formed;
forming a first electrode and an auxiliary electrode on the substrate of the display area on which the planarization layer is formed;
forming a bank exposing a portion of the auxiliary electrode on the substrate on which the first electrode and the auxiliary electrode are formed;
forming an organic compound layer on the substrate on which the bank is formed; and
forming a second electrode on the substrate on which the organic compound layer is formed so as to be in contact with the exposed auxiliary electrode;
The first electrode and the auxiliary electrode include Ag,
The gate pad electrode and the data pad electrode are formed in a triple layer structure of ITO/Cu/MoTi from above, and the ITO of the gate pad electrode and the data pad electrode is crystallized by annealing the planarization layer. Way. 10. The method according to claim 8 or 9,
and forming a jumping hole exposing one end of the data pad electrode by selectively removing the interlayer insulating layer. 10. The method according to claim 8 or 9,
The first electrode and the auxiliary electrode have a triple layer structure including an upper first electrode made of a transparent conductive material, a lower first electrode made of a transparent conductive material, and a reflective layer containing Ag between the upper first electrode and the lower first electrode. A method of manufacturing an organic light emitting display device comprising: delete 11. The method of claim 10, wherein an open hole exposing a portion of the gate pad electrode and the data pad electrode to the outside is formed by selectively removing the insulating interlayer in the pad region. 11. The method of claim 10, wherein the interlayer insulating film in the pad region is selectively removed to expose not only the surfaces of the gate pad electrode and the data pad electrode, but also side surfaces of the gate pad electrode and the data pad electrode. delete

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