KR20080048379A - An array substrate for lcd and method of fabricating the same - Google Patents

Abstract

An array substrate for an LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to minimize wavy noise and the leakage current property of a TFT(Thin Film Transistor), thereby simplifying the manufacturing process of a mask. A gate line(104) is formed on the upper portion of a substrate. A TFT includes a gate electrode connected with the gate line. A gate insulating layer is formed on the upper portion of the gate electrode. An active layer is formed on the upper portion of the gate insulating layer. An ohmic contact layer is formed on the upper portion of the ohmic contact layer. Source and drain electrodes are formed on the upper portion of the ohmic contact layer. A pixel electrode(148) is connected with the drain electrode electrically. A data line(142) is connected with the source electrode electrically and crossed with the gate line. A common electrode(150) is separated from the pixel electrode. A passivation layer is located between the pixel electrode and the common electrode, and the source electrode and the drain electrode.

Description

Array substrate for LCD and manufacturing method thereof {An array substrate for LCD and method of fabricating the same}

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device,

2 is an enlarged plan view showing one pixel of a conventional array substrate for a transverse electric field type liquid crystal display device;

3A to 3H, 4A to 4H, 5A to 5H, and 6A to 6H are cut along II-II, III-III, IV-IV, and V-V of FIG. It is the process cross section shown in order

7 is an enlarged plan view of one pixel of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

8A, 8B, 8C, and 8D are cross-sectional views taken along the lines VIII-VIII, VIII-VIII, VIII-VIII, VIII-VIII, and according to the first embodiment of the present invention. ,

9A to 9I, 10A to 10I, 11A to 11I, and 12A to 12I are cut along the line VIII-VII, VIII-VIII, VIII-VIII, VIII-VIII of FIG. Process cross-sectional view shown in accordance with the process sequence according to the first embodiment,

13A and 13B and 13C and FIG. 13D are cross-sectional views taken along the line VIII-VIII, VIII-VIII, VIII-VIII, VIII-VIII of FIG. 7, respectively.

14A to 14C, 15A to 15C, 16A to 16C, and 17A to 17C are cross-sectional views illustrating a process sequence according to a third embodiment of the present invention.

18 is a cross-sectional view showing another example of the array substrate according to the present invention.

 <Brief description of the main parts of the drawing>

100 substrate 102 gate electrode

104: gate wiring 106: gate pad electrode

108: common electrode connection portion 124: active layer

128: buffer metal layer 138: source electrode

140: drain electrode 142: data wiring

148: pixel electrode 150: common electrode

152: gate pad electrode 148a: pixel electrode connection portion

109: common wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of improving productivity and image quality characteristics, and a manufacturing method thereof.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The LCD includes an upper color filter substrate on which a common electrode is formed, an array substrate on a bottom on which a pixel electrode is formed, and a liquid crystal filled between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are disposed up-down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal by an applied electric field.

However, the liquid crystal drive by the electric field applied up-down has a disadvantage that the viewing angle characteristics are not excellent. Therefore, new techniques have been proposed to overcome the above disadvantages. The liquid crystal display device to be described below has an advantage of excellent viewing angle characteristics by a liquid crystal driving method using a transverse electric field.

Hereinafter, a general transverse electric field type liquid crystal display device will be described with reference to FIG. 1.

1 is an enlarged cross-sectional view illustrating a cross section of a general transverse electric field type liquid crystal display device.

As illustrated, the thin film transistor T, the common electrode 30, and the pixel electrode 32 are configured for each of the plurality of pixels P defined in the transparent lower substrate 10.

The thin film transistor T may include a gate electrode 14, a semiconductor layer 18 having an insulating layer 16 disposed on the gate electrode 14, and a source configured to be spaced apart from each other on the semiconductor layer 18. And drain electrodes 20 and 22.

In the above-described configuration, the common electrode 30 and the pixel electrode 32 are both spaced apart from each other in parallel on the lower substrate 10.

Although not shown, a gate line (not shown) extending along one side of the pixel P and a data line (not shown) extending in a direction perpendicular thereto are formed, and a voltage is applied to the common electrode 30. The common wiring (not shown) to apply is comprised.

A transparent upper substrate 40 is positioned to be spaced apart from the lower substrate 10, and an inner surface of the upper substrate 40 corresponds to the gate wiring (not shown), the data wiring (not shown), and the thin film transistor (T). The black matrix 42 is formed in the color filter, and the color filters 34a and 34b are formed corresponding to the pixel P.

The liquid crystal layer LC is operated by the horizontal electric field 45 of the common electrode 30 and the pixel electrode 32.

Hereinafter, with reference to FIG. 2, the structure of the conventional array board for a transverse electric field type liquid crystal display device is demonstrated.

2 is a plan view schematically illustrating a configuration of an array substrate for a transverse electric field type liquid crystal display device manufactured by a conventional four mask process.

As shown in the drawing, the gate wiring 54 extending in one direction on the insulating substrate 50 and the data wiring 92 defining the pixel region P intersect with the gate wiring 54.

A gate pad 56 is formed at one end of the gate line 54, and a data pad 94 is formed at one end of the data line 92.

The common line 58 is formed at one side of the pixel region P spaced in parallel with the gate line 54.

The gate pad 56 and the data pad 94 have a transparent gate pad electrode GP and a data pad electrode DP in contact therewith, respectively.

At the intersection of the gate line 54 and the data line 92, the gate electrode 52 in contact with the gate line 54, and an active layer (amorphous silicon layer 84) disposed on the gate electrode 52. And an ohmic contact layer (not shown), a source electrode 88 spaced apart from the ohmic contact layer (not shown), connected to the data line 92, and a drain electrode 90 spaced apart from the ohmic contact layer (not shown). The thin film transistor T is constituted.

The pixel electrode PXL is formed in the pixel region P in contact with the drain electrode 90, and the common electrode Vcom connected to the common wire 58 and spaced apart from the pixel electrode PXL is formed. It is composed.

In addition, a pure amorphous silicon pattern 72 is positioned under the data line 92.

In this case, the conventional array substrate for a transverse electric field type liquid crystal display device forms the source and drain electrodes 88 and 90, the data line 92, and the active layer 84 in the same mask process. The active layer 84, the source and drain electrodes 88 and 90, and the pure amorphous silicon pattern 72 and the data wiring 92 are stacked in such a manner that the active layer 84 and the outside of the electrode and the wiring Pure amorphous silicon pattern 72 is formed in an extended form.

In this configuration, the active layer 84 may be exposed to light to generate photo-current, and the photocurrent acts as an off current in the thin film transistor T, thereby causing a thin film transistor T. Will cause a malfunction.

In addition, when a leakage current is generated by the pure amorphous silicon pattern 72 positioned below the data line 92, coupling with an electrode near the data line 92 may occur, thereby causing liquid crystal (not shown). It will distort the movement of poems).

As a result, wavy noise in which thin wavy lines appear on the screen of the liquid crystal panel is generated.

As described above, the off current (leak current) of the thin film transistor and the wavy noise of the screen, as described above, use a general method of simultaneously patterning the source and drain electrodes and the active layer. Because.

Hereinafter, a manufacturing process of a conventional array substrate for a transverse electric field type liquid crystal display device will be described with reference to the drawings.

3A to 3H, 4A to 4H, 5A to 5H, and 6A to 6H are cut along II-II, III-III, IV-IV, and V-V of FIG. It is process sectional drawing shown in order.

3A, 4A, 5A, and 6A illustrate a first mask process.

3A, 4A, 5A, and 6A, the switching region S, the pixel region P, the gate region G, the data region D, and the common signal region on the substrate 50 are shown. (CS) is defined.

The plurality of regions S, P, G, D, and CS extend in one direction corresponding to the gate region G on the defined substrate 50, and include gate pads 56 at one end thereof. A gate wiring (54 of FIG. 2) and a gate electrode 52 connected to the gate wiring 54 and positioned in the switching region S are formed.

At the same time, a common wiring 58 is formed in the common signal region CS spaced in parallel with the gate wiring 54.

In this case, the gate pad and gate wirings 56 and 54, the gate electrode 52, and the common wiring 58 may include aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), and molybdenum (Mo). It is formed by depositing one or more materials selected from a group of conductive metals including a single metal such as Al or an aluminum (Al) / chromium (Cr) (or molybdenum (Mo)).

Next, FIGS. 3B to 3F, 4B to 4F, 5B to 5F, and 6B to 6F illustrate a second mask process.

3B, 4B, 5B, and 6B, the substrate 50 including the gate wiring 54 including the gate electrode 52 and the gate pad 56 and the common wiring 58 are formed. ), The gate insulating film 60, the pure amorphous silicon layer (a-Si: H, 62), the amorphous silicon layer (n + or p + a-Si: H, 64) containing impurities and the conductive metal layer 66 To form.

The gate insulating layer 60 is formed by depositing one or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and the like, and the conductive metal layer 66 is mentioned above. It is formed by depositing one or more materials selected from one conductive metal group.

Next, a photoresist is applied on the entire surface of the substrate 50 on which the conductive metal layer 66 is formed to form the photosensitive layer 68.

Next, a mask M including the transmissive part B1, the blocking part B2, and the transflective part B3 is positioned on the spaced upper portion of the photosensitive layer 68.

In this case, the transflective portion B3 forms a slit shape or a translucent film on the mask M, thereby lowering the intensity of light or lowering the amount of light transmitted, thereby incompletely exposing the photosensitive layer.

In addition, the blocking unit B2 functions to completely block light, and the transmitting unit B1 transmits light so that the photosensitive layer 68 is completely exposed to light by a light change.

Meanwhile, the transflective portion B3 and the blocking portion B2 are positioned at both sides of the transflective portion B3 in the switching region S, and the data region D is a direction intersecting with the gate region G. ) To the blocking portion (B2).

Next, light is irradiated to the upper portion of the mask M to expose and develop a lower photosensitive layer 68.

As shown in FIGS. 3C, 4C, 5C, and 6C, first and second photosensitive patterns 70a and 70b are formed in the switching region S and the data region D, respectively.

In this case, the first photosensitive pattern 70a includes a first portion corresponding to the gate electrode 52 and a second portion thicker than the first portion.

Next, the conductive metal layer 66 exposed to the periphery of the first and second photosensitive patterns 70a and 70b, the impurity amorphous silicon layer 64 and the pure amorphous silicon layer 62 below are removed. Proceed with the process.

 In this case, depending on the type of the conductive metal layer 66, the conductive metal layer 66 and its lower layers (64, 62) may be removed at the same time, the metal layer is first etched and then the pure pure silicon of the lower through a dry etching process The process of removing the layer 62 and the amorphous silicon layer 64 containing impurities may be performed.

As shown in FIGS. 3D, 4D, 5D, and 6D, when the above-described removal process is completed, the pure amorphous silicon pattern 72 and the impurity amorphous silicon pattern (under the first photosensitive pattern 70a) may be formed. A first semiconductor pattern 76 having a stack of 74 is formed, and a first metal pattern 78 is formed on the first semiconductor pattern 76.

Under the second photosensitive pattern 70b corresponding to the data area D, a second semiconductor pattern 80 extending from the first semiconductor pattern 76 and an upper portion of the second semiconductor pattern 80 are disposed. A second metal pattern 82 extending from the first metal pattern 78 is formed.

An ashing process for exposing the lower first metal pattern 78 is performed by removing the first portion corresponding to the center of the gate electrode 52 of the first photosensitive pattern 70a.

In this case, as illustrated in FIGS. 3E, 4E, 5E, and 6E, a portion of the first metal pattern 78 corresponding to the center of the gate electrode 52 is exposed, and the first and A portion of the first and second metal patterns 78 and 82 are simultaneously exposed to the peripheries of the second photosensitive patterns 70a and 70b.

After the ashing process, a process of removing the exposed portion of the first metal pattern 78 and the impurity amorphous silicon layer 74 under the first metal pattern 78 is performed.

As shown in FIGS. 3F, 4F, 5F, and 6F, when the removal process is completed, the pure amorphous silicon pattern (the lower portion of the first semiconductor pattern 76 positioned above the gate electrode 52) (FIG. 72 of 3E functions as an active layer 84, and a part of the upper portion of the upper portion of the active layer 84 removed and separated from each other by the impurity amorphous silicon pattern 74 (FIG. 3E) of the ohmic contact layer 86 It will function.

At this time, the active layer 84 and the upper ohmic contact layer 86 are removed, and the lower active layer 84 is overetched so that impurities remain on the surface (active channel) of the active layer 84. Do not have.

Meanwhile, the divided metal patterns positioned on the ohmic contact layer 86 are referred to as source electrodes 88 and drain electrodes 90, respectively.

In this case, the second metal pattern (82 of FIG. 4E) in contact with the source electrode 88 is called a data line 92, and one end of the data line 92 is called a data pad 94.

Next, the second mask process may be completed by performing a process of removing the remaining photosensitive patterns 70a and 70b.

3G and 4G and 5G and 6G illustrate a third mask process, and includes a substrate 50 including a data line 92 including the source and drain electrodes 88 and 90 and a data pad 94. Deposition of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) on the front surface of the benzocyclobutene (BCB) and acrylic resin (resin) in some cases A protective film 96 is formed by coating one selected from the group of organic insulating materials including the organic insulating material.

Successively, the protective film 96 is patterned to expose a part of the drain electrode 90, a drain contact hole 98a, a part of the common wiring 58 and a common wiring contact hole 98b exposing a portion of the common wiring 58. A gate pad contact hole 98c exposing the gate pad 56 and a data pad contact hole 98d exposing the data pad 94 are formed.

3H, 4H, 5H, and 6H illustrate a fourth mask process, wherein indium tin oxide (ITO) and indium zinc oxide (ITO) are formed on the entire surface of the substrate 50 on which the passivation layer 96 is formed. A selected one of the transparent conductive metal groups including IZO is deposited and patterned to form the pixel electrode PXL and the common electrode Vcom in the pixel region P.

In this case, the pixel electrode PXL is formed of a plurality of vertical portions in contact with the drain electrode 90 and parallel to the data line 92. The common electrode Vcom extends to a plurality of vertical portions parallel to the data line 92 while contacting the common line 58 and spaced apart from the pixel electrode PXL.

At the same time, a gate pad electrode GP in contact with the gate pad 56 and a data pad electrode DP in contact with the data pad 94 are formed.

As described above, the array substrate for the transverse electric field type liquid crystal display device can be manufactured by the conventional four mask process.

In the above-described process, in the second mask process, the active layer 84 of pure amorphous silicon and the ohmic contact layer 86 of impurity amorphous silicon, the source and drain electrodes 88 and 90 and the data wiring 92 of the upper part are removed. In the process of forming at the same time, the second semiconductor pattern 80 is left under the data line 92, in particular, the lower pure amorphous silicon pattern 72 of the second semiconductor pattern 80 is the data line 92 The pattern is extended to both sides of the.

As mentioned above, since the lower pure amorphous silicon pattern 72 is extended on both sides of the data line 92, there is a problem in that a wavy noise is generated on the screen.

In addition, since the active layer 84 located above the gate electrode 52 is also configured to extend outward of the gate electrode 52, it is exposed by light to generate a photocurrent, that is, a leakage current. There is a problem that can cause a malfunction of the thin film transistor.

The present invention has been proposed to solve the above-described problem, and minimizes the off current characteristics of the thin film transistor due to the photocurrent by preventing the amorphous silicon layer from being exposed to the outside of the wiring, and at the same time, wavy noise. ) To achieve high picture quality.

In addition, the second object is to simplify the process by manufacturing in a three-mask process, to improve the productivity by reducing the process cost and process time.

An array substrate for a liquid crystal display device of the present invention for achieving the above object is a substrate, a gate wiring on the substrate, a gate electrode connected to the gator wiring, a gate insulating film on the gate electrode, an active on the gate insulating film A thin film transistor comprising a layer, an ohmic contact layer over the active layer, and a source and drain electrode over the ohmic contact layer, a pixel electrode electrically connected to the drain electrode, and electrically connected to the source electrode, and the gate A data line crossing the wiring, a common electrode spaced apart from the pixel electrode, and a passivation layer positioned between the pixel electrode and the common electrode and between the source electrode and the drain electrode.

The active layer is characterized in that the edge of the island formed on top of the gate electrode without departing from the edge of the gate electrode.

A lower portion of the data line further includes an extension having a first layer extending from the ohmic contact layer and a second layer extending from the active layer.

A buffer metal layer is further included between the ohmic contact layer and the source electrode and between the ohmic contact layer and the drain electrode.

The source and drain electrodes, the common electrode, and the pixel electrode may be transparent.

And an auxiliary data line extending from the source electrode on the data line.

And an extension having a lower portion of the auxiliary data line, the data line extending from the buffer metal layer, a first layer extending from the ohmic contact layer, and a second layer extending from the active layer.

And an extension part under the data line, the same layer as the active layer and the ohmic contact layer and separated from the active layer and the ohmic contact layer.

The buffer metal layer has a multilayer structure of at least three layers, and the intermediate layer of the at least three layers includes copper.

The display device may further include a pixel electrode connection part extending from the drain electrode and connected to the pixel electrode.

A method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes defining a switching region, a pixel region, a gate region, a data region, and a common signal region on a substrate, wherein the switching region, the gate region, and the common signal region are defined in the substrate. Forming a gate electrode, a gate wiring, and a common wiring, respectively, forming a gate insulating layer, an active layer, and an ohmic contact layer on the gate electrode, and forming a source and a drain electrode on the ohmic contact layer; Forming a data line electrically connected to the source electrode and crossing the gate line, forming a pixel electrode electrically connected to the drain electrode and a common electrode spaced apart from the pixel electrode; An upper portion of the gate insulating layer and the source and the drain between the pixel electrode and the common electrode; Forming a passivation layer on the active layer between the lane electrodes.

The forming of the gate insulating layer, the active layer and the ohmic contact layer, and the forming of the data line use a mask.

The method may further include forming an auxiliary data line on the data line, wherein the source electrode, the drain electrode, the common electrode, the pixel electrode, and the auxiliary data line are formed in the same mask process.

The protective film is formed by a lift-off process.

The forming of the gate insulating layer, the active layer, and the ohmic contact layer may include forming a buffer metal layer on the ohmic contact layer.

Another method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes a first mask process step of forming a gate electrode and a gate wiring on a substrate, and a gate insulating film and an active layer on the substrate including the gate electrode and the gate wiring. And a second mask process step of sequentially forming an ohmic contact layer and a data line, a third mask process step of forming a source electrode and a drain electrode, a common electrode and a pixel electrode on the substrate, and the source electrode and the drain. Forming a passivation layer on the active layer between the electrodes and between the common electrode and the pixel electrode.

The first mask process step includes forming a gate pad at one end of the gate wiring, and the second mask process step includes forming a data pad at one end of the data wiring, and the third mask. The process step includes forming an auxiliary data line over the data line, a gate pad electrode over the gate pad, and a data pad electrode over the data pad.

The second mask process may include sequentially forming the gate insulating layer, the pure amorphous silicon layer, the impurity amorphous silicon layer, and the metal layer on the substrate including the gate electrode, the gate wiring, and the gate pad; The metal layer corresponding to the gate pad is exposed on an upper portion of the metal layer, and the first portion corresponding to the active layer, the data line, and the data pad, and the region except the active layer, the data line, and the data pad. Forming a photoresist pattern corresponding to the second portion thicker than the first portion, and removing the exposed metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating layer to expose the gate pad. And removing the second portion of the photosensitive pattern. Removing the metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer using the first portion of the photosensitive pattern as an etching mask; and removing the first portion of the photosensitive pattern. Include.

The forming of the photosensitive pattern may include a mask including a transmissive part, a blocking part, and a transflective part, the transmitting part corresponding to the gate pad, and the blocking part corresponding to the active layer, the data line, and the data pad. The transflective part may correspond to an area excluding the active layer, the data line, the data pad, and the gate pad.

The second mask process may include forming an extension under the auxiliary data line and the data pad electrode, wherein the extension includes a pure amorphous silicon pattern and an impurity amorphous silicon pattern.

The first mask process may include forming a common line parallel to the gate line, wherein the common line is electrically connected to the common electrode. The second mask process step may include exposing the common wiring by removing the exposed metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating layer.

The third mask process may include forming a conductive layer on the substrate including the data line and the data pad, a first photosensitive pattern corresponding to the source and drain electrodes on the conductive layer, Forming an auxiliary data line and a second photosensitive pattern corresponding to the data pad electrode, a third photosensitive pattern corresponding to the pixel electrode and the common electrode, and a fourth photosensitive pattern corresponding to the gate pad electrode; The conductive layer is patterned using the first to fourth photosensitive patterns as an etch mask to form the source and drain electrodes, the auxiliary data line, the data pad electrode, the pixel electrode, the common electrode, and the gate pad electrode. Forming an oxide layer and removing the ohmic contact layer between the source and drain electrodes; And exposing the active layer in between, and a step of removing said first to fourth photosensitive pattern.

The forming of the passivation layer may include forming an insulating film on the substrate including the first to fourth photosensitive patterns, and selectively removing the insulating film together with the first to fourth photosensitive patterns. . The patterning of the conductive layer may include exposing the conductive layer by wet etching to expose 2,000 to 5,000 microseconds of the edge lower surface of the first to fourth photosensitive patterns.

The forming of the passivation layer may include disposing a shadow mask covering the gate pad electrode and the data pad electrode, and depositing an insulating material on the substrate except for the gate pad electrode and the data pad electrode.

The second mask process step includes forming a buffer metal layer over the ohmic contact layer, and the forming the buffer metal layer includes sequentially depositing and patterning molybdenum-titanium alloy, copper and molybdenum-titanium alloy. Steps.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment

The first embodiment of the present invention is characterized by fabricating a transverse field array substrate in which the edge of the active layer does not extend to the outside of the data line and the gate electrode in a three mask process.

Hereinafter, the configuration of the transverse field array substrate according to the present invention will be described in detail with reference to a plan view and a cross-sectional view.

7 is an enlarged plan view of a part of an array substrate for a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention, and FIGS. 8A to 8D are FIGS. 8A to 8D, respectively, of FIGS. It is sectional drawing cut along Ⅹ-Ⅹ.

As shown in the drawing, the gate wiring 104 extending in one direction on the insulating substrate 100 and having the gate pad 106 formed at one end thereof, and the pixel region P are defined by crossing the gate wiring 104. The data line 143 including the data pad 144 is formed at one end. An auxiliary data line 142 is formed on the data line 143, and a data pad electrode 146 is formed on the data pad 144. In addition, the common wiring 109 and the common electrode connecting portion 108 spaced apart from the gate wiring 104 are formed. A gate pad electrode 152 connected to the gate pad 106 is formed on the gate pad 106.

The gate electrode 102, the ohmic contact layer 126, the active layer 124, the buffer metal layer 128, the buffer metal layer 128, and the intersection of the gate line 104 and the data line 142 The thin film transistor T including the source electrode 138 and the drain electrode 140 in contact with each other is configured. A gate insulating film 110 is formed on the gate wiring 104, the gate electrode 102, and the gate pad 106 to cover them.

The buffer metal layer 128, the active layer 124, the ohmic contact layer 126, the data line 143, and the data pad 144 are patterned with the same mask, and the ohmic contact layer 126 and the active layer 124 are also patterned. ) And an extension part (B) disposed on the same layer and including layers made of the same material under the data line 143 and the data pad 144.

In this case, the buffer metal layer 128, the data line 143, and the data pad 144 may have a laminated structure of at least three layers including a molybdenum alloy (MoTi) layer disposed up and down with a copper (Cu) layer interposed therebetween. The source and drain electrodes 138 and 140 may be formed of a molybdenum alloy (MoTi) layer or a transparent metal layer such as ITO or IZO.

At this time, since the copper (Cu) layer is very low resistance, there is an advantage that can prevent the signal delay caused by the resistance of the wiring.

The pixel region P has a pixel electrode 148 electrically contacting the drain electrode 140, and a common electrode 150 spaced apart from the pixel electrode 148 in parallel with the pixel electrode 148 and electrically connected to the common wiring 109. ). The pixel electrode 148 extends from the pixel electrode connector 148a connected to the drain electrode 140. The common electrode 150 contacts the common electrode connector 108, and although not illustrated, the common electrode connector 108 is connected to the common wire 109, so that a signal from the common wire 109 is transmitted to the common electrode 150. To apply. Therefore, the common electrode 150 is electrically connected to a common electrode (not shown) of the adjacent pixel region. The common electrode 150 may be directly connected to the common wire 109. The pixel electrode connector 148a overlaps the common line 109 to form a storage capacitor Cst.

In this case, the pixel electrode 148 and the common electrode 150 may be manufactured in the same process as the source and drain electrodes 138 and 140. Also, the pixel electrode 148 and the common electrode 150 may be transparent, such as a molybdenum alloy (MoTi) layer or ITO or IZO. It can comprise with a metal layer.

The passivation layer 154 is formed on the exposed active layer 124 of the thin film transistor T and the gate insulating layer 110 between the common electrode 150 and the pixel electrode 148. ) May be formed while exposing a portion of the gate pad electrode 152 and the data pad electrode 146 through a deposition process and a lift-off process without using a separate mask process. do.

In addition, since the active layer 124 is not exposed to the light distribution device (not shown) in the above-described configuration, operation of wavy noise or thin film transistor (TFT) due to leakage current is different from the conventional art. Characterized in that the configuration does not cause defects.

Hereinafter, a manufacturing process of an array substrate for a transverse electric field type liquid crystal display device according to a first embodiment of the present invention will be described with reference to the process cross section.

9A to 9I, 10A to 10I, 11A to 11I, and 12A to 12I are cut along the line VIII-VII, VIII-VIII, VIII-VIII, VIII-VIII of FIG. It is a process cross section shown in the process sequence which concerns on 1st Example.

9A, 10A, 11A, and 12A are cross-sectional views illustrating a first mask process.

As illustrated, the switching region S, the pixel region P, the gate region G, the data region D, and the common signal region CS are defined on the substrate 100.

Aluminum (Al), aluminum alloy (AlNd), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium on the substrate 100 defining the plurality of regions S, P, G, D, and CS. Depositing one or more metals selected from conductive metal groups including (Ti), copper (Cu), tantalum (Ta) and the like to form a first conductive metal layer (not shown) and patterning the same by using a first mask process, A gate electrode 102 is formed in the switching region S, and a gate wiring (104 in FIG. 7) including a gate pad 106 is formed at one end corresponding to the gate region G.

At the same time, the common wiring (109 of FIG. 7) and the common electrode connecting unit 108 are disposed on both sides of the pixel region P at a position spaced in parallel with the gate wiring 104 (FIG. 7), that is, the common signal region CS. Form each.

9B to 9F, 10B to 10F, 11B to 11F, and 12A to 12F are cross-sectional views illustrating a second mask process in a process sequence.

9B, 10B, 11B, and 12B, the gate electrode 102, the gate pad and the gate wiring 106 (104 in Fig. 7), the common wiring (109 in Fig. 7), and the common electrode A gate insulating layer 110, a pure amorphous silicon layer (a-Si: H, 112), an impurity amorphous silicon layer (n + a-Si: H, 114), and an impurity amorphous silicon layer (n + a-Si: H, 114) on the entire surface of the substrate 100 on which the connection portion 108 is formed, The photosensitive layer 118 is formed by coating a second conductive metal layer 116 on the impurity amorphous silicon layer 114 and a photo-resist on the second conductive metal layer 116.

The gate insulating layer 110 is formed by depositing one or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

In this case, the second conductive metal layer 116 is composed of a multi-layer, the first layer of the molybdenum alloy (MoTi) layer and the second layer of the copper (Cu) layer and the third layer of the molybdenum alloy ( It is characterized by forming a layer of MoTi).

In this case, the copper (Cu) layer is used to minimize the signal delay because the specific resistance is very low. However, since copper (Cu) may be a material having high specific resistance by reacting with silicon (Si) or oxygen, as described above, an alloy of molybdenum (Mo) and titanium (Ti) is further formed on the upper and lower portions of copper. .

Meanwhile, after the photosensitive layer 118 is formed, a mask including a transmissive part B1, a blocking part B2, and a transflective part B3 is disposed on a spaced upper portion of the substrate 100 on which the photosensitive layer 118 is formed. Place M).

In this case, the blocking unit B2 corresponds to the switching region S and the data region D, and the transmission unit B1 is positioned to correspond to the common signal region CS and the gate pad 106. In other areas, the transflective portion B3 is positioned.

At this time, the area of the blocking portion B2 corresponding to the switching region S is limited within a range not exceeding the area of the gate electrode 102.

Next, a step of exposing light to the upper portion of the mask M to expose the lower photosensitive layer 116 and a continuous developing step are performed.

In this way, as illustrated in FIGS. 9C, 10C, 11C, and 12C, the photosensitive pattern 120 is formed. The photosensitive pattern 120 is completely removed to correspond to a part of the common signal region CS and the gate region G for the gate pad 106 to expose the second conductive metal layer 116 below, and the switching region. (S) and the first portion of the first thickness d1 corresponding to the original height in the data region D, the gate region G for the common signal region CS and the gate pad 106, and the switching region ( S) and a second portion of the second thickness d2 that is lower than the first thickness d1 in the remaining regions except for the data region D. FIG.

Next, as shown in FIGS. 9D, 10D, 11D, and 12D, the second conductive metal layer 116 exposed to the common signal region CS and the gate pad 106 and impurities thereunder are exposed. The amorphous silicon layer 114, the pure amorphous silicon layer 112, and the gate insulating layer 110 are removed to expose a portion of the lower common electrode connector 108 and the gate pad 106.

Next, the second portion of the photosensitive pattern 120 except for the switching region S and the data region D is removed using an ashing process.

In this way, as illustrated in FIGS. 9E, 10E, 11E, and 12E, the front surface of the substrate 100 except for the switching region S and the data region D of the substrate 100 may be formed. 2, the conductive metal layer 116 is exposed, and at the same time, a portion of the gate pad 106 and the common electrode connection unit 108 are exposed.

Meanwhile, the photosensitive pattern 122 having a lower height corresponding to the switching area S and the data area D is left.

Next, a process of removing the second conductive metal layer 116 exposed to the outside of the photosensitive pattern 122, the amorphous silicon layer 114 below and the pure amorphous silicon layer 112 below is performed.

Next, a process of removing the remaining photosensitive pattern 122 is performed.

In this case, as shown in FIGS. 9F, 10F, 11F, and 12F, the active layer 124 and the ohmic contact layer 126 are disposed on the gate electrode 102 corresponding to the switching region S. FIG. ) And a buffer metal layer 128 are formed.

In this case, a data line 143, a data pad 144, and an extension part B are formed in the data area D. The extension part B is disposed under the data line 143 and the data pad 144, and is disposed on the same layer as the ohmic contact layer 126 and the buffer metal layer 128.

9G to 9I, 10G to 10I, 11G to 11I, and 12G to 12I illustrate a third mask process. As shown in FIGS. 9G, 10G, 11G, and 12G, the buffer metal layer 128, the active layer 124, the ohmic contact layer 126, the data line 143, and the data pad 144 are formed. A third conductive metal layer (not shown) and a photosensitive layer are stacked on the entire surface of the formed substrate 100, and the first photosensitive layer is exposed and developed by a third mask process to be spaced apart from each other in correspondence with the switching region S. A photosensitive pattern 130, a second photosensitive pattern 132 corresponding to the data area D, and a plurality of vertical photosensitive patterns 134 corresponding to the pixel area P are formed. .

At the same time, a fourth photosensitive pattern 136 covering a portion of the gate pad 106 is formed.

In this case, the third conductive metal layer (not shown) is preferably characterized in that the molybdenum alloy (MoTi) layer.

Next, by removing the third conductive metal layer (not shown) exposed to the periphery of the first to fourth photosensitive patterns 130, 132, 134, and 136, source electrodes spaced below the spaced first photosensitive pattern 130. 138, the drain electrode 140, and the data line 143, the data pad 144, and the extension portion B are covered under the second photosensitive pattern 132, and at one end of the data pad electrode 146. An auxiliary data line 142 including a second electrode, and a lower portion of the third photosensitive pattern 134, the pixel electrode connection portion 148a of FIG. 7 contacting the drain electrode 140, and the pixel region P therefrom. The pixel electrode 148 having a plurality of vertical bars extending vertically, and the common electrode 150 having a plurality of vertical bars positioned between the pixel electrode 148 while being in contact with the common electrode connection unit 108. To form.

At the same time, a gate pad electrode 152 in contact with the gate pad 106 is formed under the fourth photosensitive pattern 136.

Next, a process of exposing the lower active layer 124 is performed by removing the buffer metal layer 128 and the ohmic contact layer 126 exposed between the spaced first photosensitive patterns 130.

In the above-described configuration, the active layer 124 and the ohmic contact layer 126 are covered by the gate electrode 102 except for being positioned above the gate electrode 102, and the extension part ( B) may also be blocked from light because it is configured to be wrapped in the upper data line 142.

Therefore, the active layer 124 has an advantage that no photo leakage current due to light is generated, and thus, the thin film transistor does not cause an operation failure, and when viewed as a whole panel, wavy noise due to the photo leakage current is caused. There is an advantage that does not occur.

9H, 10H, 11H, and 12H, with the first to fourth photosensitive patterns 130, 132, 134, and 136 left, silicon nitride (SiN _X ) and silicon oxide ( An inorganic insulating film including SiO ₂ ) is deposited to form a protective film 154.

In this case, the passivation layer 154 may be disposed between the upper portions of the first to fourth photosensitive patterns 130, 132, 134 and 136, the upper portion of the exposed active layer 124, and the common electrode 150 and the pixel electrode 148. Infill is formed in the form.

Next, a lift-off process of removing the first to fourth photosensitive patterns 130, 132, 134, and 136 is performed.

In this case, as shown in FIGS. 9I, 10I, 11I, and 12I, the passivation layer 154 covers the surface of the active layer 124, and the common electrode 150 and the pixel electrode ( The gate pad electrode 152 and the data pad electrode 146 may be formed in an exposed state.

Meanwhile, in FIGS. 9G, 10G, 11G, and 12G, when the third conductive metal layer is removed, the first to fourth photosensitive patterns 130, 132, 134, and 136 under the isotropic wet etching are removed. The third conductive metal layer is overetched. Therefore, the lower edges of the edges of the first to fourth photosensitive patterns 130, 132, 134, and 136 are partially exposed. The exposed lower surfaces of the first to fourth photosensitive patterns 130, 132, 134, and 136 may remove the first to fourth photosensitive patterns 130, 132, 134, and 136 after the deposition of the passivation layer 154. In the lift-off process, a stripper smoothly penetrates into the lower portions of the first to fourth photosensitive patterns 130, 132, 134, and 136, thereby removing the first to fourth photosensitive patterns 130, 132, 134, and 136. It is for easy removal. In this case, in order to facilitate the penetration of the stripper, the exposed lower surfaces of the first to fourth photosensitive patterns 130, 132, 134, and 136 preferably have a width of 2,000 to 5,000 μs.

As described above, the array substrate for the transverse electric field type liquid crystal display device according to the present invention can be manufactured by a three mask process including a lift-off process.

Although the configuration of the first embodiment described above has described an example in which the common electrode 150 and the pixel electrode 148 are formed of an opaque metal, the common electrode and the pixel electrode are formed of a transparent conductive metal layer such as ITO and IZO. You may.

Second Embodiment

The array substrate for a transverse electric field type liquid crystal display device according to the second embodiment of the present invention is characterized in that the common electrode, the pixel electrode, the source and the drain electrode are formed of a transparent material.

This will be described below with reference to FIGS. 13A to 13D.

13A to 13D are cross-sectional views taken along the lines VIII-VIII, VIII-VIII, VIII-VIII, and VIII-VIII of FIG. 7, respectively.

As shown in FIG. 2, the gate electrode 102, the active layer 124, the ohmic contact layer 126, and the buffer metal layer may be formed on one surface of the substrate 100 defined as the switching region S. And a thin film transistor T composed of a transparent source electrode 138 'and a drain electrode 140' in contact with the buffer metal layer 128. Referring to FIG.

In addition, a rod-shaped transparent pixel electrode 148 'and a transparent common electrode 150' configured to be spaced apart from each other are formed on one surface of the substrate 100 defined as the pixel region P, and one of the pixel regions P is formed. In the data region D defined at the side, the active layer 124 and the ohmic contact layer 126 are formed with an extension portion B of the same layer and the same material. A buffer metal layer 128 and The data line 143 of the same layer and the same material and the data pad 144 at one end of the data line 143 are formed. A transparent auxiliary data line surrounding the data line 143, the data pad 144, and the extension portion B, and including a data pad electrode 146 ′ at one end of the data line 143 and the data pad 144. 142 '.

In addition, a gate wiring (104 in FIG. 7) including a gate pad 106 is formed at one end in the other gate region G of the pixel region P, and is disposed above the gate pad 106. A transparent gate pad electrode 152 'is formed in contact with it. The pixel electrode connector 108 is formed in the common signal region CS.

In this case, as described above, when the buffer metal layer 128 is formed, the upper and lower molten titanium alloy (MoTi) layers may be stacked with the copper (Cu) layer having a low resistance therebetween.

Therefore, even when the source and drain electrodes 138 'and 140' are formed of a transparent conductive metal layer having a large resistance, signal delay does not occur.

Furthermore, by forming the common electrode 150 'and the pixel electrode 148' with a transparent material, there is an advantage of further improving luminance, and in particular, since the drain electrode 140 'is transparent, the common electrode 150' and the pixel electrode 148 'are emitted from the lower backlight. Since light passes through the drain electrode 140 ′, the phenomenon that the light reflected by the drain electrode 140 ′ is irradiated onto the active layer 124 does not occur.

As described above, the manufacturing method of the array substrate for a transverse electric field type liquid crystal display device according to the second embodiment of the present invention is different from that of forming the third conductive metal layer with ITO or IZO, as compared with the first embodiment described above. Only the other processes are the same, so they are omitted.

Here, the buffer metal layer 128 may be omitted. When the third conductive metal layer is formed of ITO or IZO as in the second embodiment, the buffer metal layer 128 is formed to prevent the occurrence of signal delay. It is preferable.

As described above, the transverse electric field type liquid crystal display device according to the first and second embodiments of the present invention can be manufactured in a three mask process including a lift-off process.

In this case, the first and second embodiments are characterized in that the mask process is omitted by using a lift-off process in the process of forming the insulating film, but another modification will be described below through the third embodiment. do.

Third Embodiment

The third embodiment of the present invention is characterized in that a protective film is formed on all regions except for the gate pad and the data pad by using a shadow mask.

Hereinafter, a manufacturing process of an array substrate for a transverse electric field type liquid crystal display device according to a third embodiment of the present invention will be described with reference to the process cross section.

In this case, since the second mask process is the same as the steps described in the first embodiment, the description thereof will be omitted from the third mask process.

14A to 14C, 15A to 15C, 16A to 16C, and 17A to 17C are cut along the lines VIII-VIII, VIII-VIII, VIII-VIII, VIII-VIII of FIG. The process cross section shown in the process sequence which concerns on 3rd Example.

As shown in FIGS. 14A, 15A, 16A, and 17A, the pixel region P, the switching region S, the common signal region CS, the data region D, and the gate region are formed on the substrate 100. (G) is defined.

In the first mask process, a gate electrode 102 is formed in the switching region S, and the gate pad 106 is extended to the gate region G while being in contact with the gate electrode 102. A gate wiring (104 in FIG. 7) is formed.

At the same time, the common wiring (109 of FIG. 7) and the common electrode connecting portion 108 are formed at a position parallel to the gate wiring (104 of FIG. 7).

Next, a gate insulating layer 110 is formed on the entire surface of the substrate 100 on which the gate electrode 102, the gate wiring (104 in FIG. 7), and the gate pad 106 are formed.

In the second mask process, a process of exposing the gate pad 106 and a part of the common electrode connection unit 108 is performed, and an active layer is formed on the gate insulating layer 110 corresponding to the switching region S. FIG. 124, an ohmic contact layer 126, and a buffer metal layer 128 are formed. An extension portion B, a data line 143, and a data pad 144 are formed in the data area D. The data line 143 and the data pad 144 are formed of the same layer and the same material as the buffer metal layer 128, and the extension part B is the same layer and the same as the active layer 124 and the ohmic contact layer 126. And layers of material.

Next, a third conductive metal layer ML is formed on the entire surface of the substrate 100 on which the active layer 124, the ohmic contact layer 126, the buffer metal layer 128, the data line 143, and the data pad 144 are formed. And a photosensitive layer (not shown), the photosensitive layer is exposed and developed by a third mask process, and the first photosensitive pattern 130 spaced apart from the switching area S, and the data area D The second photosensitive pattern 132 and the third photosensitive pattern 134 having a plurality of vertical portions are formed to correspond to the pixel region P.

At the same time, a fourth photosensitive pattern 136 covering a portion of the gate pad 106 is formed.

Next, a process of removing the third conductive metal layer ML exposed to the periphery of the first to fourth photosensitive patterns 130, 132, 134 and 136 and removing the first to fourth photosensitive patterns 130, 132, 134 and 136 is performed.

In this case, the third conductive metal layer ML may be formed of a molybdenum (MoTi) layer or may be formed of a transparent conductive metal layer such as ITO and IZO, as in the examples of the first and second embodiments described above.

As shown in FIGS. 14B, 15B, 16B, and 17B, the source region 138 and the drain electrode 140 are spaced apart from each other in the switching region S, and the extension portion is formed in the data region D. The auxiliary data line 142 including the data pad electrode 146 is formed at one end thereof while covering the B), the data line 143, and the data pad 144.

At the same time, the pixel region P includes a pixel electrode 148 electrically connected to the drain electrode 140 and formed in a plurality of vertical bars extending vertically to the pixel region P, and the common electrode connecting portion ( In contact with 108, a plurality of vertical bars shaped common electrodes 150 positioned between the pixel electrodes 148 are formed.

At the same time, a gate pad electrode 152 is formed in contact with the gate pad 106.

Next, a process of exposing the lower active layer 124 is performed by removing the buffer metal layer 128 and the ohmic contact layer 126 exposed between the source and drain electrodes 138 and 140.

Next, as shown in FIGS. 14C, 15C, 16C, and 17C, a shadow mask (SM) is positioned on the gate pad electrode 152 and the data pad electrode 146. A protective film 154 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiNx) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100.

Accordingly, the passivation layer 154 may be formed in all regions except for the gate pad electrode 152 and the data pad electrode 146 by simply blocking the gate pad electrode and the data pad with a shadow mask without an additional mask process. have.

Through the above-described process, the array substrate for the transverse electric field type liquid crystal display device can be manufactured in three steps according to the first to third embodiments of the present invention.

In the first to third embodiments of the present invention, the data line 143 is separated from the buffer metal layer 128 and each layer of the extension portion B is separated from the active layer 124 and the ohmic contact layer 126. However, it may be formed to be connected to each other.

Another example of this invention is shown in FIG. 18 is a cross-sectional view showing another example of the array substrate according to the present invention. The structure of FIG. 18 has been described above except that the data line 143 is connected to the buffer metal layer 128, and each pattern of the extension portion B is connected to the active layer 124 and the ohmic contact layer 126. Since it is the same as the structure of 1st-3rd embodiment mentioned, the same code | symbol is attached | subjected about the same part and the description is abbreviate | omitted.

As shown in the drawing, an extension B formed of layers connected to the active layer 124 and the ohmic contact layer 126 and having the same stacked structure as these is positioned in the data region D. Referring to FIG. The data line 143 is formed on the extension part B, and the data line 143 is connected to the buffer metal layer 128. The auxiliary data line 142 covers the data line 143 and the extension portion B, and the source electrode 138 extends from the auxiliary data line 142.

The array substrate of FIG. 18 is manufactured through the same process as that shown in the first to third embodiments.

Hereinafter, a brief description of the process according to the present invention.

First Mask Process: A common wiring is formed with the gate electrode, the gate wiring, and the gate pad.

Second mask process: The gate pad and the common wiring are exposed under the first insulating film, and the active layer, the ohmic contact layer, the buffer metal layer, the data wiring and the data pad are formed on the gate electrode.

Third mask process: a source electrode and a drain electrode in contact with the spaced buffer metal layer, a pixel electrode and a common electrode in the pixel area, a gate pad electrode in contact with the gate pad and a data pad electrode at one end in the data area To form an auxiliary data line including;

Next, a passivation layer exposing the gate pad electrode and the data pad electrode may be formed using the lift-off process described in the first and second embodiments.

As another example, as described above in the third embodiment, a passivation layer exposing the gate pad electrode and the data pad electrode may be formed using a shadow mask.

Therefore, the array substrate for a transverse electric field type liquid crystal display device according to the present invention

First, since the active layer is not exposed to backlight light, the generation of photocurrent can be suppressed, thereby preventing the malfunction of the thin film transistor and preventing high noise from occurring on the panel. There is an effect that can be implemented.

Second, because it is manufactured in a three-mask process can reduce the production cost, shorten the production time can improve the process yield, and also improve the competitiveness of the product.

Third, since a low-resistance copper layer is used as the wiring, signal delay can be prevented, thereby improving the operating characteristics of the liquid crystal panel.

Claims (29)

A substrate; A gate wiring on the substrate; A thin film transistor including a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, an ohmic contact layer on the active layer, and a source and drain electrode on the ohmic contact layer; A pixel electrode electrically connected to the drain electrode; A data line electrically connected to the source electrode and crossing the gate line; A common electrode spaced apart from the pixel electrode; And A passivation layer between the pixel electrode and the common electrode and between the source electrode and the drain electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the active layer has an island shape formed on an upper portion of the gate electrode without departing from an edge of the gate electrode. The method of claim 1, And an extension part below the data line, the extension part having a first layer extending from the ohmic contact layer and a second layer extending from the active layer. The method of claim 1, And a buffer metal layer between the ohmic contact layer and the source electrode and between the ohmic contact layer and the drain electrode. The method of claim 4, wherein And the source and drain electrodes, the common electrode and the pixel electrode are transparent. The method of claim 4, wherein And an auxiliary data line extending from the source electrode on the data line. The method of claim 6, And an extension having a lower portion of the auxiliary data line, the data line extending from the buffer metal layer, a first layer extending from the ohmic contact layer, and a second layer extending from the active layer. . The method of claim 4, wherein And an extension part under the data line, the extension layer having the same layer as the active layer and the ohmic contact layer and separated from the active layer and the ohmic contact layer. The method of claim 4, wherein And the buffer metal layer has a multilayer structure of at least three layers. The method of claim 9, And at least three intermediate layers comprise copper. The method of claim 1, And a pixel electrode connection part extending from the drain electrode and connected to the pixel electrode. Defining a switching region, a pixel region, a gate region, a data region and a common signal region on the substrate; Forming a gate electrode, a gate wiring, and a common wiring in the switching region, the gate region, and the common signal region, respectively; Forming a gate insulating layer, an active layer, and an ohmic contact layer on the gate electrode; Forming a source and a drain electrode on the ohmic contact layer; Forming a data line electrically connected to the source electrode and crossing the gate line; Forming a pixel electrode electrically connected to the drain electrode and a common electrode spaced apart from the pixel electrode; Forming a passivation layer on the gate insulating layer between the pixel electrode and the common electrode and on the active layer between the source and drain electrodes Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 12, And forming the gate insulating film, the active layer and the ohmic contact layer, and forming the data line using a single mask. The method of claim 12, And forming an auxiliary data line on the data line, wherein the source electrode, the drain electrode, the common electrode, the pixel electrode, and the auxiliary data line are formed in the same mask process. Method for manufacturing array substrate for use. The method of claim 12, And said protective film is formed by a lift-off process. The method of claim 12, And forming the gate insulating layer, the active layer, and the ohmic contact layer include forming a buffer metal layer on the ohmic contact layer. A first mask process step of forming a gate electrode and a gate wiring on the substrate; A second mask process step of sequentially forming a gate insulating film, an active layer, an ohmic contact layer, and a data wiring on the substrate including the gate electrode and the gate wiring; A third mask process step of forming a source electrode, a drain electrode, a common electrode and a pixel electrode on the substrate; Forming a passivation layer on the active layer between the source electrode and the drain electrode and between the common electrode and the pixel electrode. Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 17, The first mask process step includes forming a gate pad at one end of the gate wiring, and the second mask process step includes forming a data pad at one end of the data wiring, and the third mask. The process step includes forming an auxiliary data line on the data line, a gate pad electrode on the gate pad, and a data pad electrode on the data pad. The method of claim 18, The second mask process step Sequentially forming the gate insulating film, the pure amorphous silicon layer, the impurity amorphous silicon layer, and the metal layer on the substrate including the gate electrode, the gate wiring, and the gate pad; An area except the active layer, the first line corresponding to the data line and the data pad, and the active layer, the data line and the data pad, the metal layer corresponding to the gate pad is exposed on the metal layer; Forming a photosensitive pattern comprising a second portion corresponding to and thicker than the first portion; Exposing the gate pad by removing the exposed metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating film; Removing a second portion of the photosensitive pattern; Removing the metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer by using the first portion of the photosensitive pattern as an etching mask; Removing a first portion of the photosensitive pattern Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 19, The forming of the photosensitive pattern may include a mask including a transmissive part, a blocking part, and a transflective part, the transmitting part corresponding to the gate pad, and the blocking part corresponding to the active layer, the data line, and the data pad. And the transflective portion corresponds to a region excluding the active layer, the data line, the data pad, and the gate pad. The method of claim 20, The second mask process may include forming an extension under the auxiliary data line and the data pad electrode, wherein the extension includes a pure amorphous silicon pattern and an impurity amorphous silicon pattern. Method for manufacturing array substrate for use. The method of claim 19, The first mask process step includes forming a common wiring parallel to the gate wiring, wherein the common wiring is electrically connected to the common electrode. The method of claim 22, The second mask process may include exposing the common wiring by removing the exposed metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer, and the gate insulating layer. The method of claim 18, The third mask process step Forming a conductive layer on the substrate including the data line and the data pad; A first photosensitive pattern corresponding to the source and drain electrodes, a second photosensitive pattern corresponding to the auxiliary data line and the data pad electrode, and a third corresponding to the pixel electrode and the common electrode on the conductive layer Forming a photosensitive pattern and a fourth photosensitive pattern corresponding to the gate pad electrode; The conductive layer is patterned by using the first to fourth photosensitive patterns as an etch mask to form the source and drain electrodes, the auxiliary data line, the data pad electrode, the pixel electrode, the common electrode, and the gate pad electrode. Forming; Removing the ohmic contact layer between the source and drain electrodes to expose the active layer between the source and drain electrodes; Removing the first to fourth photosensitive patterns Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 24, The forming of the passivation layer may include forming an insulating film on the substrate including the first to fourth photosensitive patterns, and selectively removing the insulating film together with the first to fourth photosensitive patterns. Method of manufacturing array substrate for liquid crystal display device. The method of claim 25, The patterning of the conductive layer may include exposing the conductive layer by wet etching to expose 2,000 to 5,000 microseconds of an edge lower surface of the first to fourth photosensitive patterns. Manufacturing method. The method of claim 24, The forming of the passivation layer may include disposing a shadow mask covering the gate pad electrode and the data pad electrode, and depositing an insulating material on the substrate except for the gate pad electrode and the data pad electrode. Method of manufacturing array substrate for display device. The method of claim 17, The second mask process step includes forming a buffer metal layer on the ohmic contact layer. The method of claim 28, Forming the buffer metal layer comprises the step of sequentially depositing and patterning molybdenum-titanium alloy, copper and molybdenum-titanium alloy.

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