KR20060133746A - The substrate for lcd and method for fabricating of the same - Google Patents

Abstract

An array substrate for an LCD and a method for manufacturing the same are provided to significantly decrease the number of manufacturing processes in comparison with a conventional four-mask process using a halftone mask. A gate electrode(124) and a gate line connected to the gate electrode are formed on a substrate(120) using a first mask. An active layer(AL), an ohmic contact layer(OCL), an island-shaped source and drain pattern, and a data line are formed using a second mask. A passivation layer(146) is formed on the resultant substrate. The passivation layer and the island-shaped pattern are pattern-etched using a third mask, thereby forming a source electrode(148), a drain electrode(150), and a drain contact hole(152) exposing the drain electrode. A pixel electrode(160), which is contacted with the drain electrode, is formed using a fourth mask.

Description

Array substrate for liquid crystal display device and manufacturing method therefor {The substrate for LCD and method for fabricating of the same}

1 is a perspective view schematically showing a configuration of a general liquid crystal panel.

2 is an enlarged plan view illustrating an enlarged portion of a conventional array substrate for a liquid crystal display device;

3A to 3G, 4A to 4G, and 5A to 5G are cross-sectional views taken along II-II, III-III, and IV-IV of FIG. 2 and shown in a conventional process sequence.

6 is an enlarged plan view of a portion of an array substrate for a liquid crystal display device according to the present invention;

7A to 7F, 8A to 8F, and 9A to 9F are cross-sectional views taken along the line V-V, VI-VI, VIII-V of Fig. 6 and in accordance with the process sequence of the present invention.

<Brief description of the main parts of the drawing>

120: substrate 122: gate wiring

124: gate electrode 126: gate pad

AL: active layer 137: island-like metal layer

140: data wiring 148: source electrode

150: drain electrode 160: pixel electrode

162: gate pad electrode 164: data pad electrode

The present invention relates to a liquid crystal display (LCD), and more particularly, to a new four-mask process that can significantly reduce the process step in manufacturing an array substrate for a liquid crystal display device.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy to express an image.

The liquid crystal display includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between upper and lower substrates. The liquid crystal is driven by an electric field applied up and down by the pixel electrode, so that the characteristics such as transmittance and aperture ratio are excellent.

Currently, an active matrix liquid crystal display (AM-LCD: Active Matrix LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and video performance.

Hereinafter, the configuration of the above-described liquid crystal display device will be described with reference to FIG. 1.

1 is a perspective view schematically illustrating an enlarged view of a liquid crystal display device.

As illustrated, the liquid crystal panel 51 includes a first substrate 5 and a second substrate 10 spaced apart from each other with a liquid crystal layer (not shown) interposed therebetween. One surface of the first substrate 5 facing each other includes a black matrix 6, color filters (red, green, blue) 7a, b, and c, and a transparent common electrode 9 formed on the color filter.

A plurality of pixel regions P are defined in the second substrate 10 facing the first substrate 5, and the gate wiring 14 extending through one side of the pixel region P, and the gate wirings. The data line 26 extending beyond the other side of the pixel region P where the 14 passes is not parallel.

Due to this configuration, the pixel region P becomes an area defined by the gate wiring 14 and the data wiring 26 intersecting, and the thin film transistor T is formed at the intersection of the two wirings.

The pixel region P includes a transparent pixel electrode 32 in contact with the thin film transistor T, which is transparent conductive material having excellent light transmittance such as indium-tin-oxide (ITO). Formed of metal.

The array substrate for a liquid crystal display device configured as described above is manufactured through a process of about 5 to 6 masks and briefly introduced as follows.

The following process is described using the 5 mask process as an example, and lists only the mask process.

First mask process: forming a gate electrode of a thin film transistor and a gate wiring (and gate pad) connected thereto.

Second mask process: an active layer and an ohmic contact layer forming process positioned over an insulating layer on the gate electrode.

Third mask process: a data line (and data pad) intersecting the gate line and the insulating layer therebetween, a source electrode connected to the data line and extending over the ohmic contact layer, and a drain electrode spaced apart from the data line .

4th mask process: The process of forming a contact film which forms a protective film in the whole surface of a board | substrate and exposes the said drain electrode.

Fifth mask process: forming a pixel electrode contacting through the contact hole;

An array substrate for a liquid crystal display device can be produced by the above five mask processes.

Since the array substrate is manufactured through a plurality of sequential processes as described above, the greater the number of processes, the greater the probability of occurrence of defects. In addition, the processing time increases and the process cost increases, thereby degrading the competitiveness of the product.

As a method for solving this problem, a four mask process has been proposed.

2 is an enlarged plan view of a part of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

As illustrated, the array substrate includes a gate wiring 62 extending in one direction on the insulating substrate 60, and a data wiring 82 defining the pixel region P while crossing the gate wiring 62.

The gate line 62 has a gate pad 64 at one end thereof, and the data line 82 has a data pad 84 at one end thereof.

The transparent gate pad electrode 112 and the data pad electrode 114 contacting the gate pad 64 and the data pad 84 are respectively formed on the electrodes.

At the intersection of the gate line 62 and the data line 82, a gate electrode 64 in contact with the gate line 62, a first semiconductor layer 90a disposed over the gate electrode 64, The thin film transistor T includes a source electrode 94 spaced apart from the first semiconductor layer 90a and connected to the data line 82, and a drain electrode 96 spaced apart from the source electrode 94.

The pixel region P includes a transparent pixel electrode 110 in contact with the drain electrode 96.

In this case, an island-shaped metal layer 86 formed in the same process as the source and drain electrodes 94 and 96 is formed on a part of the gate line 62, and is configured to contact the pixel electrode 110.

In this way, a storage capacitor Cst is formed in which the gate wiring 62 is a storage first electrode and the island-shaped metal layer 86 is a storage second electrode.

The second semiconductor layer 90b is formed under the metal layer of the island shape 86. In addition, a third semiconductor layer 90c is formed under the source and drain electrodes 94 and 96, the data line 82, and the data pad 84, and the semiconductor layer remains under the characteristic of the four mask process. In particular, the pure amorphous silicon layer is exposed to the outside of the source and drain electrodes 94 and 96, the data line 82, and the data pad 84.

Hereinafter, a method of manufacturing an array substrate by a four mask process according to the related art will be described with reference to the process drawings.

3A to 3F, FIGS. 4A to 4F, and FIGS. 5A to 5F are cross-sectional views taken along the lines II-II, III-III, and IV-IV of FIG. 2 and shown in a conventional process sequence.

3A, 4A, and 5A illustrate a first mask process.

3A, 4A, and 5A, a pixel region P including a switching region S, a gate region G, a data region D, and a storage region C on the substrate 60. ).

In this case, the storage area C is defined in a part of the gate area G.

Aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), molybdenum (Mo), etc., on the substrate 60 on which the plurality of regions S, P, G, D, and C are defined. A gate metal layer 62 having a single metal layer or a double metal layer structure such as aluminum (Al) / chromium (Cr) (or molybdenum (Mo)) and extending in a horizontal direction and including a gate pad 66 at one end thereof; The gate electrode 64 is formed to be connected to the gate line 62 and positioned in the switching region S.

Next, FIGS. 3B to 3E, 4B to 4E, and 5B to 5E illustrate a second mask process.

3B, 4B, and 5B, a gate insulating film 68 is formed on the entire surface of the substrate 60 on which the gate wiring 62 including the gate electrode 64 and the gate pad 66 is formed. An amorphous silicon layer (a-Si: H, 70), an amorphous silicon layer (n + or p + a-Si: H, 72) containing impurities, and a metal layer 74 are formed.

The gate insulating layer 68 may be formed of an inorganic insulating material containing silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ), or in some cases, benzocyclobutene (BCB) and acrylic resin (resin). One of the included organic insulating materials is formed by depositing, and the metal layer 74 is formed by depositing one or more materials selected from the aforementioned conductive metal group.

Next, a photoresist is applied on the metal layer 74 to form a photosensitive layer 76.

The mask M including the transmissive part B1, the blocking part B2, and the transflective part B3 is positioned on the photosensitive layer 76.

In this case, the blocking part B2 is positioned to correspond to a part corresponding to the switching area S, the data area D, and the storage area C, and the transflective part B3 is positioned at the switching area S. The transmissive part B1 is positioned in correspondence with the remaining area, and is positioned in the remaining area except for the switching area S and the data area D. FIG.

Next, a process of exposing the lower photosensitive layer 76 by irradiating light to the upper portion of the mask M is performed, and a process of developing is performed.

As shown in FIGS. 3C, 4C, and 5C, a stepped first photosensitive pattern 78a is provided in the switching area S, and a first extension pattern extending from the first photosensitive pattern 78a is provided in the data area D. Referring to FIGS. A second photosensitive pattern 78b and a third photosensitive pattern 78c are formed in the storage area C.

The photosensitive layer is removed from the switching area S, the data area D, and the storage area C, so that the lower metal layer 74 is exposed.

Next, a process of removing the exposed metal layer 74, the impurity amorphous silicon layer 72 below, and the pure amorphous silicon layer 70 is performed.

In this case, depending on the type of the metal layer 74, the metal layer and the lower layer may be removed at the same time, and after etching the metal layer first through the dry etching process, the pure amorphous silicon layer 70 and the amorphous silicon containing impurities The process of removing layer 72 may proceed.

3D, 4D, and 5D illustrate ash processing. The exposed component layer and the lower layer are removed, and a source / drain metal layer 80 is disposed below the first photosensitive pattern 78a. And a data line 82 extending from the source / drain metal layer 80 corresponding to the data area D and including a data pad 84 at one end thereof, and corresponding to the switching area S. FIG. The metal layer 86 of the shape was formed.

In this case, a pure amorphous silicon layer and an amorphous silicon layer including impurities are present under the data line 82 including the source / drain metal layer 80 and the data pad 84, and the island-shaped metal layer 86. For convenience, the second semiconductor pattern 90b and the island-shaped metal layer corresponding to the first semiconductor pattern 90a, the data wires, and the data pads 82 and 84 may correspond to the source and drain metal layers 80. Corresponding to 86, it is referred to as a third semiconductor pattern 90c.

Next, a process of ashing a part of the remaining photosensitive patterns 78a, b, and c is performed.

The ash process is a process for forming a source electrode and a drain electrode spaced apart from the switching region (S), by completely removing the lower portion of the stepped first photosensitive pattern (78a) source. A portion of the drain metal layer 80 is exposed.

At this time, a part of the periphery of each photosensitive pattern 78a, b, c is removed during the ash process, so that the lower source and drain metal layers 80, the data wirings, the data pads 82, 84, and the island-shaped metal layers 86 are removed. A portion of the surroundings is exposed.

After the ash process, a process of removing the exposed metal layer 86 and an impurity amorphous silicon layer thereunder is performed.

3E, 4E, and 5E, upon completion of the removal process, the lower layer (pure amorphous silicon layer) of the semiconductor layer located above the gate electrode 64 functions as the active layer 92a. A portion of the upper layer spaced apart from the upper portion of the active layer 92a functions as the ohmic contact layer 92b.

In addition, a portion of the divided metal layer positioned on the ohmic contact layer 92b in contact with the data line 82 serves as the source electrode 94, and a portion spaced apart from this serves as the drain electrode 96. Will be

In addition, the island-shaped metal layer 86 formed corresponding to the storage region C functions as a storage electrode along with the gate wiring 62 under the island-shaped metal layer 86.

That is, the gate line 62 functions as the storage first electrode, and the upper metal layer 86 functions as the storage second electrode. Accordingly, the storage first electrode, the gate insulating layer 68 on the upper portion thereof, the third semiconductor pattern 90c and the storage second electrode 86 on the upper portion constitute a storage capacitor Cst.

Next, the second mask process may be completed by performing a process of removing the remaining photosensitive layers 78a, b, and c.

3F, 4F, and 5F illustrate a third mask process, in which a data line 82 including the source and drain electrodes 94 and 96 and a data pad 84 and a storage capacitor Cst are provided. One selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the constructed substrate 60, or optionally, benzocyclobutene (BCB) and acryl A protective film 100 is formed by coating one selected from a group of organic insulating materials including a resin.

A drain contact hole 102 for patterning the passivation layer 100 to expose a portion of the drain electrode 96, a storage contact hole 104 for exposing the island-shaped metal layer, and

A gate pad contact hole 106 exposing a portion of the gate pad 66 and a data pad contact hole 108 exposing a portion of the data pad 84 are formed.

3G, 4G, and 5G illustrate a fourth mask process, wherein indium tin oxide (ITO) and indium zinc oxide (IZO) are formed on the entire surface of the substrate 60 on which the passivation layer 100 is formed. A selected one of the transparent conductive metal groups is deposited and patterned to form a pixel electrode 110 positioned in the pixel region P while simultaneously contacting the drain electrode 96 and the island-shaped metal layer 86. . At the same time, a gate pad electrode 112 in contact with the gate pad 66 and a data pad electrode 114 in contact with the data pad 84 are formed.

Through the above process, an array substrate for a liquid crystal display device may be manufactured by a conventional four mask process.

Conventional four-mask process has the effect of lowering the production cost and shortening the process time as a breakthrough compared to the conventional five-mask process, and as a result of the process shortens the probability of failure is also reduced.

However, the conventional four-mask process using halftone (diffraction exposure), as mentioned in the above process, an ashing process for removing only part of the photosensitive layer from the top, and a source and drain electrode to expose a portion of the active layer. And a large number of processes need to be added and precise control of the ohmic contact layer removal process in sequence and there is a problem that the production yield is lowered due to a lot of difficulties in the process.

The present invention has been proposed for the purpose of solving the above-mentioned problems, and in the four-mask process which is generally used as in the prior art, the objective is to greatly reduce the process step, simplify the process, reduce the cost and improve the production yield. It is done.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: defining a plurality of pixel regions including a switching region on a substrate; A first mask process step of forming a gate electrode in the switching region and a gate wiring connected to the switching region and extending to one side of the pixel region; A second mask process step of forming an active layer, an ohmic contact layer, a source / drain metal layer (Irish shape) and a data line connected thereto corresponding to the switching region; A third passivation layer formed on the entire surface of the substrate on which the source / drain metal layer and the data line are formed and then patterned to form a source electrode and a drain electrode spaced apart from the gate electrode, and a drain contact hole exposing the drain electrode; A mask processing step; And a fourth mask process step of forming a transparent pixel electrode in contact with the drain electrode and positioned in the pixel region.

The third mask process may include forming a passivation layer on an entire surface of the substrate on which the source / drain metal layer and the data line are formed; The passivation layer, the source drain metal layer and the ohmic contact layer under the protective layer are sequentially etched so as to correspond to the gate electrode, the source and drain electrodes spaced apart while exposing the active layer, and a drain contact exposing a portion of the drain electrode. Forming a hole.

An island metal layer may be formed on a portion of the gate line to contact the pixel electrode to form a storage capacitor. The data line may include a data pad at one end of the data line and a gate pad at one end of the gate line.

In this case, a transparent data pad electrode in contact with the data pad, a transparent gate pad electrode in contact with the gate pad, the pixel electrode, the gate pad electrode and the data pad electrode is indium tin oxide (ITO), It is formed of one selected from a group of transparent conductive metals including indium-zinc-oxide (IZO).

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

6 is an enlarged plan view of a portion of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated, the gate line 122 extends in one direction on one side of the insulating substrate 120, and one end thereof intersects the gate line 122 and the gate line 122 to cross the pixel region P. As shown in FIG. A data line 140 is defined and includes a data pad 142 at one end.

In this case, a gate pad electrode 162 and a data pad electrode 164 contacting the gate pad 126 and the data pad 142 are formed on the upper portion of the gate pad 126 and the data pad 142.

A gate electrode 124, an actiation layer AL, an ohmic contact layer (not shown), a source electrode 148, and a drain electrode 150 at an intersection point of the gate line 122 and the data line 140. The thin film transistor T is constituted.

In this case, the source and drain electrodes 148 and 150 may be patterned at the same time as the passivation layer (not shown) in the third mask process.

The pixel region P forms a transparent pixel electrode 160 in contact with the drain electrode 150.

An island-shaped metal layer is formed on the upper portion of the gate line 122 in the portion defining the pixel region P, and serves as a storage first electrode, and contacts the pixel electrode 160 extending above the gate line 122. A storage capacitor Cst having 137 as the storage second electrode is configured.

Hereinafter, the manufacturing method of the array substrate for liquid crystal display devices using the 4 mask process of the new method which concerns on this invention is demonstrated with reference to a process drawing.

7A to 7F, 8A to 8F, and 9A to 9F are cross-sectional views taken along the line V-V, VI-VI, VIII-V of FIG. 6 and according to the process sequence of the present invention. (VV of FIG. 6 is a cutting line of the thin film transistor and the pixel region, VI-VI is a cutting line of the gate pad, and V-V is a cutting line of the data pad.)

7A, 8A, and 9A illustrate a first mask process, and include a pixel region P, a gate region G, and a data region D including a switching region S on a substrate 120. And storage area (C).

In this case, the storage area C may be defined in a part of the gate area G.

Aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), molybdenum (Mo) and the like on the substrate 120 defining the plurality of regions S, P, G, D, and C. One or more metals selected from a group of conductive metals including a single metal or aluminum (Al) / chromium (Cr) (or molybdenum (Mo)) may be deposited and patterned to correspond to the gate region G. A gate wiring 122 including a gate pad 126 and a gate electrode 124 connected to the gate wiring 122 and positioned in the switching region S are formed.

7B to 7D, 8B to 8D, and 9B to 9D are views illustrating a second mask process.

As shown in FIGS. 7B, 8B, and 9B, the gate insulating layer 128 and the amorphous layer are formed on the entire surface of the substrate 100 on which the gate wiring 122 including the gate electrode 124 and the gate pad 126 is formed. The silicon layer 130, the amorphous silicon layer 132 including impurities, and the conductive metal layer 134 are stacked.

In this case, the gate insulating layer 128 is an inorganic insulating material containing silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ), or in some cases, benzocyclobutene (BCB) and acrylic resin (resin). It is formed by depositing one of the organic insulating materials, including.

The amorphous silicon layer 130 is formed by depositing amorphous silicon (a-Si: H), and the amorphous silicon layer 132 including the impurity is formed of amorphous silicon (n + or p + a-Si: H) containing impurities. ) Is formed by vapor deposition.

The conductive metal layer 134 is formed by depositing the aforementioned conductive metal.

As shown in FIGS. 7C, 8C, and 9C, a photoresist is applied to the entire surface of the substrate 120 on which the metal layer 134 is formed to form a photoresist layer (not shown). The photosensitive patterns 136a, 136b, and 136c are formed in the switching region S, the data region D, and a part of the storage region C by patterning.

Next, a process of removing the metal layer 134 exposed between the photosensitive patterns 136a, b, and c, and the impurity amorphous silicon layer 132 and the amorphous silicon layer 130 thereunder is performed.

As shown in FIGS. 7D, 8D, and 9D, the patterned amorphous silicon layer 130 and the impurity amorphous silicon layer 132 are formed under the photosensitive patterns 136a, b, and c corresponding to the switching region S. FIG. ) And a source / drain metal layer 138 formed thereon, and including a data pad 142 at one end corresponding to the data area D, and contacting the source / drain metal layer 138 (see FIG. 6). 140 is formed.

In addition, an island-shaped metal layer 137 is formed in the storage area C.

At this time, the amorphous silicon layer 130 and the impurity amorphous silicon layer 132 are also present under the data line (140 in FIG. 6) and the island-shaped metal layer 137.

In general, the amorphous silicon layer 130 disposed above the gate electrode 124 corresponding to the switching region S is called an active layer (AL), and the impurity amorphous silicon layer 132 is an ohmic contact layer ( ohmic contact layer (OCL).

7E, 8E, and 9E illustrate a third mask process, in which the source and drain metal layers 138, the data pads and the data lines 142 (140 of FIG. 6), and the island-shaped metal layers 137 are formed. The protective film 146 is formed on the entire surface of the substrate 120.

The protective layer 146 is generally formed by depositing at least one material selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ), or optionally, benzocyclobutene (BCB) and acryl. It may be formed by depositing one selected from the group of organic insulating materials including an (acryl) -based resin (resin).

Next, the passivation layer 146, and the source and drain metal layer 137 and the island-shaped metal layer 137 and the impurity amorphous silicon layer 132 underneath are removed, and the gate electrode 124 is removed. Correspondingly, part of the active layer AL is exposed.

At this time, the source and drain metal layers 138 are divided into the source electrode 148 and the drain electrode 150 with the exposed active layer AL interposed therebetween, and a part of the drain electrode 150 is also removed. A drain contact hole 152 is formed, and a storage contact hole 154 is formed to side-expose the island-shaped metal layer 137 corresponding to the storage area C.

At the same time, a gate pad contact hole 156 exposing the gate pad 126 and a data pad contact hole 158 exposing the data pad 142 are formed.

At this time, the active layer AL exposed between the source and drain electrodes 148 and 150 functions as an active channel CH.

 7F, 8F, and 9F illustrate a fourth mask process, indium tin oxide (ITO) and indium zinc oxide (IZO) formed on the entire surface of the substrate 120 on which the patterned passivation layer 146 is formed. A selected one of the group of transparent conductive metal including the (C) is deposited and patterned to form the pixel electrode 160 positioned in the pixel region P while contacting the drain electrode and the island-shaped metal layers 150 and 137.

At the same time, a gate pad electrode 162 in contact with the gate pad 126 and a data pad electrode 164 in contact with the data pad 142 are formed.

In response to the storage area C, a portion of the gate wiring 122 is used as a first storage electrode, and an island-shaped metal layer 137 in contact with the pixel electrode 160 is used as a second storage electrode. The capacitor Cst is formed.

Next, an oxygen plasma process is performed on the surface of the substrate 120 to form a thin insulating film SiO ₂ on the exposed surface of the active layer AL, thereby protecting the exposed active layer.

Through the above process, the array substrate for the liquid crystal display device can be manufactured by the four mask process according to the present invention.

Therefore, when the array substrate for the liquid crystal display device (including the array substrate for the transverse electric field type liquid crystal display device) is manufactured by the four mask process according to the present invention, the process is compared with the conventional four mask process using a halftone mask (diffraction exposure). There is an effect that can significantly reduce the step.

Therefore, it is possible to improve the competitiveness of the product by reducing the process cost, it is possible to reduce the process time has the effect of improving the production yield.

Claims (7)

Defining a plurality of pixel regions comprising a switching region on the substrate; A first mask process step of forming a gate electrode in the switching region and a gate wiring connected to the switching region and extending to one side of the pixel region; A second mask process step of forming an active layer, an ohmic contact layer, a source / drain metal layer (Irish shape) and a data line connected thereto corresponding to the switching region; A third passivation layer formed on the entire surface of the substrate on which the source / drain metal layer and the data line are formed and then patterned to form a source electrode and a drain electrode spaced apart from the gate electrode, and a drain contact hole exposing the drain electrode; A mask processing step; A fourth mask process step of forming a transparent pixel electrode in contact with the drain electrode and positioned in the pixel region Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, The third mask process is Forming a protective film on an entire surface of the substrate on which the source / drain metal layer and the data wiring are formed; The passivation layer, the source drain metal layer and the ohmic contact layer under the protective layer are sequentially etched so as to correspond to the gate electrode, the source and drain electrodes spaced apart while exposing the active layer, and a drain contact exposing a portion of the drain electrode. Forming holes Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, And an island-like metal layer formed in contact with the pixel electrode on a portion of the gate wiring to form a storage capacitor. The method of claim 1, And a data pad at one end of the data line and a gate pad at one end of the gate line. The method of claim 4, wherein And a transparent data pad electrode in contact with the data pad and a transparent gate pad electrode in contact with the gate pad. The method of claim 5, The pixel electrode, the gate pad electrode, and the data pad electrode are formed of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO). The method of claim 2, And forming an insulating film (SiO) on the exposed surface of the active layer by performing oxygen plasma (O ₂ plasama) treatment on the entire surface of the substrate on which the pixel electrode is formed.

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