KR101284697B1 - An array substrate for LCD and method for fabricating thereof - Google Patents

An array substrate for LCD and method for fabricating thereof Download PDF

Info

Publication number
KR101284697B1
KR101284697B1 KR20060060986A KR20060060986A KR101284697B1 KR 101284697 B1 KR101284697 B1 KR 101284697B1 KR 20060060986 A KR20060060986 A KR 20060060986A KR 20060060986 A KR20060060986 A KR 20060060986A KR 101284697 B1 KR101284697 B1 KR 101284697B1
Authority
KR
South Korea
Prior art keywords
layer
electrode
gate
region
metal layer
Prior art date
Application number
KR20060060986A
Other languages
Korean (ko)
Other versions
KR20080002272A (en
Inventor
김효욱
이창빈
최병국
김동영
Original Assignee
엘지디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to KR20060060986A priority Critical patent/KR101284697B1/en
Publication of KR20080002272A publication Critical patent/KR20080002272A/en
Application granted granted Critical
Publication of KR101284697B1 publication Critical patent/KR101284697B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F2001/136231Active matrix addressed cells for reducing the number of lithographic steps
    • G02F2001/136236Active matrix addressed cells for reducing the number of lithographic steps using a gray or half tone lithographic process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Abstract

The present invention relates to a liquid crystal display device, and in particular, to produce an array substrate for a liquid crystal display device in a new four-mask process.
According to the present invention, in fabricating an array substrate using a new four-mask process, the active layer is formed in an island shape only on the upper portion of the gate wiring, and the source and drain electrodes of the thin film transistor are formed of only a transparent material.
When the array substrate is fabricated as described above, since the active layer is covered by the gate electrode from the lower light, and the source and drain electrodes of the form extending out of the gate electrode are transparent, the lower light is the source and the Since it is not reflected by the drain electrode, there is an advantage of minimizing occurrence of leakage current in the active layer.
In addition, since there is no active layer (amorphous silicon layer) extending laterally under the data line, there is an advantage that an opening area can be further secured.

Description

Array substrate for LCD and manufacturing method thereof {An array substrate for LCD and method for fabricating etc}

1 is a perspective view schematically showing a configuration of a general liquid crystal panel,

2 is an enlarged plan view of a portion of a conventional array substrate for a liquid crystal display device;

3 is a cross-sectional view taken along II-II and V-V of FIG. 2,

4A to 4G, 5A to 5G, and 6A to 6G are cross-sectional views illustrating cutting processes of II-II, III-III, and IV-IV of FIG.

7 is an enlarged plan view of a portion of an array substrate for a liquid crystal display according to a first embodiment of the present invention;

8A to 8C are cross-sectional views taken along the line VI-VI, VIII-VIII and VIII-VIII in FIG. 7, respectively.

9A to 9K, 10A to 10K, and 11A to 11K are cut along the lines VI-VI, VIII-VIII and VIII-V of Fig. 7, and are shown in the process sequence according to the first embodiment of the present invention. Is a process cross section,

12A to 12E are cross-sectional views illustrating a process sequence according to a second embodiment of the present invention, cut along VI-VI, VIII-VIII, VIII-VIII in FIG.

13 is an enlarged plan view of a part of an array substrate for a transverse electric field type liquid crystal display device according to a third embodiment of the present invention;

14A, 14B, 14C, and 14D are cross-sectional views taken along the line VIII-VIII, VIII-VIII,?-?,?-? Of Fig. 13, respectively.

15A to 15K, 16A to 16K, 17A to 17K, and 18A to 18K are cut along the lines VIII-VIII, VIII-VIII,?-?,?-? Of FIG. Process sectional drawing shown by the process sequence which concerns on 3rd Example,

19A to 19D and FIGS. 20A to 20D are cross-sectional views illustrating a process sequence according to a fourth embodiment of the present invention, cut along the lines VIII-VIII and VIII-13 of FIG. 13.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

100 substrate 102 gate electrode

104: gate wiring 106: gate pad

122: active layer 126: buffer metal

136: source electrode 138: drain electrode

140: pixel electrode 142: gate pad electrode

146 data wiring 148 data pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to an array substrate for a liquid crystal display device applying a new four mask process and a method of manufacturing the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal.

The liquid crystal has an elongated shape, has directivity in the arrangement of molecules, and can control the direction of the molecular arrangement by applying an electric field to the liquid crystal artificially.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy to express an image.

The liquid crystal display includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between upper and lower substrates. The liquid crystal is driven by an electric field applied up and down by the pixel electrode, so that the characteristics such as transmittance and aperture ratio are excellent.

Currently, an active matrix liquid crystal display (AM-LCD: Active Matrix LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and video performance.

Hereinafter, the configuration of the above-described liquid crystal display device will be described with reference to FIG. 1.

1 is a perspective view schematically illustrating an enlarged view of a liquid crystal display device.

As illustrated, the liquid crystal panel 51 includes a first substrate 5 and a second substrate 10 spaced apart from each other with a liquid crystal layer (not shown) interposed therebetween. One surface of the first substrate 5 facing each other includes a black matrix 6, color filters (red, green, and blue) 7a, 7b, and 7c, and a transparent common electrode 9 on the color filter.

A plurality of pixel regions P are defined in the second substrate 10 facing the first substrate 5, and the gate wiring 14 extending through one side of the pixel region P, and the gate wirings. The data line 26 extending beyond the other side of the pixel region P where the 14 passes is not parallel.

Due to this configuration, the pixel region P becomes an area defined by the gate wiring 14 and the data wiring 26 intersecting, and the thin film transistor T is formed at the intersection of the two wirings.

The pixel region P includes a transparent pixel electrode 32 in contact with the thin film transistor T, which is transparent, such as indium-tin-oxide (ITO), having a relatively high light transmittance. It is formed of a conductive metal.

The array substrate for a liquid crystal display device configured as described above is manufactured through a process of about 5 to 6 masks and briefly introduced as follows.

The following process is described using the 5 mask process as an example, and lists only the mask process.

1st mask process: The process of forming a gate electrode and a gate wiring (and gate pad).

Second mask process: forming an active layer and an ohmic contact layer on the gate electrode.

Third mask process: forming a data wiring (and data pad), a source electrode and a drain electrode.

4th mask process: The process of forming a contact film which forms a protective film in the whole surface of a board | substrate and exposes the said drain electrode.

Fifth mask process: forming a pixel electrode contacting through the contact hole;

An array substrate for a liquid crystal display device can be produced by the above five mask processes.

Since the array substrate is manufactured through a plurality of processes as described above, the more the number of processes, the greater the probability of defects, and thus the production yield is lowered, and the problem of product competitiveness being weakened due to increased process time and increased process cost. have.

As a method for solving this problem, a four mask process has been proposed.

2 is an enlarged plan view of a part of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

As shown, the array substrate includes a gate wiring 62 extending in one direction on the insulating substrate 60 and a data wiring 98 crossing the gate wiring 62 to define the pixel region P. Referring to FIG.

A gate pad 64 is formed at one end of the gate line 62, and a data pad 99 is formed at one end of the data line 98.

On the gate pad 64 and the data pad 99, a transparent gate pad electrode GP and a data pad electrode DP are formed in contact with the gate pad 64 and the data pad 99, respectively.

At the intersection of the gate line 62 and the data line 98, a gate electrode 64 in contact with the gate line 62, a first semiconductor layer 90a disposed over the gate electrode 64, The thin film transistor T includes a source electrode 94 spaced apart from the first semiconductor layer 90a and connected to the data line 82, and a drain electrode 96 spaced apart from the source electrode 94.

The pixel region P includes a transparent pixel electrode PXL in contact with the drain electrode 96.

At this time, by forming an island-shaped metal layer 86 in contact with the pixel electrode PXL on a portion of the gate line 62, a portion of the gate line 62 is used as the first electrode and the island shape is formed. A storage capacitor Cst is formed using a metal layer 86 as a second electrode and a gate insulating film (not shown) positioned between the two electrodes as a dielectric.

A second semiconductor layer 90b extending from the first semiconductor layer 90a is formed below the data line 98, and a third semiconductor layer 90c is formed below the island-shaped metal layer 86. do.

At this time, the array substrate fabricated by a conventional four-mask process, the lower active layer (amorphous silicon layer, 92a, 70) around the source and drain electrodes 94, 96 and data wiring 98 It is composed of an extended form.

The pure amorphous silicon layer 70 is exposed to light to generate a photocurrent, and due to the photo-leakage current generated therein, a coupling phenomenon occurs with the adjacent pixel electrode PXL. There is a problem in that a wavy noise occurs on the screen of the liquid crystal panel.

Hereinafter, this will be described in detail with reference to FIG. 3.

3 is a cross-sectional view taken along lines II-II and V-V of FIG. 2.

As shown in the drawing, when the thin film transistor array substrate 60 is manufactured by a conventional four mask process, the first semiconductor layer 90a and the first semiconductor layer 90a and the lower portion of the source and drain electrodes 94 and 96 and the data wiring 98 are formed. 2 semiconductor layers 90b are comprised.

The first and second semiconductor layers 90a and 90b are formed by laminating a pure amorphous silicon layer (a-Si: H layer) and an amorphous silicon layer (n + a-Si: H) containing impurities. The pure amorphous silicon layer constituting the first semiconductor layer 90a is called an active layer 92a and the upper impurity amorphous silicon layer is called an ohmic contact layer 92b.

The pure amorphous silicon layer 70 of the second semiconductor layer 90b which is positioned below the data line 98 and protrudes to both sides of the data line 98 is exposed to a light source (not shown) at the bottom so that a photocurrent is generated. Will occur.

At this time, due to the minute flicker by the light source of the lower, the pure amorphous silicon layer 70 reacts finely and the activation and deactivation state is repeated, resulting in a change in the photocurrent.

Such a current component is coupled with a signal flowing through the neighboring pixel electrode PXL to distort the movement of a liquid crystal (not shown) positioned in the pixel electrode PXL.

As a result, wavy noise in which thin wavy lines appear on the screen of the liquid crystal panel is generated.

In particular, the photocurrent generated in the active layer 92a of the thin film transistor T acts as a leakage current, causing a malfunction of the thin film transistor.

On the other hand, the pure amorphous silicon layer 70 under the data line 98 protrudes about 1.7 mu m from both sides of the data line 98, respectively.

In general, the data line 98 and the pixel electrode PXL are patterned at a distance of about 4.75 μm in consideration of an alignment error. In this case, the data line 98 and the pixel electrode PXL are considered in consideration of the protrusion. ), The separation distance D is 6.45 m.

That is, the pixel electrode PXL is patterned as long as the length of the portion protruding to one side of the data line 98, and at the same time, the width W1 of the black matrix BM that covers the light leakage of the portion is also widened. There is a problem that the area is encroached.

As described above, the shape of the second semiconductor layer 90b beneath the data line 98 in which the wavy noise occurs is inevitably generated by a conventional general four mask process. To facilitate understanding, a conventional four mask process will be described.

Hereinafter, a method of manufacturing an array substrate by a four mask process according to the related art will be described with reference to the process drawings.

4A to 4G, 5A to 5G, and 6A to 6G are cross-sectional views taken along the II-II, III-III, IV-IV of FIG. 2 and shown in a conventional four mask process sequence. .

4A, 5A, and 6A illustrate a first mask process.

4A, 5A, and 6A, a pixel region P, a gate region G, a data region D, and a storage region C including a switching region S on a substrate 60 are provided. ).

In this case, the storage area C is defined in a part of the gate area G.

A plurality of regions (S, P, G, D, C) extending in one direction on a defined substrate (60), including gate pads (66) at one end thereof, and the gate lines A gate electrode 64 connected to the 62 and positioned in the switching region S is formed.

In this case, the gate pad and the gate wiring 66 and 62 and the gate electrode 64 may be made of a single metal such as aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), or molybdenum (Mo). It is formed by depositing one or more materials selected from the group of conductive metals including aluminum (Al) / chromium (Cr) (or molybdenum (Mo)).

Next, FIGS. 4B to 4E, 5B to 5E, and 6B to 6E illustrate a second mask process.

As shown in FIGS. 4B, 5B, and 6B, the gate insulating film 68 is formed on the entire surface of the substrate 60 on which the gate wiring 62 including the gate electrode 64 and the gate pad 66 is formed. A pure amorphous silicon layer (a-Si: H, 70), an amorphous silicon layer (n + or p + a-Si: H, 72) containing impurities, and a conductive metal layer 74 are formed.

The gate insulating layer 68 may be formed of an inorganic insulating material containing silicon nitride (SiN x ) and silicon oxide (SiO 2 ), or in some cases, benzocyclobutene (BCB) and acrylic resin (resin). One of the included organic insulating materials is formed by depositing, and the metal layer 74 is formed by depositing one or more materials selected from the aforementioned conductive metal group.

Next, a photoresist is coated on the entire surface of the substrate 60 on which the conductive metal layer 74 is formed to form the photosensitive layer 76.

Next, a mask M including the transmissive part B1, the blocking part B2, and the transflective part B3 is positioned on the spaced upper portion of the photosensitive layer 76.

In this case, the transflective portion B3 forms a slit shape or a translucent film on the mask M, thereby lowering the intensity of light or lowering the amount of light transmitted, thereby incompletely exposing the photosensitive layer.

In addition, the blocking unit B2 functions to completely block light, and the transmitting unit B1 transmits light so that the photosensitive layer 76 is completely exposed to chemical changes, that is, fully exposed by light.

Meanwhile, the transflective portion B3 and the cutoff portion B2 are positioned at both sides of the transflective portion B3 in the switching region S, and the cutoff portion B2 is positioned at the storage region C. The blocking part B2 is positioned in the data area D that crosses the gate area G.

Next, light is irradiated to the upper portion of the mask M, and a process of exposing and developing the lower photosensitive layer 76 is performed.

As shown in FIGS. 4C, 5C, and 6C, the first to third photosensitive layers 78a, 78b, and 78c are patterned on the switching region S, the data region D, and the storage region C. FIGS. ).

Next, the metal layer 74 exposed to the periphery of the first to third photosensitive layers 78a, 78b, and 78c, an impurity amorphous silicon layer 72 below it, and a pure amorphous silicon layer 70 are removed. Proceed with the process.

 In this case, depending on the type of the metal layer 74, the metal layer and its lower layers (72, 70) may be removed at the same time, and the pure amorphous silicon layer 70 and the impurities of the lower portion through the dry etching process after etching the metal layer first The process of removing the included amorphous silicon layer 72 is performed.

As shown in FIGS. 4D, 5D, and 6D, when the above-described removal process is completed, the first metal pattern 80 and the lower portion of the first to third photosensitive layers 78a, 78b, and 78c may be formed. In the first metal pattern 80, a second metal pattern 82 extending along one side of the pixel region P and an island-shaped third metal pattern 86 corresponding to the storage region C are formed. do.

In this case, a pure amorphous silicon layer 70 and an amorphous silicon layer 72 including impurities are present under the first to third metal patterns 80, 82, and 86. For convenience, the first metal pattern 80 is provided. ) Is formed below the first semiconductor pattern 90a, and is formed below the second metal pattern 82 is the second semiconductor pattern 90b, and is formed below the third metal pattern 86 is the third The semiconductor pattern 90c is called.

Next, an ashing process for exposing the lower metal pattern 80 by removing a portion having a lower height corresponding to the center of the gate electrode 64 of the first photosensitive layer 78a is performed. do.

As a result, as shown in the figure, a part of the first metal pattern 80 corresponding to the center of the gate electrode 64 is exposed, and at this time, to the periphery of the first to third photosensitive patterns 78a, 78b, and 78c. Portions of the first to third metal patterns 80, 84, and 86 are simultaneously exposed.

After the ashing process, a process of removing the exposed portion of the first metal pattern 86 and the impurity amorphous silicon layer 72 below it is performed.

As shown in FIGS. 4E, 5E, and 6E, when the removal process is completed, the lower layer (pure amorphous silicon layer) of the first semiconductor pattern 90a disposed on the gate electrode 64 may be an active layer ( 92a), and a portion of the upper layer spaced apart from the upper portion of the active layer 92a functions as the ohmic contact layer 92b.

At this time, the ohmic contact layer 92b on the active layer 92a is removed, and the lower active layer 92a is etched to prevent impurities from remaining on the surface (active channel) of the active layer.

On the other hand, the metal pattern divided above the ohmic contact layer 92b is referred to as a source electrode 94 and a drain electrode 96, respectively.

In this case, the second metal pattern (82 of FIG. 5C) in contact with the source electrode 94 is called a data line 98, and one end of the data line 98 is called a data pad 99.

In addition, the island-shaped third metal pattern 86 formed to correspond to the storage area C functions as a storage electrode along with the gate wiring 62 below.

That is, the gate line 62 functions as the storage first electrode, and the upper third metal pattern 86 functions as the storage second electrode. Accordingly, the storage first electrode, the gate insulating layer 68 on the upper portion thereof, the third semiconductor pattern 90c and the storage second electrode 86 on the upper portion constitute a storage capacitor Cst.

Next, the second mask process may be completed by performing a process of removing the remaining photosensitive layers 78a, 78b, and 78c.

4F, 5F, and 6F illustrate a third mask process, in which a data line 98 including the source and drain electrodes 94 and 96 and a data pad 99 and a storage capacitor Cst are provided. One selected from the group of inorganic insulating materials including silicon nitride (SiN X ) or silicon oxide (SiO 2 ) is deposited on the entire surface of the constructed substrate 60, or optionally, benzocyclobutene (BCB) and acryl A protective film PAS is formed by coating one selected from the group of organic insulating materials including resin.

A drain contact hole CH1 exposing a portion of the drain electrode 96 by patterning the passivation layer PAS, a storage contact hole CH2 exposing the island-shaped third metal pattern 86, The gate pad contact hole CH3 exposing a part of the gate pad 66 and the data pad contact hole CH4 exposing a part of the data pad DP are formed.

4G, 5G, and 6G illustrate a fourth mask process, wherein indium tin oxide (ITO) and indium zinc oxide (IZO) are formed on the entire surface of the substrate 60 on which the passivation layer (PAS) is formed. A pixel electrode PXL positioned in the pixel region P while simultaneously depositing and patterning one selected from the group of transparent conductive metals including the same, and contacting the drain electrode 96 with the island-shaped third metal pattern 86. To form. At the same time, a gate pad electrode GP in contact with the gate pad 66 and a data pad electrode DP in contact with the data pad 99 are formed.

Through the above-described process, an array substrate for a liquid crystal display device can be manufactured by a conventional four mask process.

Conventional four-mask process has the effect of lowering the production cost and shortening the process time as a breakthrough compared to the conventional five-mask process, and as a result of the process shortens the probability of failure is also reduced.

However, as mentioned above, in the structure of the thin film transistor array substrate fabricated by the conventional four-mask process, since the semiconductor layer is extended on both sides of the data wiring, this results in wavy noise on the screen. There is a problem that occurs and there is a problem that the opening ratio is lowered due to the expanded semiconductor layer.

In addition, since the light leakage current may occur in the active layer of the thin film transistor, there is a problem that may cause a malfunction of the thin film transistor.

Disclosure of Invention The present invention has been made to solve the above-described problem, and a first object of the present invention is to manufacture a liquid crystal panel that realizes high quality without generating wavy noise, and a second object of realizing high brightness through enlargement of an opening area. The third object is to prevent light leakage current from occurring in the thin film transistor.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: a substrate in which a pixel region, a switching region, a gate region, and a data region are defined; A data line positioned in the data area and including a transparent data pad at one end and having a transparent metal layer and an opaque metal layer having a smaller width; A thin film disposed in the switching region and including an ohmic contact layer and a buffer metal spaced apart from the gate electrode, the insulating film, and the active layer, and a transparent source electrode extending to the data line while being in contact with the buffer metal, respectively; A transistor; A gate wiring positioned in the gate region and including a transparent pad electrode at one end thereof and a gate pad in contact with the gate pad; And a transparent pixel electrode positioned in the pixel area.

The source electrode may have a “U” shape, and the drain electrode may be configured to be spaced apart from the inside of the source electrode.

The source and drain electrodes, the gate pad electrode, the data pad electrode, and the pixel electrode may be formed of indium tin oxide (ITO).

The active layer is formed in an island shape on top of the gate electrode.

And further comprising a storage capacitor formed by extending the pixel electrode over a portion of the gate wiring, and using the gate wiring as the first electrode and the extended portion of the pixel electrode as the second electrode.

The source electrode may be integrated with the lower transparent metal layer (electrode layer) of the data line.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: defining a pixel region, a switch region, a gate region, and a data region on a substrate; Forming a gate wiring including a gate electrode in the switching region and a gate pad at one end of the gate region; Forming a active layer, an etch stop layer, an ohmic contact layer, a buffer metal on the gate electrode, and exposing the gate pad; A transparent source electrode in contact with the buffer metal and the data line at the same time; a drain electrode spaced apart therefrom; a pixel electrode extending from the drain electrode to the pixel region; a gate pad electrode in contact with the gate pad; and the data region. Forming a data line including a data pad at one end of the at least one end, and forming a space between the buffer metal and an underlying ohmic contact layer; Forming a second insulating film (protective film) formed on the entire surface of the substrate and exposing the gate pad electrode and the data pad.

The second mask process may include: laminating a first insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, a conductive metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode, the gate wiring, and the gate pad are formed; Placing a mask comprising a transmissive part, a blocking part, and a half over part spaced apart from the upper part of the photosensitive layer, and irradiating light to the upper part of the mask to expose a lower photosensitive layer; Developing the exposed photosensitive layer to expose a conductive metal layer corresponding to the gate pad, and forming a photosensitive pattern patterned at a low height in a region except the switching region; Etching the exposed conductive metal layer, the lower impurity amorphous silicon layer, the pure amorphous silicon layer, and the first insulating layer to expose a lower gate pad; By removing the photosensitive pattern formed to a lower height other than the switching region, to expose the lower conductive metal layer, and to remove the exposed conductive metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer and the first insulating film below And forming a gate electrode, a first insulating layer, an active layer (pure amorphous silicon layer), an ohmic contact layer, and a buffer metal (patterned second metal layer) in the switching region.

The mask may be configured such that the transflective portions are positioned at both sides of the blocking portion corresponding to the switching region, the transmissive portion is positioned corresponding to the gate pad, and the transflective portion is positioned at the other region.

The conductive metal layer is characterized in that the molybdenum (Mo).

The third mask process may include forming a transparent conductive metal layer and an opaque conductive metal layer on the entire surface of the substrate on which the buffer metal is formed and the gate pad is exposed; A photosensitive layer is formed on the opaque conductive metal layer, and a mask including a transmissive part, a blocking part, and a semi-transmissive part is disposed on the spaced upper part of the photosensitive layer, and the lower photosensitive layer is exposed by irradiating light to the upper part of the mask. Making a step; Developing the exposed photosensitive layer, a first photosensitive pattern spaced at a low height corresponding to the switching region, a second photosensitive pattern patterned at a low height in the pixel region, and positioned at an upper portion of the gate pad Forming a third photosensitive pattern patterned in height and a stepped fourth photosensitive pattern positioned in the data area and patterned at one end at a low height; Etching the lower opaque conductive metal layer and the transparent conductive metal layer exposed between the first to fourth photosensitive patterns to form a source electrode and a drain electrode spaced apart from the switching region, a pixel electrode in the pixel region, a gate pad, Forming a data line including a gate pad electrode in contact and a data pad at one end of the data region; An ashing process of completely removing the photosensitive pattern patterned to a low height to expose the source and drain electrodes, the pixel electrode, the gate pad electrode, and the data pad; Removing the source and drain electrodes, the gate pad electrode, and the upper opaque conductive metal layer constituting the data pad to leave only a lower transparent conductive metal layer; Removing the exposed buffer metal and the underlying ohmic contact layer between the transparent source electrode and the drain electrode, and exposing the underlying active layer.

According to another aspect of the present disclosure, the third mask process may include forming a transparent conductive metal layer and an opaque conductive metal layer on the entire surface of the substrate on which the buffer metal is formed and the gate pad is exposed; Forming a photosensitive layer on the opaque conductive metal layer, placing a mask including a transmissive part and a blocking part on a spaced upper part of the photosensitive layer, and exposing a lower photosensitive layer by irradiating light to the upper part of the mask; ; Developing the exposed photosensitive layer to form a photosensitive pattern corresponding to the switching region, the gate pad, and the data region; A lower opaque conductive metal layer and a transparent conductive metal layer exposed between the photosensitive patterns are etched to form a source electrode and a drain electrode spaced apart from the switching region, a pixel electrode in the pixel region, and a gate pad electrode in contact with the gate pad. And forming a data line at one end of the data area, the data line including a data pad; An over-etching process using an etching solution includes removing only the opaque metal layer on the source electrode and the drain electrode to form a transparent source electrode and a drain electrode.

The width of the source electrode and the drain electrode is smaller than the width of the data line, and the size of the source electrode and the drain electrode may be etched by an overetch process.

According to an aspect of the present invention, an array substrate for a transverse electric field type liquid crystal display device includes: a substrate in which a pixel region, a switching region, a gate region, and a data region are defined; A thin film transistor positioned in the switching region, the ohmic contact layer and the buffer metal spaced apart from the gate electrode, the insulating film, and the active layer, and a transparent source electrode and a drain electrode respectively contacting the buffer metal; A data line formed in the data area and including a data pad transparent at one end thereof; A gate line electrode formed in the gate region, the gate line including a gate pad at one end thereof, a gate pad electrode in contact with the gate line, and having a transparent metal layer and an opaque metal layer stacked thereon; The pixel region may include a plurality of pixel electrodes formed in a vertical bar shape, a plurality of common electrodes spaced apart from each other, and a passivation layer covering an entire surface of the substrate and exposing the gate pad electrode and the data pad electrode.

The active layer is characterized by consisting of a smaller area than the gate electrode.

The common electrode and the pixel electrode may have a structure in which a transparent metal layer and an opaque metal layer are stacked.

Further comprising a common wiring spaced in parallel with the gate wiring, wherein the common electrode is configured in contact with the common wiring.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, including: defining a switching region, a pixel region, a gate region, and a data region on a substrate; Forming a gate wiring including a gate electrode in the switching region and a gate pad at one end of the gate region; Forming a dielectric layer, an active layer, an ohmic contact layer, and a buffer metal on the gate electrode, and exposing the gate pad; A transparent source electrode and a drain electrode in contact with the buffer metal, a plurality of pixel electrodes in a vertical bar shape extending to the pixel area while in contact with the drain electrode, and a plurality of common bars formed in a vertical bar spaced apart from the pixel electrode A third mask disposed between the electrode, a data line positioned at the data region and including a transparent data pad at one end thereof, a gate pad electrode in contact with the gate pad, and a buffer metal and an ohmic contact layer below the spacer; Process steps; And forming a passivation layer covering the entire surface of the substrate and exposing the gate pad electrode and the data pad.

The pixel electrode and the common electrode are characterized in that the transparent metal layer is exposed to the outside of the opaque metal layer.

The second mask process may include: depositing a first insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, a conductive metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode, the gate wiring, and the gate pad are formed; ; Placing a mask comprising a transmissive part, a blocking part, and a half over part spaced apart from the upper part of the photosensitive layer, and irradiating light to the upper part of the mask to expose a lower photosensitive layer; Developing the exposed photosensitive layer to expose a conductive metal layer corresponding to the gate pad, and forming a photosensitive pattern patterned at a low height in a region except the switching region; Etching the exposed conductive metal layer, the lower impurity amorphous silicon layer, the pure amorphous silicon layer, and the first insulating layer to expose a lower gate pad; By removing the photosensitive pattern formed to a lower height other than the switching region, to expose the lower conductive metal layer, and to remove the exposed conductive metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer and the first insulating film below And forming a gate electrode, a first insulating film, an active layer (pure amorphous silicon layer), an ohmic contact layer, and a buffer metal (patterned conductive metal layer) in the switching region.

The mask may be configured such that the transflective portions are positioned at both sides of the blocking portion corresponding to the switching region, the transmissive portion is positioned corresponding to the gate pad, and the transflective portion is positioned at the other region.

The third mask process may include: forming an active layer, an ohmic contact layer, and a buffer metal in the switching region, and depositing a transparent metal layer, an opaque metal layer, and a photosensitive layer on an entire surface of the substrate to which the gate pad is exposed; Placing a mask including a transmissive part, a blocking part, and a transflective part on an upper part of the photosensitive layer, and irradiating light to the upper part of the mask to expose a lower photosensitive layer; Developing the exposed photosensitive layer to form a first photosensitive pattern patterned to be spaced apart at a low height corresponding to the switching region, a plurality of second photosensitive patterns spaced to form a vertical bar corresponding to the pixel region, and the gate Forming a third photosensitive pattern corresponding to the pad and a fourth photosensitive pattern corresponding to the data area; A source electrode and a drain electrode spaced apart from the lower portion of the first photosensitive pattern by removing the opaque metal layer exposed to the outside of the first to fourth photosensitive patterns and the transparent metal layer below the second photosensitive pattern; A plurality of pixel electrodes and a common electrode spaced apart from each other in a vertical bar shape in a lower portion of the pattern, a gate pad electrode in contact with the gate pad under the third photosensitive pattern, and a data pad under the fourth photosensitive pattern Forming a data wiring; Removing the buffer metal exposed between the source and drain electrodes and a lower ohmic contact layer to form a spaced configuration; Completely removing the first photosensitive pattern through an ashing process to expose a lower source electrode and a drain electrode; And removing only the upper opaque metal layer constituting the source electrode and the drain electrode, leaving only the lower transparent metal layer.

The mask may be configured such that blocking portions are positioned at both sides of the transmissive portion corresponding to the switching region, and a plurality of transmitting portions and the blocking portions are alternately positioned to correspond to the pixel region, and the gate pad and the data region may be disposed. Correspondingly configured to position the cut-off portion.

In the third mask process step, the active layer, the ohmic contact layer, and the buffer metal may be formed in the switching region, and the transparent metal layer, the opaque metal layer, and the photosensitive layer may be formed on the entire surface of the substrate to which the gate pad is exposed. Laminating; Placing a mask including a transmissive part and a blocking part on an upper portion of the photosensitive layer, and exposing light to an upper portion of the mask to expose a lower photosensitive layer; Developing the exposed photosensitive layer, a first photosensitive pattern corresponding to the switching region, a plurality of second photosensitive patterns spaced apart in a vertical bar shape corresponding to the pixel region, and a third photosensitive component corresponding to the gate pad; Forming a pattern and a fourth photosensitive pattern corresponding to the data area; A source electrode and a drain electrode spaced apart from the lower portion of the first photosensitive pattern by removing the opaque metal layer exposed to the outside of the first to fourth photosensitive patterns and the transparent metal layer below the second photosensitive pattern; A plurality of pixel electrodes and a common electrode spaced apart from each other in a vertical bar shape in a lower portion of the pattern, a gate pad electrode in contact with the gate pad under the third photosensitive pattern, and a data pad under the fourth photosensitive pattern Forming a data wiring; An over-etching process using an etching solution may include removing only an opaque metal layer on the source electrode and the drain electrode to form a transparent source electrode and a drain electrode.

The source electrode and the drain electrode may be smaller than the width of the data line, and may be etched by an overetch process.

The source electrode is "U" shape, the drain electrode is characterized in that the rod shape configured to be spaced apart from the source electrode.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

- First Embodiment -

The present invention is characterized in that the active substrate (amorphous silicon layer) is formed in an island shape only on the upper portion of the gate electrode, and the array substrate in which the source and drain electrodes are composed only of the transparent electrode is manufactured by a new four-mask process.

7 is an enlarged plan view of a portion of an array substrate for a liquid crystal display according to the present invention.

As shown in the drawing, the gate wiring 104 extending in one direction on the insulating substrate 100 and having the gate pad 106 formed at one end thereof, and the pixel region P are defined by crossing the gate wiring 104. The data line 146 including the data pad 148 is formed at one end.

In this case, a transparent gate pad electrode 142 is formed on the gate pad 106 in contact with the gate pad 106.

A gate electrode 102, an actiation layer 122, an ohmic contact layer (not shown), a buffer metal 126 in contact with the ohmic contact layer, and an intersection point of the gate wiring 104 and the data wiring 146. The thin film transistor T includes a source electrode 136 and a drain electrode 138 which are in contact with the buffer metal 126 and are made of a transparent material.

In this case, the source electrode 136 is slit to shorten the length of the active layer 122 exposed between the source and drain electrodes 136 and 138 (the length between the source and drain electrodes) and to increase the width. It has a "U" shape, the drain electrode 138 is formed in a bar shape located in parallel with the inside of the source electrode 136.

The pixel region P includes a transparent pixel electrode 140 connected to the drain electrode 138.

On the other hand, the upper portion of the gate wiring 104 in the portion defining the pixel region P is used as a storage first electrode, and a portion of the pixel electrode 140 extending above the gate wiring 104 is second. A storage capacitor Cst is used as the storage electrode.

The above-described configuration is fabricated by a new four-mask process, and in particular, the active layer (amorphous silicon layer) is formed in an island shape on the upper portion of the gate electrode 102 and does not exist below the data line 146. It is characterized by not.

Hereinafter, a cross-sectional configuration of a thin film transistor array substrate according to the present invention will be described with reference to FIGS. 8A, 8B, and 8C.

8A, 8B, and 8C are cross-sectional views cut along VI-VI, VIII-VIII, VIII-VIII in Fig. 7, respectively, and cross-sectional views cut through the switching region and the pixel region, and the gate wiring and the pad are cut, respectively. One cross-sectional view and a cross-sectional view of a data wiring and a pad cut out.

As illustrated, the substrate 100 is defined as a plurality of pixel regions P, a gate region G, and a data region D, and at the same time, a storage region C is defined in a portion of the gate region G. For each pixel area P, a switching area S is defined adjacent thereto.

In the switching region S, a gate electrode 102, an ohmic contact layer 124 spaced apart from the first insulating layer 108, the active layer 122, and an ohmic contact layer 124 on the gate electrode 102. ) And a thin film transistor T composed of a buffer metal 126 in contact with each other) and source and drain electrodes 136 and 138 in contact with the buffer metal 126.

In addition, a data line 146 connected to the source electrode 138 is formed at one side of the pixel region P, and the data line 146 is formed of a laminated structure of transparent and opaque metal layers 128 and 130. The data pad 148, which is the end of the data line 146, is composed of a transparent metal layer 128.

In this case, unlike the data line, the source and drain electrodes 136 and 138 are formed of only the transparent metal layer 128, and since the resistance is very high at the contact surface between the transparent metal layer 128 and the ohmic contact layer 124 below, In order to lower this, the buffer metal 126 is further configured.

In addition, a gate pad electrode 142 composed of a transparent metal layer is formed on the gate pad 106.

In the above-described configuration, the most characteristic configuration is that the active layer 122 (pure amorphous silicon layer) and the ohmic contact layer 124 (impurity amorphous silicon layer) are formed in an island shape on top of the gate electrode 102, Amorphous silicon (a-Si: H) and impurity amorphous silicon (n + a-Si: H) do not exist in the lower portion of the gate wiring and data wiring 104,146, and because of this configuration, representative of the conventional four-mask structure There are advantages that can solve the problem of the wavy noise and aperture ratio which used to be a problem.

In addition, as mentioned above, since the source electrode 136 and the drain electrode 138 are formed of only a transparent metal layer (transparent electrode layer), the lower light is reflected by the source and drain electrodes 136 and 138 so that the active layer ( The phenomenon irradiated with 122) does not occur, which also has the advantage that no photocurrent occurs.

The characteristic features described above are due to the four mask process proposed in the present invention, hereinafter with reference to the drawings, a method of manufacturing an array substrate for a liquid crystal display device with a new four mask process according to the present invention will be described in detail.

9A to 9K, 10A to 10K, and 11A to 11K are cross-sectional views taken along the line VI-VI, VIII-VIII and VIII-V in accordance with the process sequence of the present invention. (At this time, VI-VI of FIG. 7 is a cutting line of the thin film transistor and the pixel region, VII-V is a cutting line of the gate pad and the wiring, and VII-V is a cutting line of the data pad and the wiring.)

9A to 9C and FIG. 10A are cross-sectional views illustrating a first mask process.

As illustrated, the switching region S, the pixel region P, the gate region G, the data region D, and the storage region C are defined on the substrate 100. In this case, the storage area C is defined in a part of the gate area G.

Aluminum (Al), aluminum alloy (AlNd), chromium (Cr), molybdenum (Mo), tungsten (W), titanium on the substrate 100 defining the plurality of regions S, P, G, D, and C (Ti), copper (Cu), tantalum (Ta), and the like, and depositing one or more metals selected from the group of conductive metals to form a first conductive metal layer (not shown), and the first conductive metal layer (not shown) ) Is formed in the first mask process to form a gate electrode 102 in the switching region S, and includes a gate wiring including a gate pad 106 at one end corresponding to the gate region G. 104).

9B to 9E, 10B to 10E, and 11B to 11E are cross-sectional views illustrating a second mask process according to a process sequence.

As shown in FIGS. 9B, 10B, and 11B, the first insulating film 108 and the pure amorphous silicon layer are formed on the entire surface of the substrate 100 on which the gate electrode 102, the gate pads, and the gate wirings 106 and 104 are formed. (a-Si: H layer, 110), an impurity amorphous silicon layer (n + a-Si: H layer, 112), and a second conductive metal layer 114 are stacked, and a photo is formed on the second conductive metal layer 114. A resist (photo-resist) is applied to form the photosensitive layer 116.

In this case, the first insulating layer 108 is formed by depositing one or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN X ) and silicon oxide (SiO 2 ), and the second conductive metal layer 114. ) May be formed of one selected from the above-mentioned conductive metal group, but preferably a metal capable of dry etching, and molybdenum (Mo) among these metals.

Meanwhile, after the photosensitive layer 116 is formed, a mask including a transmissive part B1, a blocking part B2, and a transflective part B3 is disposed on a spaced upper portion of the substrate 100 on which the photosensitive layer 116 is formed. Place M).

At this time, the blocking portion B2 is positioned in correspondence with the switching region S, the transmissive portion B1 is positioned in correspondence with the gate pad 106, and the transflective portion B3 is positioned in the other region. Do it.

At this time, the area of the blocking portion B2 corresponding to the switching region S is limited within a range not exceeding the area of the gate electrode 102.

Next, a step of exposing light to the upper portion of the mask M to expose the lower photosensitive layer 116 and a continuous developing step are performed.

In this case, as shown in FIGS. 9C, 10C, and 11C, the switching region S is patterned to its original height and completely removed in correspondence with the gate pad 106 to form a lower second conductive metal layer. The photoresist pattern 118 patterned to a low height remains after exposing the 112.

Next, the second conductive metal layer 114 exposed to the gate pad 106, the impurity amorphous silicon layer 112, the pure amorphous silicon layer 110, and the first insulating layer 108 below are removed. In addition, the process of ashing and completely removing the developed portion of the photosensitive pattern 118 in a state where the height is low in correspondence with the region except the switching region S is performed.

In this case, as shown in FIGS. 9D, 10D, and 11D, the gate pad contact hole CH exposing the gate pad 106 is formed, and the height is low in the switching region S. FIG. The patterned photosensitive pattern 120 remains, and the other region is in a state in which the second conductive metal layer 114 is exposed.

Next, a process of removing the second metal layer 114, the impurity amorphous silicon layer 112 and the pure amorphous silicon layer 110 under the exposed photoresist pattern 120 is performed.

In this case, as illustrated in FIGS. 9E, 10E, and 11E, the gate electrode 102, the first insulating layer 110, and the active layer (the patterned pure amorphous silicon layer, corresponding to the switching region S), 122) and an ohmic contact layer (patterned impurity amorphous silicon layer 124) and a metal pattern 126 are stacked, and other regions expose the gate pad 106 through the gate pad contact hole CH. The first insulating film 108 is left.

9F to 9J, 10F to 10J, and 11F to 11J are cross-sectional views illustrating a third mask process step according to a process sequence.

9F, 10F, and 11F, a transparent conductive metal layer 128 and an opaque conductive metal layer 130 are stacked on the entire surface of the substrate 100, and an upper portion of the opaque conductive metal layer 130 is formed. A photoresist is applied to the photoresist layer 132 to form a photoresist.

Next, a mask M including the transmissive part B1, the blocking part B2, and the semi-transmissive part B3 is positioned on the spaced upper portion of the photosensitive layer 132.

The switching region S has the blocking portion B2 positioned at both sides of the transmissive portion B1, and the transflective portion B3 is positioned at the gate pad 106 and the pixel region P. In the data area D, the transflective part B3 is positioned at the end, the rest part is the blocking part B2, and the transflective part B1 is located in the other area.

Next, after the light is irradiated to the upper portion of the mask (M) to expose the lower photosensitive layer 132, the process of developing.

In this case, as illustrated in FIGS. 9G, 10G, and 11G, the photosensitive pattern 134a spaced apart at a low height from the switching region P, the pixel region P, and the gate pad 106 are disposed. The second and third photosensitive patterns 134b and 134c developed at low heights corresponding to the second and third photosensitive patterns 134d, respectively. Is formed.

Next, a process of removing the opaque metal layer 130 and the lower transparent metal layer 128 exposed between the first to fourth photosensitive patterns 134a, 134b, 134c and 134d is performed.

In this case, as shown in FIGS. 9H, 10H, and 11H, the source electrode 136 and the drain electrode 138 are disposed under the first photosensitive pattern 134a spaced apart from the switching region S. FIG. Is formed, and in the pixel region P, a pixel electrode 140 extending from the drain electrode 138 is formed under the second photosensitive pattern 134b and under the third photosensitive pattern 134c. The gate pad 106 and the contact gate pad electrode 142 are formed thereon, and a data line 146 including a data pad 148 is formed at one end thereof corresponding to the fourth photosensitive pattern 134d.

In this case, the source electrode 136, the drain electrode 138, the pixel electrode 140, the gate pad electrode 142, the data wires, and the data pads 146 and 148 are both transparent metal layers 128 and opaque metal layers 130. Patterned in a stacked state.

Next, a process of removing the lower buffer metal 126 and the ohmic contact layer 124 thereunder exposed between the source and drain electrodes 136 and 138 is performed.

Next, an ashing process is performed to completely remove the lower portions of the second photosensitive pattern 134b, the third photosensitive pattern 134c, and the fourth photosensitive pattern 134d.

In this case, as shown in FIGS. 9I, 10I, and 11I, the buffer metal 126 and the ohmic contact layer 124 are disposed below the source and drain electrodes 136 and 138 corresponding to the switching region S. The gap is spaced apart to expose the lower active layer 122.

In addition, the source and drain electrodes 136 and 138 except for the data line 146, the pixel electrode 140, the gate pad electrode 142, and the data pad 148 are exposed.

Next, a process of removing the upper opaque metal layer 130 forming the source and drain electrodes 136 and 138, the pixel electrode 140, the gate pad electrode 142, and the data pad 148 is performed. The process of leaving only the transparent metal layer 128 is performed.

The transparent metal layer 128 and the opaque metal layer 130 may be simultaneously etched as in the above process or may be separately etched as in the above example depending on the difference or etching method of the etching solution.

Next, a process of stripping the fourth photosensitive pattern 134d left on the data line is performed.

In this case, as illustrated in FIGS. 9J, 10J, and 11J, a source electrode 136 and a drain electrode 138 formed of only a transparent metal layer are formed in the switching region S, and the pixel region 140 is formed. A transparent pixel electrode 140 is formed in the gate region, a transparent gate pad electrode 142 in contact with the gate pad 106 is formed in the gate region G, and a transparent metal layer 128 is formed in the data region D. The data line 146 in the form of the double metal layers 128 and 130 of the over-transparent metal layer 130 and the transparent data pad 148 are formed at one end thereof.

As shown in FIGS. 9K, 10K, and 11K, one or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN 2 ) and silicon oxide (SiO 2 ) are deposited on the entire surface of the substrate 100. The second insulating film 150 (protective film) is formed.

Next, the second insulating layer 150 is patterned by a fourth mask process to expose the pixel electrode 140, the gator pad electrode 142, and the data pad electrode 146.

Through the above-described process, a new four-mask process according to the present invention can produce an array substrate for a liquid crystal display device having a shape in which an active layer does not exist below the wiring.

Hereinafter, a brief description of the process according to the present invention.

First Mask Process: A gate electrode, a gate wiring, and a gate pad are formed.

Second Mask Step: The gate pad is exposed under the insulating film, and a gate electrode, an insulating layer, an active layer, an ohmic contact layer, and a buffer metal are formed over the gate electrode.

Third mask process: source and drain electrodes and pixel electrodes, gate pad electrodes in contact with the gate pads, data lines and data pads are formed.

In this case, the source electrode, the drain electrode, the pixel electrode, the gate pad electrode, and the data pad are formed of only a transparent metal layer.

4th mask process: A 2nd insulating film is formed and patterned on a board | substrate, and the said pixel electrode, the gate pad electrode, and a data pad are exposed.

Through the above process, an array substrate for a liquid crystal display device according to the present invention can be manufactured.

The array substrate fabricated by the new four-mask process described above is not only exposed to light because the active layer is formed in an island shape having a smaller area on top of the gate electrode, and the source and drain electrodes are transparent. In addition, since the phenomenon that the lower light is reflected by the source and drain electrodes 136 and 138 and irradiates the lower active layer 122 does not occur, this also has the advantage that no leakage current occurs.

Therefore, there is an advantage that can completely block the active layer from light.

In the above-described process, in order to configure only the source and drain electrodes except the data wiring as the transparent electrode layer, halftones are used in the third mask process, but in the second embodiment, etch bias is used. By using the present invention, a method of leaving only a transparent electrode layer on the source and drain electrodes is proposed.

 - Second Embodiment -

According to the second embodiment of the present invention, when the source and drain electrodes and the data wiring are patterned in the same process, only the source and drain electrodes are formed of the transparent electrode layer using an etching characteristic. It is characterized by.

In the method of manufacturing the array substrate for a liquid crystal display device according to the first embodiment of the present invention, since the two mask processes and the fourth mask processes of the first embodiment are the same, only the three mask processes will be described.

12A to 12E are cross-sectional views illustrating a process sequence according to a second embodiment of the present invention, respectively, cut along VI-VI of FIG. 7.

(The process of the gate pad portion and the data pad portion is the same, so a separate drawing will be omitted.)

As shown in FIG. 12A, a transparent conductive metal layer is formed on the entire surface of the substrate 100 in which the active layer 122, the ohmic contact layer 124, and the buffer metal 126 are formed in the switching region S by the second mask process. 128 and an opaque conductive metal layer 130 are laminated.

Next, a photosensitive layer 132 is formed on the conductive metal layer 130, and the transmission part B1, the blocking part B2, and the semi-transmissive part B3 are formed on the spaced upper part of the photosensitive layer 132. Place the mask M.

In this case, in the switching region S, the transmissive portion B1 and the blocking portion B2 are positioned at both sides of the transmissive portion B1, and the transflective portion B3 is positioned in the pixel region P. The blocking unit B2 is positioned in the data area D, and the blocking unit is positioned in correspondence with the gate pad (not shown).

Next, after the light is irradiated to the upper portion of the mask (M) to expose the lower photosensitive layer 132, the process of developing continuously.

In this case, as illustrated in FIG. 12B, the first photosensitive pattern 134a spaced apart from the switching region S, and the second photosensitive pattern developed to a low height corresponding to the pixel region P, may be used. 134c is formed, a fourth photosensitive pattern (not shown) is formed corresponding to the gate pad (not shown), and a fourth photosensitive pattern (not shown) is formed corresponding to the data area D. FIG.

A process of removing the opaque metal layer 130 exposed to the periphery of the first to fourth photosensitive patterns 134a and 134b (not shown) is performed.

In this case, as shown in FIG. 12C, the source electrode 136 and the drain electrode 138 in which the transparent metal layer 128 and the opaque metal layer 130 are stacked below the first photosensitive pattern 134a. ) Is formed, a pixel electrode 140 is formed under the second photosensitive pattern 134b, a gate pad (not shown) is formed under the third photosensitive pattern (not shown), and the fourth A data pad (not shown) and a data line 146 are formed under the photosensitive pattern 134d.

Next, a process of removing the second photosensitive layer 134b patterned to a low height corresponding to the pixel region P is performed.

12D and 12E will show the subsequent processes after FIG. 12C described above, and together show the planar configuration of the thin film transistor portion E for understanding.

 As shown in FIG. 12D, when the above-described removal process is performed, the pixel electrode 140 is exposed to correspond to the pixel region P, and the ashing region S and the data region D are previously ashed. In the process, the first and second photosensitive patterns 134a and 134b whose heights are lowered remain.

Next, the process of removing the opaque metal layer 130 on the source and drain electrodes 135 and 138 and the pixel region P while leaving the first and second photosensitive patterns 134a and 134b is performed. do.

In order to leave only the lower transparent metal layer 128, a separate etchant capable of removing only the upper opaque metal layer 130 may be used.

In this case, the reason why the upper opaque metal layer 130 of the source and drain electrodes 136 and 138 may be removed only by the etching process in the switching region may be illustrated in FIG. This is because the line width W1 is formed thinner than the data wiring.

That is, the line width W2 of the data line 146 is patterned to about 6 to 7 μm, while the line widths of the source and drain electrodes 136 and 138 are patterned to about 5 μm.

At this time, the longer the time to immerse the substrate 100 in the etch solution, the more tends to be over-etched, such as the source and drain electrodes 136 and 138, if the width is small, the upper opaque metal layer 130 You can remove them all.

That is, by using the degree of over-etching of the material, it is possible to remove the constituent layer existing in the lower portion of the photosensitive pattern without a separate process.

When the above-described process is completed, as shown in FIG. 12E, the source and drain electrodes 136 and 138 may be formed of only a transparent metal layer.

In this case, the data line 146 also performs the same process as the source and drain electrodes 136 and 138. However, since the data line 146 has a larger line width than the source and drain electrodes 136 and 138, the data line 146 is overetched to the left and right. The opaque metal layer 130 remains.

Next, the buffer metal 126 exposed between the source and drain electrodes 136 and 138 and the lower ohmic contact layer 124 are removed to form a spaced shape as illustrated.

Next, the remaining first and second photosensitive patterns 134a and 134b are removed to have the same shape as that of FIG. 9J of the first embodiment.

Through the above-described process, a modification of the third mask process of the first embodiment of the present invention has been described.

Through the above process, an array substrate for a liquid crystal display device according to the present invention can be manufactured.

The first and second embodiments described above are examples of fabricating an array substrate for a vertical field type liquid crystal display device that includes only pixel electrodes on an array substrate using a new four-mask process. Hereinafter, Examples 3 and 4 will be described. A method of manufacturing an array substrate for a horizontal field type liquid crystal display device that simultaneously constitutes a common electrode and a pixel electrode on an array substrate will be described.

- Third Embodiment -

A third embodiment of the present invention is to fabricate a transverse field array substrate having an active layer (amorphous silicon layer) in an island shape only on top of a gate electrode, and wherein the source and drain electrodes are composed of only transparent electrodes in a new four-mask process. It features.

FIG. 13 is a plan view schematically illustrating a configuration of an array substrate for a transverse electric field type liquid crystal display device according to a third exemplary embodiment of the present invention.

As shown in the drawing, the gate wiring 204 extending in one direction on the insulating substrate 200 and having the gate pad 206 formed at one end thereof, and the pixel region P are defined by crossing the gate wiring 204. The data line 246 including the data pad 248 is formed at one end.

At the same time, a common wiring 208 spaced apart from the gate wiring 204 is formed.

In this case, the gate pad 206 forms a gate pad electrode 244 having a shape in which a transparent metal layer and an opaque metal layer are stacked on the gate pad 206.

A buffer metal 226 contacting the gate electrode 202, the acti layer 222, an ohmic contact layer (not shown), and the ohmic contact layer at an intersection point of the gate wiring 204 and the data wiring 246. And a thin film transistor T including a source electrode 236 and a drain electrode 238 in contact with the buffer metal 226.

The pixel region P includes a pixel electrode 240 including a plurality of vertical portions extending vertically to the pixel region P while in contact with the drain electrode 238, and the pixel while being in contact with the common wiring 208. It extends vertically to the region P to form a common electrode 242 spaced apart from the pixel electrode 240.

The above-described configuration is fabricated by a new four-mask process, and in particular, since the active layer 222 (amorphous silicon layer) is not present in the lower portion of the data line 246 but is formed in a smaller area only in the upper portion of the gate electrode. The active layer 222 may be shielded from the lower light.

In addition, since the source and drain electrodes 236 and 238 are made of only a transparent material, a phenomenon in which light is reflected by the source and drain electrodes 236 and 238 and irradiated to the active layer 222 may be prevented.

Hereinafter, a cross-sectional configuration of an array substrate for a transverse electric field type liquid crystal display device according to a third embodiment of the present invention will be described with reference to FIGS. 14A, 14B, and 14C.

As illustrated, a plurality of pixel regions P, gate regions G, data regions D, switching regions S, and common signal regions CS are defined in the substrate 100.

In the switching region S, a gate electrode 202, an ohmic contact layer 224 spaced apart from the first insulating layer 210, an active layer 222, and an ohmic contact layer 224 on the gate electrode 202. ) And a thin film transistor (T) including a buffer metal (226) in contact with each other) and source and drain electrodes (236,238) in contact with the buffer metal (226).

In this case, the source and drain electrodes 236 and 238 are composed of only the transparent metal layer 228, and since the resistance is very high at the contact surface between the transparent metal layer 228 and the ohmic contact layer 224 thereunder, the buffer metal is reduced in order to lower them. 226 is further constituted.

In addition, a data line 246 connected to the source electrode 236 is configured at one side of the pixel region P, and the data line 246 is a stack of transparent and opaque metal layers 228 and 230 unlike the pixel electrode. Consists of structure.

In addition, an upper portion of the gate pad 106 forms a gate pad electrode 248 in contact with the gate pad 106. The gate pad electrode 248 also has a structure in which a transparent metal layer 228 and an opaque metal layer 230 are stacked. It features.

The pixel region P is in contact with the drain electrode 238 in the form of a plurality of vertical bars extending to the pixel region, and the pixel region P is in contact with the common wiring 242. The common electrode 242 is configured in the form of a plurality of vertical bars extending to each other.

The pixel electrode 240 and the common electrode 242 are configured to be spaced apart from each other in the pixel region P. In this case, the two electrodes 240 and 242 are formed by laminating a transparent metal layer 228 and an opaque metal layer 230. It consists of states.

In this case, the lower transparent metal layer 228 is configured to be exposed to the outside of the upper opaque metal layer 230, thereby improving luminance.

In addition, the region except for the gate pad electrode 244 and the data pad 248 is formed in such a manner as to cover the second insulating layer (protective layer 250).

In the above-described configuration, the most characteristic configuration is pure amorphous silicon (a-Si: H) and impurity amorphous silicon (n + a-Si: H), which are the same materials as the active layer 222 and the ohmic contact layer 224. The gate wiring and the data wiring 204 and 246 do not exist below, and this configuration has the advantage that the conventional noise (wavy noise) and aperture ratio problems that have been a typical problem of the four mask structure can be solved. .

In addition, as mentioned above, since both the source and drain electrodes 236 and 238 are configured to be transparent, light irradiated from the lower light is reflected by the source and drain electrodes 236 and 238 so that the active layer is formed. There is an advantage that the photocurrent does not occur because the phenomenon irradiated with 222 does not occur.

In addition, the characteristic features described above are due to the four mask process proposed in the present invention. Hereinafter, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device with a new four mask process according to the present invention will be described with reference to the accompanying drawings.

Hereinafter, FIGS. 15A to 15L, 16A to 16L, 17A to 17L, and 18A to 18L cut VIII-VIII, VIII-VIII,?-?,?-? Of FIG. It is process sectional drawing shown according to the process sequence of.

15A, 16A, 17A, and 18A are cross-sectional views illustrating a first mask process.

As illustrated, the switching region S, the pixel region P, the gate region G, the data region D, and the common signal region CS are defined on the substrate 200.

Aluminum (Al), aluminum alloy (AlNd), chromium (Cr), molybdenum (Mo), tungsten (W), titanium on the substrate 200 defining the plurality of regions S, P, G, D, and SC (Ti), copper (Cu), tantalum (Ta), and the like, and depositing one or more metals selected from a group of conductive metals to form a first conductive metal layer, and patterning the first conductive metal layer by a first mask process. Thus, the gate electrode 202 is formed in the switching region S, and the gate wiring 204 of FIG. 13 including the gate pad 206 is formed at one end corresponding to the gate region G. As shown in FIG.

At the same time, a common wiring 208 spaced in parallel with the gate wiring 204 of FIG. 13 is formed.

Hereinafter, FIGS. 15B to 15F, 16B to 16F, and 17B to 17F are process cross-sectional views illustrating a second mask process according to a process sequence.

As shown in FIGS. 14B, 15B, 16B, and 17B, the substrate 200 having the gate electrode 202, the gate pad, the gate wiring 206 (204 of FIG. 13), and the common wiring 208 is formed. The first insulating layer 210, the amorphous silicon layer (a-Si: H layer, 212), the impurity amorphous silicon layer (n + a-Si: H layer, 214) and the second conductive metal layer 216 are stacked on the entire surface. In addition, a photoresist is applied on the second conductive metal layer 216 to form the photosensitive layer 218.

In this case, the first insulating layer 210 is formed by depositing one or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN X ) and silicon oxide (SiO 2 ), and forming the second conductive metal layer ( 216 may be formed of one selected from the above-mentioned conductive metal group, but preferably a metal capable of dry etching, and molybdenum (Mo).

Meanwhile, after the photosensitive layer 218 is formed, a mask including a transmissive part B1, a blocking part B2, and a transflective part B3 is disposed on a spaced upper portion of the substrate 200 on which the photosensitive layer 218 is formed ( Place M).

In this case, the blocking unit B2 and the transflective unit B3 are positioned at both sides of the blocking unit B2 in correspondence to the switching region S, and the transmissive unit B1 is partially positioned in the common signal region CS. The transmissive part B1 is positioned to correspond to the gate pad 206, and the transflective part B3 is positioned in the other area.

In this case, the area of the blocking part B2 positioned in the switching area S is limited to a range not exceeding the area of the gate electrode 202.

Next, a step of exposing light to the upper portion of the mask M to expose the lower photosensitive layer 218 and a continuous developing step are performed.

In this way, as shown in FIGS. 15C, 16C, 17C, and 18C, the switching region S is patterned to its original height, and completely removed in correspondence with the gate pad 206 to form a second lower portion. The metal layer 216 is exposed, and the remaining area is left with the photosensitive pattern 220 patterned to a low height.

Next, an upper portion of the exposed second conductive metal layer 216, an impurity amorphous silicon layer 214, a pure amorphous silicon layer 212, and a first insulating layer 210 corresponding to the gay pad 206 may be formed. Remove

In this case, as shown in FIGS. 15D, 16D, 17D, and 18D, the common wiring contact hole CH1 exposing the common wiring 208 and the gate pad contact exposing the gate pad 206 are exposed. The hole CH2 is formed.

Next, a process of completely removing the low-patterned portion of the photosensitive pattern 220 in a region other than the switching region S by an ashing process is performed.

In this case, as illustrated in FIGS. 15E, 16E, 17E, and 18E, the photosensitive pattern 120 having a lower height through the ashing process remains in the switching region S, and the photosensitive pattern 120 remains in the other region. The second conductive metal layer 216 is exposed.

Next, a process of removing the second conductive metal layer 216, the impurity amorphous silicon layer 214 and the pure amorphous silicon layer 212 under the exposed photoresist pattern 220 is performed.

Next, a process of removing the remaining photosensitive pattern 220 is performed.

In this way, as shown in FIGS. 15F, 16F, 17F, and 18F, the pure amorphous silicon layer patterned with the gate electrode 202 and the first insulating layer 210 corresponding to the switching region S ( 222, hereinafter referred to as an 'active layer', a patterned impurity amorphous silicon layer (224, hereinafter referred to as an 'ohmic contact layer'), and a patterned second metal layer (226, hereinafter referred to as a "buffer metal") And a portion of the common wiring 208 and the gate pad 206 are externally formed through the first contact hole CH1 and the second contact hole CH2 formed in the first insulating layer 210. Will be exposed.

Hereinafter, FIGS. 15G to 15K, 16G to 16K, 17G to 17K, and 18G to 18K are process cross-sectional views illustrating a third mask process step of the present invention according to a process sequence.

As shown in FIGS. 15G, 16G, 17G, and 18G, a transparent metal layer 228 and an opaque metal layer 230 are stacked on the entire surface of the substrate 200, and on top of the opaque metal layer 230. A process of forming a photosensitive layer 232 by applying a photoresist is performed.

Next, the transparent metal layer 228 is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide, and the opaque metal layer 230 is a conductive metal. Form one of the selected groups.

The mask M including the transmissive part B3, the blocking part B2, and the transflective part B3 is positioned on the spaced upper portion of the photosensitive layer 232.

The switching region S has semi-transmissive B3 at both sides of the transmissive portion B1, and the pixel region P has the transmissive portion B1 and the blocking portion B2 (o) and B2 (e). Are alternately arranged, and the blocking portion B2 is positioned in the gate pad 206 and the data region D, and the transmissive portion B1 is positioned in the other region.

The blocking part B2 is positioned in a part of the common signal area CS.

In this case, although not shown in the drawing, the blocking parts B2 (o) and B2 (e) corresponding to the pixel area P are positioned in the vertical bar shape, and the blocking parts B2 (o) and B2 (e) are disposed. The odd-numbered blocking unit B2 (o) is integrally formed with the blocking unit B2 of the common signal region CS, and the even-numbered blocking unit B2 (e) is the switching region S. It is comprised integrally with the interruption | blocking part B2 of ().

Next, after the light is irradiated to the upper portion of the mask (M) to expose the lower photosensitive layer 232, the process of developing.

In this case, as shown in FIGS. 15H, 16H, 17H, and 18H, the photosensitive pattern 234a formed to be spaced apart at a low height corresponding to the switching region S, and the pixel region P A plurality of spaced apart second photosensitive patterns 234b, a third photosensitive pattern 234c positioned in the common signal region CS, a fourth photosensitive pattern 234d corresponding to the gate pad 206, and the data region In response to (D), a fifth photosensitive pattern 234e is formed.

Next, a process of removing the opaque metal layer 230 and the lower transparent metal layer 228 exposed between the first to fifth photosensitive patterns 234a, 234b, 234c and 234d is performed.

In this case, as illustrated in FIGS. 15I, 16I, 17I, and 18I, the source electrode 236 and the drain electrode 238 spaced apart from each other under the spaced apart first photosensitive pattern 234a, and Under the second photosensitive pattern 234b and the third photosensitive pattern 234c, a plurality of pixel electrodes 240 extending from the drain electrode 238 and extending in a vertical bar shape to the pixel region P, A plurality of common electrodes 242 are formed in contact with the common wiring 208 and extend in a vertical bar shape to the pixel region P.

In addition, a gate pad electrode 244 in contact with the gate pad 206 is formed under the fourth photosensitive pattern 234d, and a data pad 248 is disposed at one end under the fifth photosensitive pattern 234e. The data line 246 including the () is constructed.

In this case, the source and drain electrodes 236 and 238, the pixel electrode and the common electrode 240 and 242, the gate pad 244, the data pad and the data line 244 and 226 are both transparent metal layers 228 and opaque metal layers ( 230 is configured in a stacked form.

Next, a process of removing the lower buffer metal 226 and the ohmic contact layer 224 exposed between the spaced apart first photosensitive patterns 234a is performed.

Next, an ashing process of completely removing the first photosensitive pattern 234a of the switching region S is performed.

In this way, as shown in FIGS. 15J, 16J, 17J, and 18J, the source electrode 236 and the drain electrode 238 are exposed in correspondence to the switching region S, and the region thereof is height. The lowered photosensitive patterns 234b, 234c, 234d, and 234e remain.

Next, after the process of removing the upper opaque metal layer 230 of the source and drain electrodes 236 and 238, the remaining photosensitive patterns 234b, 234c, 234d and 234e are removed.

In this way, as shown in FIGS. 15K, 16K, 17K, and 18K, the transparent source electrode 236 and the drain electrode 238 are formed in the switching region S, and the gate pad 206 The gate pad electrode 244 is in contact with each other, and a data line 246 including a data pad 248 is formed at one end of the data region D.

The common electrode 242 and the pixel electrode 240 are formed in the pixel area P.

In this case, the common electrode 240 and the pixel electrode 242 are previously formed by an ashing process, and both sides of the opaque metal layer 230 are partially etched to expose the lower transparent metal layer 228 to the outside. Therefore, the luminance can play a role in this part.

Next, as illustrated in FIGS. 15L, 16L, 17L, and 18L, a second insulating film (protective film) may be deposited on the entire surface of the substrate 200 by depositing one or more materials selected from the aforementioned inorganic insulating material group. And 250 to form a pattern using a fourth mask process to expose the gate pad electrode 244 and the data pad 248.

Through the above-described process, an array substrate for a transverse electric field type liquid crystal display device according to a third embodiment of the present invention can be manufactured.

Through the above-described third embodiment, the fabricated array substrate for a transverse electric field type liquid crystal display device according to the present invention can be fabricated, and the above-described configuration also includes an amorphous silicon layer (active layer) not present in the lower portion of the wiring and the gate It is composed of an island shape only on the top of the electrode can be blocked from the light of the bottom.

In addition, since only the above-described source electrode 236 and the drain electrode 238 are formed of a transparent metal layer, the path of the lower light reflected by the source and drain electrodes 236 and 238 and irradiated to the active layer 122 can be blocked. As an example, there is an advantage in that the photo leakage current is prevented from occurring in the active layer 222.

Hereinafter, modifications of the above-described third embodiment will be described with reference to the fourth embodiment.

-4th Example--

In the fourth embodiment of the present invention, in the process of the above-described third embodiment, when the source and drain electrodes and the data wiring are patterned in the same process, by using an etching characteristic, an opaque electrode layer is left in the data wiring, The source and drain electrodes may be composed of only a transparent electrode layer.

In the method of manufacturing the array substrate for a liquid crystal display device according to the fourth embodiment of the present invention, since the first to second mask processes and the four mask processes of the third embodiment are the same, only the three mask processes will be described. .

19A to 19D and FIGS. 20A to 20D are cut along the lines VIII-VIII, VIII-VIII,?-?,?-? Of FIG. 13, and are shown according to a process sequence according to the fourth embodiment of the present invention. It is a process cross section. (At this time, numbers are written the same as in the third embodiment.)

Prior to the second mask process, the gate region 202, the first insulating layer 210, the active layer 222, the ohmic contact layer 224, and the buffer metal 246 are formed in the switching region S of the substrate 200. The other regions are stacked and covered with the first insulating layer 210 so that only the gate pad (not shown) is exposed.

19A to 19D and 20A to 20D are cross-sectional views illustrating a third mask process step in a process sequence.

After completing the second mask process, as shown in FIGS. 19A and 20A, the transparent metal layer 228 and the opaque metal layer 230 are stacked on the entire surface of the substrate 200, and the opaque metal layer 230 is formed. A photoresist is applied to the upper portion of the C) to form the photosensitive layer 232.

Next, the transparent metal layer 228 is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO), and the opaque metal layer 230 is mentioned above. It is formed with one selected from one conductive metal group.

The mask M including the transmission part B3 and the blocking part B2 is positioned on the spaced upper portion of the photosensitive layer 232.

The switching region S has the blocking portions B2 positioned on both sides of the transmissive portion B1, and the pixel region P has the transmissive portion B1 and the blocking portions B2 (o) and B2 (e). ) Are alternately arranged, the blocking portion is positioned in the gate pad (not shown), the blocking portion B2 is positioned in the data region D, and the transmissive portion B1 is positioned in the other region. It features.

The blocking part B2 is positioned in a part of the common signal area CS.

At this time, although not shown in the drawings, the transmission parts B2 (o) and B2 (e) corresponding to the pixel area P are positioned in the form of vertical bars, and the blocking parts B2 (o) and B2 (e) are disposed. The odd-numbered blocking unit B2 (o) is integrally formed with the blocking unit B3 of the common signal region CS, and the even-numbered blocking unit B2 (e) is formed of the switching region S. It is connected to the blocking unit (B2) integrally.

Next, after the light is irradiated to the upper portion of the mask (M) to expose the lower photosensitive layer 232, the process of developing.

In this case, as illustrated in FIGS. 19B and 20B, the first photosensitive pattern 234a spaced apart from the switching region S, and the second photosensitive pattern 234b may be disposed in the pixel region P. Referring to FIGS. A fourth photosensitive pattern (not shown) and a fifth photosensitive pattern 234e are formed in the common signal region (third photosensitive pattern), the gate pad, and the data region.

Next, a process of removing the lower second conductive metal layer 230 and the lower transparent metal layer 228 exposed between the photosensitive patterns is performed.

Hereinafter, FIGS. 19C to 19D and 20C to 20D illustrate the continuous processes of FIGS. 19 and 20B, and the F portion, which is a thin film transistor portion, is illustrated in a planar structure for understanding.

19C and 20C, a source electrode 238 and a drain electrode 240 spaced apart from the switching region S are formed, and the pixel region S is in contact with the common wiring 208. Common electrodes 242 in the form of a plurality of vertical bars extending into the pixel region P, and multiple common bars in the form of a plurality of vertical bars extending from the drain electrode 238 to the pixel region P and the common electrodes 242. A pixel electrode 240 spaced apart in parallel to each other, a data line D and a data pad 246 (not shown) are formed, and the gate area (not shown) is a gate pad (not shown). Is formed.

Next, the substrate 200 is immersed in an etchant to remove only the opaque metal layers 230 of the source and drain electrodes 236 and 238 disposed under the first photosensitive pattern 234a.

Such a process is possible because, as mentioned in the second embodiment, the width W1 of the source and drain electrodes 236 and 238 is smaller than the width W2 of the data line 244, thereby overeating. Only the opaque metal layers 230 of the source and drain electrodes 236 and 238 may be removed by the angle.

In this case, the opaque metal layer 230 of the pixel electrode 240 and the common electrode 242 is also partially removed. In this case, in the luminance side, both the common electrode 242 and the pixel electrode 240 are transparent metal layers. The same effect as that formed can be obtained.

As shown in Figs. 19D and 20D, only the source and drain electrodes 236 and 238 are made of a transparent metal layer, and the data wiring 246, the data pad electrode 248, the gate pad electrode (not shown), and the pixel electrode are shown. The 242 and the common electrode 240 are left in a state where the transparent metal layer 228 and the opaque metal layer 230 are stacked.

Next, if the remaining sensitization patterns 234a, 234b, 234c, 234d, and 234e are removed, the same shape as that of 15k of the third embodiment is obtained. The process is then the same as in the third embodiment, as mentioned above.

Through the above-described process, an array substrate for a transverse electric field type liquid crystal display device according to a fourth embodiment of the present invention can be manufactured.

The arrangement of the liquid crystal display array substrate according to the present invention is such that the active layer (pure amorphous silicon layer) does not exist in the lower portion of the wiring, that is, only the island-like active layer exists in the upper portion of the gate electrode. As a result, no leakage current is generated in the thin film transistor and no wavy noise is generated, thereby producing a high-quality liquid crystal panel.

Since the source electrode and the drain electrode are composed of only the transparent metal layer, the phenomenon that the lower light is reflected and irradiated to the active layer does not occur, which also has the effect of preventing the leakage current from occurring.

Further, since the pixel electrode and the common electrode of the third and fourth embodiments of the present invention are configured in such a manner that the lower transparent metal layer is exposed to both sides, the luminance can be improved.

Claims (33)

  1. A substrate in which a pixel region, a gate region on one side of the pixel region, a data region on the other side of the pixel region, and a switching region near a portion where the gate region and the data region intersect are defined;
    A data line positioned in the data area, the data line including a transparent data pad at one end and sequentially stacked with a transparent metal layer and an opaque metal layer having a smaller width;
    An ohmic contact layer and a buffer metal disposed in the switching region and sequentially spaced apart from the insulating layer, the active layer, and a transparent source electrode extending to the data line while being in contact with the buffer metal; A thin film transistor comprising;
    A gate wiring positioned in the gate region, the gate wiring including a transparent gate pad electrode at one end thereof and a gate pad in contact with the gate pad electrode;
    A transparent pixel electrode positioned in the pixel region
    Array substrate for a liquid crystal display device comprising a.
  2. The method of claim 1,
    And a source electrode having a “U” shape and the drain electrode spaced apart from the inside of the source electrode.
  3. The method of claim 1,
    And the source and drain electrodes, the gate pad electrode, the data pad, and the pixel electrode are made of indium tin oxide (ITO).
  4. The method of claim 1,
    And the active layer is formed in an island shape on the gate electrode.
  5. The method of claim 1,
    And a storage capacitor formed by extending the pixel electrode over a portion of the gate wiring, and using the gate wiring as the first electrode and the extended portion of the pixel electrode as the second electrode. Array substrate.
  6. The method of claim 1,
    And the source electrode is integrated with the lower transparent metal layer (electrode layer) of the data line.
  7. Defining a pixel region, a gate region on one side of the pixel region, a data region on the other side of the pixel region, and a switching region near a portion where the gate region and the data region cross each other on the substrate;
    Forming a gate wiring including a gate electrode in the switching region and a gate pad at one end of the gate region;
    Forming a active layer, an etch stop layer, an ohmic contact layer, a buffer metal on the gate electrode, and exposing the gate pad;
    A transparent source electrode in contact with the buffer metal and the data line at the same time; a drain electrode spaced apart therefrom; a pixel electrode extending from the drain electrode to the pixel region; a gate pad electrode in contact with the gate pad; and the data region. Forming a data line including a data pad at one end of the at least one end, and forming a space between the buffer metal and an underlying ohmic contact layer;
    Forming a second insulating film (protective film) formed on the entire surface of the substrate and exposing the gate pad electrode and the data pad;
    Array substrate manufacturing method for a liquid crystal display device comprising a.
  8. The method of claim 7, wherein
    The second mask process step is
    Stacking a first insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, a conductive metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode, the gate wiring, and the gate pad are formed;
    Placing a mask comprising a transmissive part, a blocking part, and a half over part spaced apart from the upper part of the photosensitive layer, and irradiating light to the upper part of the mask to expose a lower photosensitive layer;
    Developing the exposed photosensitive layer to expose a conductive metal layer corresponding to the gate pad, and forming a photosensitive pattern patterned at a low height in a region except the switching region;
    Etching the exposed conductive metal layer, the lower impurity amorphous silicon layer, the pure amorphous silicon layer, and the first insulating layer to expose a lower gate pad;
    By removing the photosensitive pattern formed to a lower height other than the switching region, to expose the lower conductive metal layer, and to remove the exposed conductive metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer and the first insulating film below Forming a gate electrode, a first insulating layer, an active layer (pure amorphous silicon layer), an ohmic contact layer, and a buffer metal (conductive metal layer) in the switching region.
    Array substrate manufacturing method for a liquid crystal display device comprising a.
  9. 9. The method of claim 8,
    The mask is configured such that the transflective portion is positioned at both sides of the blocking portion corresponding to the switching region, and the transmissive portion is positioned corresponding to the gate pad, and the transflective portion is positioned at the other region. Manufacturing method.
  10. 9. The method of claim 8,
    The conductive metal layer is molybdenum (Mo), characterized in that the array substrate manufacturing method for a liquid crystal display device.
  11. The method of claim 7, wherein
    The third mask process step
    Forming a buffer metal, and laminating a transparent conductive metal layer and an opaque conductive metal layer on the entire surface of the substrate to which the gate pad is exposed;
    A photosensitive layer is formed on the opaque conductive metal layer, and a mask including a transmissive part, a blocking part, and a semi-transmissive part is disposed on the spaced upper part of the photosensitive layer, and the lower photosensitive layer is irradiated with light to the upper part of the mask. Exposing;
    Developing the exposed photosensitive layer, a first photosensitive pattern spaced at a low height corresponding to the switching region, a second photosensitive pattern patterned at a low height in the pixel region, and positioned at an upper portion of the gate pad Forming a third photosensitive pattern patterned in height and a stepped fourth photosensitive pattern positioned in the data area and patterned at one end at a low height;
    Etching the lower opaque conductive metal layer and the transparent conductive metal layer exposed between the first to fourth photosensitive patterns to form a source electrode and a drain electrode spaced apart from the switching region, a pixel electrode in the pixel region, a gate pad, Forming a data line including a gate pad electrode in contact and a data pad at one end of the data region;
    An ashing process of completely removing the photosensitive pattern patterned to a low height to expose the source and drain electrodes, the pixel electrode, the gate pad electrode, and the data pad;
    Removing the source and drain electrodes, the gate pad electrode, and the upper opaque conductive metal layer constituting the data pad to leave only a lower transparent conductive metal layer;
    Exposing the underlying active layer by removing the exposed buffer metal and the underlying ohmic contact layer between the transparent source electrode and the drain electrode.
    Array substrate manufacturing method for a liquid crystal display device comprising a.
  12. The method of claim 11,
    The transparent conductive metal layer is an array substrate manufacturing method for a liquid crystal display device formed of one selected from the group consisting of a transparent conductive metal including indium tin oxide (ITO) and indium zinc oxide (IZO).
  13. The method of claim 7, wherein
    Wherein the third mask processing step comprises:
    Forming a buffer metal, and laminating a transparent conductive metal layer and an opaque conductive metal layer on the entire surface of the substrate to which the gate pad is exposed;
    Forming a photosensitive layer on the opaque conductive metal layer, placing a mask including a transmissive part and a blocking part on a spaced upper part of the photosensitive layer, and exposing a lower photosensitive layer by irradiating light to the upper part of the mask; ;
    Developing the exposed photosensitive layer to form a photosensitive pattern corresponding to the switching region, the gate pad, and the data region;
    A lower opaque conductive metal layer and a transparent conductive metal layer exposed between the photosensitive patterns are etched to form a source electrode and a drain electrode spaced apart from the switching region, a pixel electrode in the pixel region, and a gate pad electrode in contact with the gate pad. And forming a data line at one end of the data area, the data line including a data pad;
    In the over-etching process using an etching solution, removing only the opaque metal layer on the source electrode and the drain electrode to form a transparent source electrode and drain electrode
    Array substrate manufacturing method for a liquid crystal display device comprising a.
  14. 14. The method of claim 13,
    The width of the source electrode and the drain electrode is smaller than the width of the data line, it is a size that can be etched by the over-etching process, characterized in that the array substrate manufacturing method for a liquid crystal display device.
  15. A substrate in which a pixel region, a gate region on one side of the pixel region, a data region on the other side of the pixel region, and a switching region near a portion where the gate region and the data region cross each other are defined;
    A thin film transistor disposed in the switching region, the thin film transistor including a sequentially stacked gate electrode, an insulating layer, an ohmic contact layer spaced apart from an active layer, and a buffer metal, and a transparent source electrode and a drain electrode respectively contacting the buffer metal;
    A data line formed in the data area and including a data pad transparent at one end thereof;
    A gate wiring electrode formed in the gate region, the gate wiring including a gate pad at one end thereof, and a gate pad electrode in contact with the gate wiring and in which a transparent metal layer and an opaque metal layer are sequentially stacked;
      A plurality of pixel electrodes formed in a vertical bar shape in the pixel area and a plurality of common electrodes spaced apart from the plurality of pixel electrodes;
    A passivation layer covering an entire surface of the substrate and exposing the gate pad electrode and the data pad electrode;
    Array substrate for a transverse electric field type liquid crystal display device comprising a.
  16. 16. The method of claim 15,
    And the active layer has a smaller area than the gate electrode.
  17. 16. The method of claim 15,
    And the common electrode and the pixel electrode have a structure in which a transparent metal layer and an opaque metal layer are stacked.
  18. 16. The method of claim 15,
    And a common wiring spaced apart in parallel with the gate wiring.
  19. The method of claim 18,
    And the common electrode is in contact with the common wiring.
  20. Defining a pixel region, a gate region on one side of the pixel region, a data region on the other side of the pixel region, and a switching region near a portion where the gate region and the data region cross each other on the substrate;
    Forming a gate wiring including a gate electrode in the switching region and a gate pad at one end of the gate region;
    Forming a dielectric layer, an active layer, an ohmic contact layer, and a buffer metal on the gate electrode, and exposing the gate pad;
    A transparent source electrode and a drain electrode in contact with the buffer metal, and a plurality of pixel electrodes having a vertical bar shape extending to the pixel area while being in contact with the drain electrode.
    A plurality of common electrodes spaced apart from the pixel electrode and formed in a vertical bar shape;
    A third mask process step disposed in the data area, the data line including a transparent data pad at one end, a gate pad electrode in contact with the gate pad, and a space between the buffer metal and an ohmic contact layer below the third mask process step;
    A fourth mask process step of forming a passivation layer covering an entire surface of the substrate and exposing the gate pad electrode and the data pad;
    Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a.
  21. 21. The method of claim 20,
    The gate pad electrode, the data line, the common electrode, and the pixel electrode have a structure in which a transparent metal layer and an opaque metal layer are stacked.
  22. The method of claim 21
    The pixel electrode and the common electrode, wherein the transparent metal layer is a form exposed to the outside of the opaque metal layer array substrate manufacturing method for a transverse electric field type liquid crystal display device.
  23. 21. The method of claim 20,
    Wherein the second mask processing step comprises:
    Stacking a first insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, a conductive metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode, the gate wiring, and the gate pad are formed;
    Placing a mask comprising a transmissive part, a blocking part, and a half over part spaced apart from the upper part of the photosensitive layer, and irradiating light to the upper part of the mask to expose a lower photosensitive layer;
    Developing the exposed photosensitive layer to expose a conductive metal layer corresponding to the gate pad, and forming a photosensitive pattern patterned at a low height in a region except the switching region;
    Etching the exposed conductive metal layer, the lower impurity amorphous silicon layer, the pure amorphous silicon layer, and the first insulating layer to expose a lower gate pad;
    By removing the photosensitive pattern formed to a lower height other than the switching region, to expose the lower conductive metal layer, and to remove the exposed conductive metal layer, the impurity amorphous silicon layer, the pure amorphous silicon layer and the first insulating film below Forming a gate electrode, a first insulating layer, an active layer (pure amorphous silicon layer), an ohmic contact layer, and a buffer metal (patterned conductive metal layer) in the switching region.
    Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a.
  24. 24. The method of claim 23,
    The mask is a transverse electric field type liquid crystal display device, wherein the transflective portion is positioned at both sides of the blocking portion corresponding to the switching region, and the transmissive portion is positioned corresponding to the gate pad and the transflective portion is positioned at the other region. Method for manufacturing an array substrate for use.
  25. 24. The method of claim 23,
    And the conductive metal layer is molybdenum (Mo).
  26. 21. The method of claim 20,
    The third mask process step
    Forming an active layer, an ohmic contact layer, and a buffer metal in the switching region, and stacking a transparent metal layer, an opaque metal layer, and a photosensitive layer on the entire surface of the substrate to which the gate pad is exposed;
    Placing a mask including a transmissive part, a blocking part, and a transflective part on an upper part of the photosensitive layer, and irradiating light to the upper part of the mask to expose a lower photosensitive layer;
    Developing the exposed photosensitive layer to form a first photosensitive pattern patterned to be spaced apart at a low height corresponding to the switching region, a plurality of second photosensitive patterns spaced to form a vertical bar corresponding to the pixel region, and the gate Forming a third photosensitive pattern corresponding to the pad and a fourth photosensitive pattern corresponding to the data area;
    A source electrode and a drain electrode spaced apart from the lower portion of the first photosensitive pattern by removing the opaque metal layer exposed to the outside of the first to fourth photosensitive patterns and the transparent metal layer below the second photosensitive pattern; A plurality of pixel electrodes and a common electrode spaced apart from each other in a vertical bar shape in a lower portion of the pattern, a gate pad electrode in contact with the gate pad under the third photosensitive pattern, and a data pad under the fourth photosensitive pattern Forming a data wiring;
    Removing the buffer metal exposed between the source and drain electrodes and a lower ohmic contact layer to form a spaced configuration;
    Completely removing the first photosensitive pattern through an ashing process to expose a lower source electrode and a drain electrode;
    Removing an upper opaque metal layer constituting the source electrode and the drain electrode to leave only a lower transparent metal layer
    Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a.
  27. 27. The method of claim 26,
    The mask may be configured such that blocking portions are positioned at both sides of the transmissive portion corresponding to the switching region, and a plurality of transmitting portions and the blocking portions are alternately positioned to correspond to the pixel region, and the gate pad and the data region may be disposed. 12. A method of fabricating an array substrate for a transverse electric field type liquid crystal display device, characterized in that the cut-off portion is positioned so as to correspond thereto.
  28. 27. The method of claim 26,
    And the transparent metal layer is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).
  29. 21. The method of claim 20,
    And forming a common wiring at a position spaced in parallel with the gate wiring in the first mask process.
  30. 30. The method of claim 29,
    And said common electrode is formed in contact with said common wiring.
  31. 21. The method of claim 20,
    The third mask process step
    Forming an active layer, an ohmic contact layer, and a buffer metal in the switching region, and stacking a transparent metal layer, an opaque metal layer, and a photosensitive layer on the entire surface of the substrate to which the gate pad is exposed;
    Placing a mask including a transmissive part and a blocking part on an upper portion of the photosensitive layer, and exposing light to an upper portion of the mask to expose a lower photosensitive layer;
    Developing the exposed photosensitive layer, a first photosensitive pattern corresponding to the switching region, a plurality of second photosensitive patterns spaced apart in a vertical bar shape corresponding to the pixel region, and a third photosensitive component corresponding to the gate pad; Forming a pattern and a fourth photosensitive pattern corresponding to the data area;
    A source electrode and a drain electrode spaced apart from the lower portion of the first photosensitive pattern by removing the opaque metal layer exposed to the outside of the first to fourth photosensitive patterns and the transparent metal layer below the second photosensitive pattern; A plurality of pixel electrodes and a common electrode spaced apart from each other in a vertical bar shape in a lower portion of the pattern, a gate pad electrode in contact with the gate pad under the third photosensitive pattern, and a data pad under the fourth photosensitive pattern Forming a data wiring;
    In the over-etching process using an etching solution, removing only the opaque metal layer on the source electrode and the drain electrode to form a transparent source electrode and drain electrode
    Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a.
  32. 32. The method of claim 31,
    And the source electrode and the drain electrode are smaller than the width of the data line and have a size that can be etched by an overetch process.
  33. 33. The method of claim 32,
    And the source electrode has a “U” shape, and the drain electrode has a bar shape spaced apart from the source electrode in the source electrode.
KR20060060986A 2006-06-30 2006-06-30 An array substrate for LCD and method for fabricating thereof KR101284697B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR20060060986A KR101284697B1 (en) 2006-06-30 2006-06-30 An array substrate for LCD and method for fabricating thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR20060060986A KR101284697B1 (en) 2006-06-30 2006-06-30 An array substrate for LCD and method for fabricating thereof
US11/639,567 US7528409B2 (en) 2006-06-30 2006-12-15 Array substrate for liquid crystal display device and method of manufacturing the same
US12/410,839 US8198111B2 (en) 2006-06-30 2009-03-25 Array substrate for liquid crystal display device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
KR20080002272A KR20080002272A (en) 2008-01-04
KR101284697B1 true KR101284697B1 (en) 2013-07-23

Family

ID=38875682

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20060060986A KR101284697B1 (en) 2006-06-30 2006-06-30 An array substrate for LCD and method for fabricating thereof

Country Status (2)

Country Link
US (2) US7528409B2 (en)
KR (1) KR101284697B1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW413844B (en) 1998-11-26 2000-12-01 Samsung Electronics Co Ltd Manufacturing methods of thin film transistor array panels for liquid crystal displays and photolithography method of thin films
KR101284697B1 (en) * 2006-06-30 2013-07-23 엘지디스플레이 주식회사 An array substrate for LCD and method for fabricating thereof
JP2009094413A (en) * 2007-10-11 2009-04-30 Sumitomo Chemical Co Ltd Thin-film active element, organic light-emitting device, display device, electronic device and method for manufacturing thin-film active element
KR101602635B1 (en) * 2009-11-30 2016-03-22 삼성디스플레이 주식회사 Display devise, thin film transistor substrate and method of fabricating the same
KR20120108336A (en) 2011-03-23 2012-10-05 삼성디스플레이 주식회사 Display device and fabrication method thereof
US8895985B2 (en) 2012-11-23 2014-11-25 Lg Display Co., Ltd. Array substrate for liquid crystal display and method for manufacturing the same
JP6278633B2 (en) * 2013-07-26 2018-02-14 三菱電機株式会社 Thin film transistor array substrate and manufacturing method thereof, and liquid crystal display device and manufacturing method thereof
CN105655407A (en) * 2016-03-11 2016-06-08 京东方科技集团股份有限公司 Polycrystalline silicon thin film transistor and preparation method thereof, array substrate and display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060089452A (en) * 2005-02-04 2006-08-09 삼성전자주식회사 Array substrate, manufacturing method thereof and liquid crystal display panel

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333273B1 (en) * 1999-08-02 2002-04-24 구본준, 론 위라하디락사 The array substrate of TFT type liquid crystal display device and a method of fabricating the same
US6580127B1 (en) * 1999-09-30 2003-06-17 International Business Machines Corporation High performance thin film transistor and active matrix process for flat panel displays
TW498178B (en) * 2000-05-02 2002-08-11 Hannstar Display Corp Manufacturing method and structure for in-plane switching mode liquid crystal display unit
KR100766493B1 (en) * 2001-02-12 2007-10-15 삼성전자주식회사 Tft lcd
KR100799464B1 (en) * 2001-03-21 2008-02-01 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Device and Fabricating Method Thereof
KR100797374B1 (en) * 2001-06-05 2008-01-22 엘지.필립스 엘시디 주식회사 Liquid Crystal Display and Fabricating Method Thereof
KR100450701B1 (en) * 2001-12-28 2004-10-01 엘지.필립스 엘시디 주식회사 The substrate for LCD and method for fabricating the same
KR100883769B1 (en) * 2002-11-08 2009-02-18 엘지디스플레이 주식회사 Method for fabricating of an array substrate for LCD
KR101012491B1 (en) * 2003-12-04 2011-02-08 엘지디스플레이 주식회사 Substrate of LCD and method for fabricating of the same
KR101086476B1 (en) * 2004-04-14 2011-11-25 엘지디스플레이 주식회사 Liquid Crystal Display Panel and Method of Fabricating the same
KR101049001B1 (en) * 2004-05-31 2011-07-12 엘지디스플레이 주식회사 Liquid crystal display device of color filter on-film transistor (COT) structure of transverse electric field system (ISP)
KR101126396B1 (en) * 2004-06-25 2012-03-28 엘지디스플레이 주식회사 Thin film transistor array substrate and fabricating method thereof
KR100679100B1 (en) * 2004-10-29 2007-02-06 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Panel Of Horizontal Electronic Fileld Applying Type and Method of Fabricating the same
JP2006171723A (en) * 2004-12-13 2006-06-29 Samsung Electronics Co Ltd Array substrate, method of manufacturing same, and liquid crystal display apparatus having same
KR101249774B1 (en) * 2005-12-29 2013-04-09 엘지디스플레이 주식회사 An array substrate for In-Plane switching mode LCD and method of fabricating of the same
KR101257811B1 (en) * 2006-06-30 2013-04-29 엘지디스플레이 주식회사 An array substrate for LCD and method for fabricating thereof
KR101284697B1 (en) * 2006-06-30 2013-07-23 엘지디스플레이 주식회사 An array substrate for LCD and method for fabricating thereof
KR101297358B1 (en) * 2006-06-30 2013-08-14 엘지디스플레이 주식회사 An array substrate for LCD and method for fabricating thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060089452A (en) * 2005-02-04 2006-08-09 삼성전자주식회사 Array substrate, manufacturing method thereof and liquid crystal display panel

Also Published As

Publication number Publication date
US20080001177A1 (en) 2008-01-03
US8198111B2 (en) 2012-06-12
US7528409B2 (en) 2009-05-05
KR20080002272A (en) 2008-01-04
US20090186438A1 (en) 2009-07-23

Similar Documents

Publication Publication Date Title
US6300152B1 (en) Method for manufacturing a panel for a liquid crystal display with a plasma-treated organic insulating layer
US7202502B2 (en) Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
JP4897995B2 (en) Thin film transistor substrate for liquid crystal display device
US7978292B2 (en) Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
US6586286B2 (en) Method for fabricating thin film transistor array substrate for liquid crystal display
US7768621B2 (en) Manufacturing method for a liquid crystal display
KR100372579B1 (en) A method for fabricating array substrate for liquid crystal display device and the same
KR101225440B1 (en) Liquid crystal display and fabricating method thereof
US7751021B2 (en) Liquid crystal display and fabricating method thereof
KR100445791B1 (en) Active matrix substrate and manufacturing method thereof
JP4710026B2 (en) Array substrate manufacturing method for liquid crystal display device
KR101055011B1 (en) Active matrix substrate and liquid crystal display device having the same
CN101097320B (en) Liquid crystal display device and method of fabricating the same
CN100407036C (en) Liquid crystal display device and fabricating method thereof
KR100726132B1 (en) A method for fabricating array substrate for liquid crystal display device and the same
CN1267784C (en) Method for producing liquid crystal display device
US7612373B2 (en) Liquid crystal display device and method of manufacturing liquid crystal display device with color filter layer on thin film transistor
US6765270B2 (en) Thin film transistor array gate electrode for liquid crystal display device
US20060001803A1 (en) Liquid crystal display device and fabricating method thereof
KR101250319B1 (en) Fringe field switching mode liquid crystal display device and Method of fabricating the same
US7777822B2 (en) Array substrate for LCD device having double-layered metal structure and manufacturing method thereof
CN1288490C (en) Substrate for liquid crystal display and liquid crystal display using same
US7763483B2 (en) Array substrate for liquid crystal display device and method of manufacturing the same
KR101085136B1 (en) Thin film transistor substrate of horizontal electric field and fabricating method thereof
KR101246719B1 (en) Array substrate for In-Plane switching mode LCD and the method for fabricating the same

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20160630

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20190617

Year of fee payment: 7