KR20110076725A - Array substrate for wide-viewing angle mode liquid crystal display device - Google Patents

Abstract

PURPOSE: An array substrate for wide-viewing angle liquid crystal display device is provided to increase an opening rate and improve charging characteristics by reducing the capacitance of a storage capacitor. CONSTITUTION: An array substrate for wide viewing angle includes as follows. A gate wired is formed to a first direction on a substrate. A data wire defines a pixel area by exchanging the gate wire. A thin film transistor is electrically connected to the gate wire and the data wire. A pixel electrode(155) is formed to the pixel area, is connected to a drain electrode of the thin film transistor and includes at least first opening unit(op1). A protective layer(160) is formed on upper part of the pixel electrode and covers a thin film transistor, a gate wire and a data wire. A common electrode(170) is formed on upper part of the protective layer, is overlapped with the pixel electrode, and has a plurality of second opening unit(op2). The first opening unit corresponds to a common electrode which is between neighboring second opening unit.

Description

Array Substrate for Wide-Viewing Angle Mode Liquid Crystal Display Device}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a wide viewing angle liquid crystal display device having improved aperture ratio and transmittance.

A liquid crystal display device (LCD) is a display device using optical anisotropy and polarization properties of liquid crystals, and is widely used in display units of portable electronic devices, monitors of computers, and televisions.

The liquid crystal has an elongated molecular structure, which is oriented in orientation, and when placed in an electric field, the direction of molecular arrangement changes according to its size and direction. Accordingly, the liquid crystal display includes a liquid crystal panel in which a liquid crystal layer is positioned between two substrates on which electric field generating electrodes are formed, and artificially adjusts an arrangement direction of liquid crystal molecules through a change in an electric field generated between the two electrodes. Various images are displayed by changing the light transmittance accordingly.

In general, a liquid crystal display device includes an array substrate on which a plurality of wirings, switching elements, and pixel electrodes are formed, and a color filter substrate on which a color filter and a common electrode are formed, and liquid crystal molecules between the two substrates are disposed between the pixel electrode and the common electrode. It is driven by an induced electric field, ie a vertical electric field in a direction perpendicular to the substrate.

However, the method of driving the liquid crystal by the vertical electric field has a problem that the viewing angle characteristics are not excellent.

To overcome this problem, a transverse electric field type liquid crystal display device has been proposed. In a transverse electric field type liquid crystal display, pixel electrodes and a common electrode are alternately formed on the same substrate, so that a horizontal electric field in a direction parallel to the substrate is induced between the two electrodes. Therefore, the liquid crystal molecules are driven by a horizontal electric field and move in a direction parallel to the substrate, and such a transverse electric field type liquid crystal display device has an improved viewing angle.

However, such a transverse electric field type liquid crystal display has a low aperture ratio and low transmittance.

Therefore, in order to improve the disadvantage of the transverse electric field type liquid crystal display, a fringe field switching mode LCD for driving a liquid crystal by a fringe field has been proposed.

1 is a plan view of one pixel area in a conventional fringe field switching mode liquid crystal display array substrate.

As shown in the drawing, the gate wiring 43 is formed along one direction, and the data wiring 51 defining the pixel region is formed to cross the gate wiring 43.

A thin film transistor Tr connected to the gate line 43 and the data line 51 is formed in the pixel region, and the thin film transistor Tr includes the gate electrode 45, the active layer 48, and the source electrode 55. ), And a drain electrode 58.

In addition, a pixel electrode 60 connected to the thin film transistor Tr is formed in the pixel region, and the pixel electrode 60 contacts the drain electrode 58 of the thin film transistor Tr through the drain contact hole 59. do. The pixel electrode 60 has a plate shape substantially corresponding to the entire pixel area.

The common electrode 75 is formed to overlap the pixel electrode 60, and the common electrode 75 has a plurality of openings op in the pixel area. The common electrode 75 extends to an adjacent pixel area so as to correspond to the entire surface of the display area including the plurality of pixel areas. Each of the openings op of the common electrode 75 has a bar shape parallel to the data line 51.

FIG. 2 is a cross-sectional view of a pixel region of a conventional fringe field switching mode liquid crystal display array substrate. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. As shown in FIG. 2, the gate electrode 45 is formed on the substrate 10, and the gate insulating film 30 covers the gate electrode 45. An active layer 48 is formed on the gate insulating layer 30 on the gate electrode 45, and an ohmic contact layer 49 formed of two patterns separated thereon is formed. Source and drain electrodes 55 and 58 are formed on the ohmic contact layer 49, and the source and drain electrodes 55 and 58 are spaced apart from the gate electrode 45. On the other hand, the data wiring 51 is formed on the gate insulating film 30. A first passivation layer 50 is formed on the data line 51 and the source and drain electrodes 55 and 58, and the first passivation layer 50 has a drain contact hole 59 exposing the drain electrode 58. Has The pixel electrode 60 is formed on the first passivation layer 50. The pixel electrode 60 has an area substantially corresponding to the pixel area, and contacts the drain electrode 58 through the drain contact hole 59. The second passivation layer 70 is formed on the pixel electrode 60, and the common electrode 75 is formed thereon. The common electrode 75 has a plurality of openings op over the pixel electrode 60. The common electrode 75 overlaps the pixel electrode 60 to form a storage capacitor.

In a fringe field switching mode liquid crystal display device having an array substrate having such a structure, when a voltage is applied to the pixel electrode 60 and the common electrode 75, between the overlapping pixel electrode 60 and the common electrode 75. A fringe field is formed. Therefore, even the liquid crystal molecules positioned on the electrodes are all operated, so that an improved transmittance and aperture ratio can be obtained as compared to the transverse electric field type liquid crystal display device.

By the way, in the fringe field switching mode liquid crystal display, since the storage capacitor formed between the pixel electrode 60 and the common electrode 74 is formed over the entire pixel region, it is three to five times larger than the transverse field type liquid crystal display. It will have capacity. If the capacity of the storage capacitor is too large, it is difficult to charge in high resolution models with short charge times or high frequency models. To improve this, the line width of the gate line 43 or the data line 51 should be increased to reduce the resistance, or the channel width of the thin film transistor Tr should be increased. However, in this case, a reduction of the aperture ratio is caused.

An object of the present invention is to provide an array substrate for a wide viewing angle liquid crystal display device capable of reducing the capacity of a storage capacitor, thereby improving charging characteristics and increasing aperture ratio.

In order to achieve the above object, the array substrate for a wide viewing angle liquid crystal display device of the present invention comprises a gate wiring formed in a first direction on the substrate; A data line formed in a second direction and defining a pixel region crossing the gate line; A thin film transistor electrically connected to the gate line and the data line; A pixel electrode formed in the pixel region, in contact with the drain electrode of the thin film transistor, and including at least one first opening; A protective layer formed on the pixel electrode and covering the thin film transistor, the gate line, and the data line; A common electrode formed on the passivation layer and overlapping the pixel electrode and having a plurality of second openings positioned in the pixel region, wherein the first opening corresponds to a common electrode between adjacent second openings; It is characterized by.

Each of the first and second openings has a major axis disposed in the second direction, wherein the first opening has a width wider than that of the common electrode between the adjacent second openings.

The distance from the common electrode between the adjacent second openings to one side of the first opening is less than 2.5 μm, and the width of the first opening is 2 μm to 7 μm.

In addition, each of the first opening and the second opening has at least one bent portion, wherein each of the first opening and the second opening is a first bent portion in the center of the pixel area, and 1 bend includes the second and third bent portions on both sides.

In addition, the first opening is characterized in that the edge is formed of a concave-convex structure in which a regular or irregular zigzag form.

At this time, the average width of the first opening is characterized in that 2㎛ to 7㎛.

The second opening may have a long axis parallel to the data line, and the first opening may be disposed such that the long axis intersects the long axis of the second opening. Is characterized in that 2㎛ to 4㎛.

In addition, the common electrode may include a third opening that exposes the thin film transistor.

In addition, the pixel electrode is in contact with an upper surface and a side surface of the drain electrode.

In the fringe field switching mode, a first opening corresponding to the common electrode is formed in the pixel electrode, thereby reducing the capacitance of the storage capacitor formed between the two electrodes. Therefore, the charging characteristic can be improved, and the width ratio of the gate and data lines and the size of the thin film transistor can be reduced, thereby improving the aperture ratio.

1 is a plan view of one pixel area in a conventional fringe field switching mode liquid crystal display array substrate.
FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.
3 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention.
4 is a cross-sectional view of an array substrate for a fringe switching mode liquid crystal display device according to a first embodiment of the present invention, and corresponds to a cross section taken along line IV-IV of FIG. 3.
FIG. 5 is a cross-sectional view of an array substrate for a fringe switching mode liquid crystal display device according to a first embodiment of the present invention, and corresponds to a cross section taken along the line VV of FIG. 3.
6 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view of an array substrate for a fringe switching mode liquid crystal display according to a second exemplary embodiment of the present invention, and corresponds to a cross section taken along the line VII-VII of FIG. 6.
FIG. 8 is a cross-sectional view of an array substrate for a fringe switching mode liquid crystal display device according to a first embodiment of the present invention, and corresponds to a cross section taken along the line VII-VII of FIG. 6.
9 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a third exemplary embodiment of the present invention.
10 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a modification of the third embodiment of the present invention.

Hereinafter, an array substrate for a liquid crystal display device according to first, second, and third embodiments of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>

3 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention.

As illustrated, a plurality of gate lines 105 extending in the first direction are formed, and a plurality of data lines 130 are formed to cross the plurality of gate lines 105 and define a plurality of pixel regions. have.

In addition, a thin film transistor Tr connected to the gate line 105 and the data line 130 is formed in each pixel area. The thin film transistor Tr is sequentially stacked and includes a gate electrode 108, a gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon, and an ohmic contact layer (not shown) of impurity amorphous silicon. A semiconductor layer (not shown) and source and drain electrodes 133 and 136 spaced apart from each other are included. In this case, in the drawing, although the thin film transistor Tr has a U-shaped channel as an example, the channel of the thin film transistor Tr may be modified in various forms.

A plate-shaped pixel electrode 155 is formed in each pixel area, and the pixel electrode 155 contacts the drain electrode 136 of the thin film transistor Tr. The pixel electrode 155 has at least one first opening op1.

The common electrode 170 is formed on an entire surface of the display area including the plurality of pixel areas, and the common electrode 170 includes a plurality of second openings op2 spaced apart from each other by a predetermined interval in each pixel area.

Here, the first opening op1 corresponds to the common electrode 170 between the adjacent second openings op2, and partially overlaps the adjacent second openings op2. The first opening op1 preferably has the same shape as the second opening op2. For example, the pixel electrode 155 may have two first openings op1, and the common electrode 170 may have five second openings op2. The number of such first and second openings op1 and op2 is not limited to those shown in the embodiment, but may be changed.

More specifically, each of the second openings op2 is in the form of a bar having multiple bends. That is, each of the second openings op2 has a first bent portion at the center of the pixel region, and has a second and third bent portions symmetrically at the upper and lower portions of the first bent portion. In this case, the distance w1 between the first and second bent portions and between the first and third bent portions, that is, the distance w1 from the second bent portion to the third bent portion is 10 micrometers to 20 degrees. It is preferable that it is about micrometer.

In this case, in each pixel area, an area above the second bent portion on the drawing becomes the first domain region D1, and an area under the third bent portion becomes the second domain region D2, and the second bent portion The area between and the third bent portion is a domain boundary area CA.

In this case, when the rubbing direction of the alignment layer (not shown) formed on the common electrode 170 is in the second direction perpendicular to the gate line 105, the first and second domain regions D1 and D2 may be disposed. Each of the second openings op2 has an angle of ± 7 degrees to ± 10 degrees with respect to the second direction, and each of the second openings op2 located in the domain boundary region CA has ± 15 degrees to ± ± with respect to the second direction. It is desirable to have an angle of 30 degrees. Here, each second opening op2 has a symmetrical structure with respect to the line passing through the first bent portion along the first direction.

As described above, in the exemplary embodiment of the present invention, the first opening op1 corresponding to the common electrode 170 is formed in the pixel electrode 155. Therefore, it is possible to reduce the capacity of the storage capacitor formed between the two electrodes, thereby improving the charging characteristics. In addition, since the width of the wiring and the size of the thin film transistor Tr can be reduced, the aperture ratio can be improved.

On the other hand, each of the second openings op2 has multiple bent portions, so that the initial arrangement angle of the liquid crystal molecules in the domain boundary region CA in each pixel region is significantly different from each other symmetrically. Therefore, even if an external pressure is applied, problems such as the initial arrangement of liquid crystal molecules being made equal by the collapse of the domain boundary can be solved.

In the embodiment of the present invention, the structure of each of the second openings op2 has a plurality of bent portions, but the second openings op2 may be parallel to the second direction without the bent portions, or one bent portion. It may have, and the shape can be changed in various ways.

Hereinafter, a cross-sectional structure of an array substrate for a fringe switching mode liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

4 and 5 are cross-sectional views of an array substrate for a fringe switching mode liquid crystal display according to an exemplary embodiment of the present invention. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3, and FIG. 5 is a cross-sectional view of FIG. Corresponds to the section cut along the VV line.

As shown, the gate electrode 108 is formed on the transparent insulating substrate 101. Although not shown, a gate wiring connected to the gate electrode 108 is also formed on the substrate 101. The gate wiring and the gate electrode 108 may be formed of a metal material having low resistance, for example, an aluminum alloy such as aluminum (Al), aluminum-nedium (AlNd), copper (Cu), copper alloy, chromium (Cr), Molybdenum (Mo) is made of one metal material selected.

A gate insulating layer 115 of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 101 over the gate wiring (not shown) and the gate electrode 108.

A semiconductor layer 120 including an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon is formed on the gate insulating layer 115 to correspond to the gate electrode 208. Subsequently, source and drain electrodes 133 and 136 spaced apart from each other are formed on the semiconductor layer 120. At this time, the active layer 120a is exposed between the source and drain electrodes 133 and 136. Here, the gate electrode 108, the gate insulating layer 115, the semiconductor layer 120, and the source and drain electrodes 133 and 136 form a thin film transistor Tr.

In addition, a data line 130 is formed on the gate insulating layer 115 to cross the gate line (not shown) to define the pixel area, and the data line 130 is a source electrode 133 of the thin film transistor Tr. Connected with In this case, a semiconductor pattern 121 including first and second patterns 121a and 121b of the same material as the active layer 120a and the ohmic contact layer 120b is formed under the data line 130. This is an example, and the semiconductor pattern 121 may be omitted.

A pixel electrode 155 of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO) is formed in the pixel region on the drain electrode 136 and the gate insulating layer 115. have. The pixel electrode 155 has a plate shape and contacts the drain electrode 136 of the thin film transistor Tr. In addition, the pixel electrode 155 includes a first opening op1.

Covering the pixel electrode 155, one selected from an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or an organic insulating material such as benzocyclobutene (BCB) or photoacryl A protective layer 160 made of photo acryl is formed on the entire surface of the substrate 101.

In addition, a common electrode 170 made of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), may be disposed on the front surface of the substrate 101 substantially on the protective layer 160. The common electrode 170 has a plurality of second openings op2.

The first opening op1 corresponds to the common electrode 170 between the adjacent second openings op2 and has a wider width than the common electrode 170 between the adjacent second openings op2. Therefore, the first opening op1 partially overlaps each of the adjacent second openings op2.

At this time, when the distance a from the common electrode 170 corresponding to the first opening op1 to one side of the first opening op1 is 2.5 micrometers or more, a sudden decrease in luminance may occur, and thus staining may occur. high. Therefore, the distance a from the common electrode 170 corresponding to the first opening op1 to one side of the first opening op1 is preferably less than 2.5 micrometers.

This will be described in more detail with reference to Tables 1 and 2. Table 1 shows the transmission efficiency according to the change of the distance a from the common electrode 170 corresponding to the first opening op1 to one side of the first opening op1 with respect to the width of the first opening op1. 2 represents the capacity of the storage capacitor, that is, the storage capacitance. Here, the transmission efficiency and the storage capacitance are measured in a structure in which the number of first openings op1 is three and the number of second openings op2 is eight.

In Tables 1 and 2, an overlay shift refers to a misalignment occurring between the common electrode 170 and the pixel electrode 155, and the distance a depends on the degree of overlay shift.

On the other hand, in Table 1 and Table 2, the increase and decrease ratio indicates a change in transmission efficiency or storage capacitance with respect to the conventional structure when the overlay shift does not occur, and the variation rate is in accordance with the degree of overlay shift with respect to the width of the first opening op1. Change in transmission efficiency or storage capacitance.

First opening width
(Micrometer) Overlay shift
(Micrometer) Distance (a)
(Micrometer) Penetration efficiency
Change rate (variation rate) Conventional 0.0 0 69.50% 0.00% (0.00%) 0.5 0 69.46% (-0.06%) 1.0 0 69.44% (-0.09%) 4 0.0 0.5 68.87% -0.91% (0.00%) 0.5 1.0 68.79% (-0.11%) 1.0 1.5 69.01% (0.21%) 6

0.0 1.0 68.90% -0.87% (0.00%) 0.5 1.5 68.69% (-0.30%) 1.0 2.0 68.55% (-0.51%) 6

0.0 1.5 68.51% -1.43% (0.00%) 0.5 2.0 68.55% (0.07%) 1.0 2.5 66.28% (-3.26%) 7

0.0 2.0 69.25% -0.36% (0.00%) 0.5 2.5 66.51% (-3.95%) 1.0 3.0 63.43% (-8.40%)

As shown in Table 1, when the overlay shift occurs and the distance a becomes 2.5 micrometers or more, the transmission efficiency is lower than that of the conventional 69.60%, such as 66.28%, 66.51%, and 63.43%, resulting in a sudden decrease in luminance. Occurs. Accordingly, staining is likely to occur.

First opening width
(Micrometer) Overlay shift
(Micrometer) Distance (a)
(Micrometer) Storage capacitance (fF) Change rate (variation rate) Conventional 0.0 0 65.31 0.00% (0.00%) 0.5 0 65.71 (0.61%) 1.0 0 66.35 (1.59%) 4 0.0 0.5 50.67 -22.41% (0.00%) 0.5 1.0 52.20 (3.02%) 1.0 1.5 55.50 (9.52%) 6

0.0 1.0 47.69 -26.98% (0.00%) 0.5 1.5 48.96 (2.66%) 1.0 2.0 51.36 (7.70%) 6

0.0 1.5 46.20 -29.26% (0.00%) 0.5 2.0 46.53 (0.72%) 1.0 2.5 48.55 (5.09%) 7

0.0 2.0 44.54 -31.80% (0.00%) 0.5 2.5 45.59 (2.35%) 1.0 3.0 46.15 (3.62%)

On the other hand, as shown in Table 2, when the first opening (op1) is formed in the pixel electrode 155, it can be seen that the storage capacitance is significantly reduced compared to the conventional 65.31 fF (femtofarads). In particular, even when the overlay shift occurs, when the distance (a) is less than 2.5 micrometers, it can be seen that the storage capacitance is at least 44.54 fF, which is reduced by about 30% compared with the conventional art.

As such, the distance a from the common electrode 170 corresponding to the first opening op1 to one side of the first opening op1 is preferably less than 2.5 micrometers.

Meanwhile, in the first embodiment of the present invention, the structure in which the pixel electrode is formed at the bottom and the common electrode is formed at the bottom has been described. However, the common electrode is formed at the bottom and the pixel electrode is formed at the top. It may have a first opening for reduction, and the pixel electrode may have a second opening.

&Lt; Embodiment 2 >

6 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention. In this case, for the convenience of description, the same reference numerals are added to the same elements as in the first embodiment.

As illustrated, a plurality of gate lines 205 extending in the first direction are formed, and a plurality of data lines 230 crossing the plurality of gate lines 205 and defining a plurality of pixel regions P are defined. Is being formed.

In addition, a thin film transistor Tr connected to the gate line 205 and the data line 230 is formed in each pixel area P. Referring to FIG. The thin film transistor Tr is sequentially stacked and includes a gate electrode 208, a gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon, and an ohmic contact layer (not shown) of impurity amorphous silicon. A semiconductor layer (not shown) and source and drain electrodes 233 and 236 spaced apart from each other are included. In this case, in the drawing, although the thin film transistor Tr has a U-shaped channel as an example, the channel of the thin film transistor Tr may be modified in various forms.

A plate-shaped pixel electrode 255 is formed in each pixel area P, and the pixel electrode 255 contacts the drain electrode 236 of the thin film transistor Tr. The pixel electrode 255 has at least one first opening op1. In this case, the at least one or more first openings op1 provided in the pixel areas P may have the longest direction in the gate wiring 205 in the second embodiment. ) Is arranged in the direction parallel to or in the direction perpendicular to the long axis of the second opening (op2).

That is, in the first embodiment (see FIG. 3), the first opening (op1 in FIG. 3) provided in the pixel electrode (155 in FIG. 3) has a long axis parallel to the data line (130 in FIG. 3). In the second exemplary embodiment, the first opening op1 may be arranged in parallel with the gate wiring 205 or in parallel with the data wiring 230. The long axis is arranged so as to intersect with). At this time, it is preferable that the width (shortening length) of the first opening op1 is about 2 μm to 4 μm.

Meanwhile, a common electrode 270 is formed on an entire surface of the display area including the plurality of pixel regions P, and the common electrodes 270 are spaced apart from each other in the pixel regions P by a predetermined distance. Two openings op2. In this case, the plurality of second openings op2 may have a long axis arranged in parallel with the data line 230.

Accordingly, the first and second openings op1 and op2 are formed to cross each other by the above-described long axis arrangement structure, and each pixel region P is planar by the first and second openings op1 and op2. It is characterized by forming a lattice structure.

In this way, the first and second openings op1 and op2 are formed to cross each other in each pixel area P, so that the first and second openings op1 and op2 intersect each other (hereinafter referred to as a first region). Since the pixel field 255 and the common electrode 270 are not formed, the free field is unlikely to be formed, but the width of the first opening op1 is about 2 μm to 4 μm. It can be seen that the fringe field is still formed by the common electrode 270 and the pixel electrode 255 positioned around the first region. Therefore, when the width of the first opening op1 is about 2 μm to 4 μm, the first opening op1 and the second opening op2 overlap each other in the pixel area P to be common with the pixel electrode 255. Even if a first region in which the electrode 270 is not formed partially occurs, the fringe field is still formed by the common electrode 270 and the pixel electrode 255 formed around the first region, so that the first region has luminance. The problem such as the reduction or the like does not occur because it does not occur.

In the drawing, although six first openings op2 and five second openings op2 are formed in each pixel area P, the number of the first and second openings op1 and op2 is shown. Is not limited to that shown in the second embodiment, and may be variously changed.

On the other hand, each of the second openings (op2) is shown to form a bar (bar) having a plurality of bent portions as in the first embodiment, the first embodiment with respect to the shape of the second opening (op2) Since it has been described in detail through the description below will be omitted.

As described above, in the second embodiment of the present invention, at least one pixel area P is formed in the pixel electrode 255 in the pixel electrode 255 so as to cross the plurality of second openings op2 formed in the common electrode 270. One opening op1 is provided. Therefore, the capacitance of the storage capacitor formed between the pixel electrode 255 and the common electrode 270 overlapping each other with the protective layer 260 interposed therebetween can be reduced, thereby improving charging characteristics. In addition, since the width of the wiring and the size of the thin film transistor Tr can be reduced, the aperture ratio can be improved.

That is, according to the second embodiment of the present invention, the storage capacitor is substantially as large as the total area of the first opening op1 having the long axis arranged in parallel with the gate wiring 205 in the pixel electrode 255. By reducing the capacity it is possible to improve the charging characteristics.

 In the array substrate 201 for the fringe field switching mode liquid crystal display according to the second embodiment of the present invention, the first opening op1 intersects the second opening op2 in each pixel area P. Although the patterning error within the allowable range in the manufacturing process is generated by being formed in a direction parallel to the gate wiring 205, an area in which the first and second openings op1 and op2 overlap each other in the pixel area P is overlapped. Since it can be kept constant compared to the first embodiment, it is characterized in that it has the effect of suppressing the luminance decrease and the occurrence of spots caused by the overlap area is changed by the patterning error.

That is, when the pixel electrode having the first opening op1 is formed and then the common electrode 270 having the second opening op2 is formed, one of the directions of up / down / left / right sides is changed due to a patterning error. In the second embodiment, the first and second openings op1 and op2 are formed to cross each other. If the second openings op1 and p2 are formed only in each pixel area P, the overlap area is the same even if a shift occurs during the patterning. In other words, the same area of the first and second openings op1 and op2 overlapping each other is the same as that of the pixel electrode 255 and the common electrode 270 overlapping each other. The area of the first region overlapping between (op1, op2) is always kept constant, and since the fringe field is formed in the first region, problems such as luminance reduction and spotting do not occur.

Meanwhile, although the common electrode is formed on the entire display area except for the portion where the second opening op2 is formed corresponding to each pixel area P, the common electrode 270 is formed on each pixel area P. Therefore, a third opening (not shown) may be further formed to correspond to the region where the thin film transistor Tr is formed, more precisely, the region where the channel, which is a separation region between the source and drain electrodes 233 and 236, is formed. It is apparent that the third opening (not shown) may be formed in the array substrate (101 in FIG. 3) for the fringe field switching mode liquid crystal display according to the first embodiment.

FIG. 7 is a cross-sectional view of a portion taken along the cutting line VII-V and FIG. 8 is a cross-sectional view of a portion taken along the cutting line VII-V.

The cross-sectional structure according to the second embodiment is the same as that of the first embodiment except that the long-axis arrangement of the first opening op1 provided in the pixel electrode 255 is formed along the gate wiring (not shown).

First, referring to FIG. 7, which is a cross-sectional view taken along the first opening op1, in the case of the array substrate 201 for a fringe field switching mode liquid crystal display device according to the second embodiment of the present invention, the gate insulating film 215 is used. The pixel electrode 255 having one first opening op11 is formed thereon, and the common electrode 270 having a plurality of second openings op1 is formed on the upper portion of the pixel electrode 255 through the protective layer 260. Although it appears to be formed, this is because it is a cross-sectional view of a portion cut along the long axis of the first opening op1 from which the pixel electrode is removed, and the first opening op1 is also at least one in each pixel region P. FIG. More than one can be formed.

On the contrary, referring to FIG. 8, which is cut along a portion where the first opening op1 is not formed in the pixel electrode 255, the first opening may be formed on the gate insulating film 215 as if the entire pixel region P was formed. It is shown that the pixel electrode 255 is formed without op1), and the common electrode 270 is formed with a plurality of second openings op2 through the protective layer 260 thereon. This cross-sectional shape will also be called according to the characteristics of the cut portion.

In addition to the above-described parts, the stacked structure of a thin film transistor (not shown) and the like are the same as those of the first embodiment described above, and thus description thereof is omitted.

Third Embodiment

9 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a third embodiment of the present invention, and FIG. 10 is a fringe field switching mode according to a modification of the third embodiment of the present invention. Fig. 1 is a plan view of one pixel region of the array substrate for a liquid crystal display device. In this case, for the convenience of description, the same components as in the first embodiment are denoted by the reference numeral 200 added. In the case of the third embodiment, only the shape of the first opening op1 provided in the pixel electrode 355 is different, and all other components are the same as those of the first embodiment.

Referring to the drawings, a part different from the first embodiment is in the form of the first opening op1 provided in the pixel electrode 355. In the case of the first embodiment (see FIG. 3), the first opening (op1 in FIG. 3) has a bar shape in which a central portion thereof has a plurality of bent portions, and a boundary thereof, that is, a border portion has a smooth straight line shape. However, the first opening op1 provided in the third embodiment has the same thing as having a plurality of bent portions w1 in the center thereof, but the edge thereof is formed in a zigzag form with a concave-convex structure. At this time, the zigzag shape is formed irregularly (for example, irregular saw tooth shape) as shown in FIG. 9 or is regular (for example, rectangular shape as shown in FIG. 10 showing a modification of the third embodiment). Of the convex portions may be formed in a predetermined spaced apart form).

In this case, as shown in FIG. 9, the width of the first opening op11 having an irregular zigzag edge, that is, the short length of the first opening op1 is small by position. In the case of forming a regular zigzag form as shown in FIG. 10, the bar has a configuration in which convex parts are formed on one side and convex parts on the other side, and have the same width for each position.

In this way, the edge of the first opening op1 has an irregular or regular zigzag-shaped uneven structure, that is, overlay shift variation caused by a process error, that is, the first opening op1 and the first opening. This is to minimize the variation of the overlapping area with the two openings op2.

As described above, since the edge of the first opening op1 has an irregular or regular zigzag shape, one pixel region P may be compensated and canceled when the overlay region is changed in the extension direction of the gate wiring 305. The change in overlapping area between the pixel electrode 355 and the common electrode 370 in the inside is minimized so that the change in the storage capacitor capacity can be minimized.

For example, it is assumed that the pixel electrode 355 having the first opening op1 is entirely patterned outwardly, and the convex parts disposed at one side of the first opening op1 are spaced apart to the left by a predetermined interval to the common electrode 370. ) And the overlapping area becomes larger, but on the contrary, the convex portion located on the other side of the first opening op1 is also moved to the left, thereby reducing the area overlapping with the common electrode.

Therefore, due to the zigzag-shaped concave-convex structure formed on the edge of the first opening op1, the overlapped area can be minimized when the overlay fluctuations from side to side due to the manufacturing process error are minimized, thereby minimizing the luminance variation and defect due to the change of the storage capacitor capacity. can do.

Table 3 shows the transmission efficiency according to the distance change from the common electrode 370 corresponding to the first opening op1 to one side of the first opening op1 with respect to the width of the first opening op1. Here, the transmission efficiency is a result measured in a structure in which the number of the first openings op1 is three and the number of the second openings op2 is eight.

In Table 3, an overlay shift refers to a misalignment occurring between the common electrode 370 and the pixel electrode 355, and corresponds to the first opening op1 with respect to the width of the first opening op1. The change in distance from the common electrode 370 to one side of the first opening op1 depends on the degree of overlay shift.

First opening width
(Micrometer) Overlay shift
(Micrometer) Third embodiment First embodiment Penetration efficiency Penetration efficiency
Conventional
0.0 69.5% 69.50% 0.5 69.46% 69.46% 1.0 69.44% 69.44%
4
0.0 69.69% 68.87% 0.5 69.47% 68.79% 1.0 69.68% 69.01%
5
0.0 69.10% 68.90% 0.5 69.57% 68.69% 1.0 69.85% 68.55%
6
0.0 69.31% 68.51% 0.5 68.43% 68.55% 1.0 68.03% 66.28%

As shown in Table 3, when the first opening op1 is formed in the pixel electrode 355 so as to have a zigzag-shaped concave-convex structure, when overlay shifts do not occur in terms of transmission efficiency, respectively. It can be seen that the transmission efficiency was improved by having the transmission efficiencies of 69.69%, 69.10%, and 69.31% compared to the first embodiment having the linear boundary having the transmission efficiencies of 68.87%, 68.90%, and 68.51%. In this case, although not shown in Table 3, the variation of the storage capacitor capacity due to the change of the overlay shift is less stable than that of the first embodiment in the third embodiment. It is done.

The width and the spacing interval of the first opening op1 and the second opening op2 according to the third embodiment all follow the range shown in the first embodiment. That is, the first opening op1 corresponds to the common electrode 370 between the adjacent second openings op2, and has a width wider than that of the common electrode 370 between the adjacent second openings op2. The first opening op1 has a configuration that partially overlaps each of the adjacent second openings op2.

At this time, when the distance from the common electrode 370 corresponding to the first opening op1 to one side of the first opening op1, more precisely, the end of the convex portion is 2.5 μm or more, luminance decreases, which may result in unevenness. Since the height is high, the distance from the common electrode 370 corresponding to the first opening op1 to the end of the iron ball of the first opening op1 is preferably less than 2.5 μm.

In addition, it was found experimentally that the average width (shortened length) of the first opening op1 is preferably 2 μm to 7 μm. Although the width of the first opening op1 is not mentioned in the first embodiment, it can be seen from the experiment that the width of the first opening op1 is also in the range of 2 μm to 7 μm. there was.

On the other hand, in the case of the third embodiment of the present invention and modifications thereof, except for the shape of the first opening op1 described above, the planar structure is the same as the first embodiment described above, and the cross-sectional structure thereof is also the first embodiment. Since the description is the same as that, the description is omitted.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: array substrate
115: gate insulating film
155 pixel electrode
160: protective layer
170: common electrode
a: distance from the common electrode corresponding to the first opening to one side of the first opening
op1: first opening
op2: second opening

Claims (13)

A gate wiring formed on the substrate in a first direction;
A data line formed in a second direction and defining a pixel region crossing the gate line;
A thin film transistor electrically connected to the gate line and the data line;
A pixel electrode formed in the pixel region and in contact with the drain electrode of the thin film transistor, the pixel electrode including at least one first opening;
A protective layer formed on the pixel electrode and covering the thin film transistor, the gate wiring, and the data wiring;
A common electrode formed on the passivation layer and overlapping the pixel electrode and having a plurality of second openings positioned in the pixel region;
Including;
And the first opening corresponds to a common electrode between adjacent second openings.
The method of claim 1,
And each of the long axes of the first opening and the second opening is arranged in the second direction.
The method of claim 2,
And the first opening has a width wider than that of the common electrode between the adjacent second openings.
The method of claim 3, wherein
And a distance from the common electrode between the adjacent second openings to one side of the first opening is less than 2.5 μm.
The method of claim 4, wherein
The width of the first opening is 2㎛ 7㎛ array substrate for a wide viewing angle liquid crystal display device.
The method of claim 2,
And each of the first opening and the second opening has at least one bent portion.
The method according to claim 6,
Each of the first opening portion and the second opening portion includes a first bent portion at the center of the pixel region and second and third bent portions at both sides of the first bent portion. .
The method of claim 3, wherein
And the first opening is formed in a concave-convex structure whose edges are regularly or irregularly zigzag-shaped.
The method of claim 8,
The average width of the first opening is 2㎛ 7㎛ array substrate for a liquid crystal display device.
The method of claim 1,
And wherein the second opening has a long axis parallel to the data line, and the first opening is disposed such that the long axis intersects the long axis of the second opening.
The method of claim 10,
The width of the first opening is 2㎛ 4㎛ array substrate for a wide viewing angle liquid crystal display device.
The method according to any one of claims 1, 8 and 10,
And the third opening is formed in the common electrode to expose the thin film transistor.
The method according to any one of claims 1, 8 and 10,
And the pixel electrode is in contact with the top and side surfaces of the drain electrode.

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