KR20110066737A - Array substrate for fringe field switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: A fringe field switching mode array panel for a liquid crystal display device is provided to reduce driving voltage by minimizing the parasitic capacitance between a data line and a common electrode. CONSTITUTION: A fringe field switching mode array panel for a liquid crystal display device comprises a gate line formed on a transparent substrate, a gate insulation layer formed on the gate line, a data line(130) which defines a pixel(P) area by perpendicularly crossing the gate line on the gate insulation layer, a TFT(Tr) which is formed on the intersection area of the gate line and the data line, a pixel electrode(138) which is formed on the pixel region by touching with a drain electrode(136) of the TFT on the gate insulation layer, and an etch stopper(145) which if formed on each pixel area on a first protective layer.

Description

Array substrate for fringe field switching mode liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of reducing power consumption.

In general, the liquid crystal display device is driven by using the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as liquid crystal table market value), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are caused by an electric field applied up and down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other, and the liquid crystal layer 11 is interposed between the upper and lower substrates 9, 10. It is.

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane. In this case, the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views illustrating operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by the horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, in the transverse electric field type liquid crystal display device, since the liquid crystal moves by the horizontal electric field, the viewing angle is widened.

Therefore, when viewed from the front, the transverse electric field type liquid crystal display device can be seen in the up / down / left / right directions without inversion phenomenon even in about 80 to 85 degrees.

Next, referring to FIG. 2B, since no voltage is applied to the liquid crystal display, a horizontal electric field is not formed between the common electrode and the pixel electrode, so that the arrangement state of the liquid crystal layer 11 does not change.

However, such a transverse field type liquid crystal display device has an advantage of improving the viewing angle, but has a disadvantage of low aperture ratio and low transmittance.

Therefore, in order to characterize the shortcomings of the transverse electric field type liquid crystal display, a fringe field switching mode LCD is characterized in that the liquid crystal is operated by a fringe field.

3 is a cross-sectional view of a portion cut through a central portion of one pixel area of a conventional fringe field switching mode liquid crystal display array substrate.

As shown, the conventional fringe field switching mode liquid crystal display array substrate 41 has a plurality of pixel regions (not shown) intersecting with each other at a lower portion and an upper portion thereof through a gate insulating layer 45 to define a gate wiring. (Not shown) and data lines 47 are formed, and each of the pixel regions (not shown) is connected to the gate and data lines (not shown) 47 and a thin film transistor (not shown) is formed.

In addition, the pixel electrode 55 in the form of a plate is formed in each pixel region (not shown) on the gate insulating layer 45 to contact the drain electrode (not shown) of the thin film transistor. In this case, the pixel electrode 55 is formed on the same layer as the data line 47, that is, on the gate insulating layer 45, and the data line 47 is prevented from being shorted with the data line 47. ) And spaced apart at regular intervals.

In addition, a protective layer 60 is formed on the front surface of the data line 47 and the pixel electrode 55 as an inorganic insulating material, and corresponds to each pixel region (not shown) on the front surface of the protective layer 60. Thus, the common electrode 65 is spaced apart from each other and has a plurality of openings (oa) having a bar shape.

The conventional fringe field switching mode liquid crystal display array substrate 41 having such a cross-sectional configuration has a structure in which the common electrode 65 is positioned at the top and formed on the entire display area, and thus corresponds to the data line 47. Also, the common electrode 65 is formed to overlap with the protective layer 60.

Therefore, the data line 47, the protective layer 60, and the common electrode 67 overlapping each other form a parasitic capacitor, and the protective layer in order to perform fringe field switching driving in consideration of the influence on the parasitic capacitor. Has a thickness of at least 6000Å.

In this case, since the separation distance between the common electrode and the pixel electrode is at least 6000 kV, the driving voltage for forming the fringe field for driving the liquid crystal to maintain the proper display quality is relatively large, thus increasing power consumption.

In a conventional fringe field switching mode liquid crystal display array substrate having such a configuration, when the driving voltage is lowered, the transmittance is decreased, the contrast ratio is lowered, and the display quality is lowered.

In addition, when the protective layer is formed to have a thickness smaller than about 6000 mW, the distance between the common electrode and the data line is reduced, and thus, power consumption is increased again due to the increase of parasitic capacitance by these components.

The present invention has been made to solve the problem of the conventional array substrate for fringe field switching mode liquid crystal display device, and is formed by the pixel electrode and the common electrode by lowering the thickness of the protective layer interposed between the pixel electrode and the common electrode. It is an object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device which can increase the fringe field strength and reduce the power consumption by minimizing the parasitic capacitance between the data line and the common electrode.

An array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention for achieving the above object includes a gate wiring formed extending in one direction on a transparent substrate; A gate insulating film formed over the gate wiring; A data line over the gate insulating layer, the data line crossing the gate line and defining a pixel area; A thin film transistor electrically connected to the gate line and the data line and formed near an intersection point of the two lines; A pixel electrode on the gate insulating layer and in contact with the drain electrode of the thin film transistor and formed in the pixel region; A first passivation layer formed on the entire surface of the substrate over the pixel electrode and having a first thickness; An etch stopper formed in each pixel area over the first passivation layer; A second protective layer having a second thickness on the entire surface of the substrate above the etch stopper; And a common electrode having a plurality of first openings having a bar shape spaced apart from each other in the pixel area over the second protective layer, wherein the second protective layer corresponds to the plurality of first openings. The groove is formed to expose the etch stopper.

In this case, the first protective layer is provided with a first contact hole exposing the pixel electrode, and the etch stopper is in contact with the pixel electrode through the first contact hole.

According to still another aspect of the present invention, an array substrate for a fringe field switching mode liquid crystal display device includes: a gate wiring extending in one direction on a transparent substrate; A gate insulating film formed over the gate wiring; A data line over the gate insulating layer, the data line crossing the gate line and defining a pixel area; A thin film transistor electrically connected to the gate line and the data line and formed near an intersection point of the two lines; A first protective layer having a first thickness on the entire surface of the substrate over the thin film transistor; A pixel electrode formed in contact with the drain electrode of the thin film transistor on each pixel area over the first passivation layer; A second protective layer formed on the entire surface of the substrate over the pixel electrode and having a second thickness; And a common electrode having a plurality of first openings having a bar shape spaced apart from each other in the pixel area over the second protective layer, wherein the second protective layer corresponds to the plurality of first openings. The groove is formed to expose the etch stopper.

The first protective layer includes a drain contact hole exposing the drain electrode of the thin film transistor, wherein the pixel electrode is in contact with the pixel electrode through the drain contact hole, array for a fringe field switching mode liquid crystal display device Board.

The first thickness is 3000 kPa to 4000 kPa, and the second thickness is 2000 kPa to 3000 kPa, wherein the sum of the first and second thicknesses is 6000 kPa or more, wherein the first and second protective layers are It is made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) which is an inorganic insulating material.

In addition, the common electrode is characterized in that the second opening is formed corresponding to the thin film transistor.

In addition, the pixel electrode is made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material.

In addition, the etch stopper is made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, and has the same planar shape as that of the pixel electrode.

In the array substrate for a fringe field switching mode liquid crystal display device according to the present invention, a double layer protective layer having a thickness of 6000 Å or more is formed between the data line and the common electrode, and the first protective layer is removed between the common electrode and the pixel electrode. By forming the grooves, there is an effect of improving the fringe field strength applied to reduce the driving voltage.

By reducing the driving voltage, there is an effect of reducing the power consumption.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. Although not shown in the drawings for convenience of description, an area in which a plurality of pixel areas P is formed is defined as a display area, and an area outside the display area is referred to as a non-display area, and an area in which the thin film transistor Tr is formed is an element area. This is defined as.

As illustrated, a plurality of gate wires 105 are formed in the display area and extend in a first direction, and extend in a second direction orthogonal to the first direction and include a plurality of pixel areas P together with the gate wires. A large number of data wires 130 are defined.

In addition, the gate line 105 and the data line 130 are connected to the inside of each of the plurality of pixel regions P or to boundaries of the pixel regions P, and the gate electrode 108 and the gate insulating layer (not shown). And a semiconductor layer (not shown) consisting of an active layer (not shown) of pure amorphous silicon and an ohmic contact layer (not shown) of impurity amorphous silicon, and source and drain electrodes 133 and 136 spaced apart from each other. The thin film transistor Tr is formed.

In this case, although the separation region (hereinafter, referred to as a channel region) between the source and drain electrodes 133 and 136 forms a '-' shape, the channel region may be modified in various forms. have. For example, when the source electrode 133 is formed in a 'U' shape, and the drain electrode 136 is formed to be inserted into an opening of the 'U' type source electrode 133, the channel region is formed of 'U'. Form.

In addition, although the thin film transistor Tr is formed on the boundary of the pixel region P and a part of the pixel region P in the drawing, the semiconductor layer (not shown) and the source and drain electrodes 133 and 136 are shown. ) May be formed to completely overlap the gate wiring 105 to be formed at the boundary of each pixel region P, thereby improving the aperture ratio.

The pixel electrode 138 is formed in contact with the drain electrode of the thin film transistor Tr.

Further, although not shown in the drawing, a first passivation layer (not shown) is formed on the pixel electrode 138, and the pixel electrode (not shown) is formed in each pixel area P above the first passivation layer (not shown). An etch stopper 145 is formed to have the same planar area as that of 138 and completely overlap. In addition, a second protective layer (not shown) is formed on the etch stopper 145 as an inorganic insulating material.

On the second passivation layer (not shown), a common electrode (not shown) having a plurality of first openings op1 having a bar shape spaced apart from each other in correspondence to each pixel area P is formed. Is characteristic.

In this case, as a characteristic configuration, a groove for exposing the etch stopper 145 is formed by removing the second protective layer (not shown) corresponding to the first opening op1.

Since such a configuration is well shown through the cross-sectional structure, a cross-sectional structure of the array substrate for the fringe field switching mode liquid crystal display device according to the first embodiment will be described later.

5 is a cross-sectional view of a portion taken along the cutting line VV of FIG. 4. For convenience of description, a portion in which a thin film transistor, which is a switching element, is formed is defined as an element region TrA.

As shown, a metal material having low resistance, for example, aluminum (Al), is formed on the transparent insulating substrate 101 that forms the base of the array substrate 101 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. ), An aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), molybdenum (Mo) is a metal material selected from the gate wiring (not shown) extending in one direction is formed, A gate electrode 108 is formed in the device region TrA in connection with the gate line.

In addition, a gate insulating film 115 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 101 over the gate wiring 105 and the gate electrode 108. have.

The semiconductor layer 120 including the active layer 120a of pure amorphous silicon and the ohmic contact layer 120b of impurity amorphous silicon is formed in the device region TrA on the gate insulating layer 115 in response to the gate electrode 108. The source and drain electrodes 133 and 136 are spaced apart from each other above the semiconductor layer 120. In this case, the active layer 120a is exposed between the source and drain electrodes 133 and 136 spaced apart from each other.

In addition, an upper portion of the gate insulating layer 115 intersects the gate line 105 to define a pixel region P, is connected to a source electrode 133 of the thin film transistor Tr, and a data line 130 is formed. have. In this case, although the first and second dummy patterns 121a and 121b are formed under the data line 130 with the same material forming the semiconductor layer 120, the first and second dummy patterns are formed. 121a and 121b are due to the manufacturing method and may be omitted.

Next, in each of the pixel regions P, a plate-shaped pixel electrode 138 directly contacting one end of the drain electrode is formed on the gate insulating layer 115 and is formed of a transparent conductive material.

In addition, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the thin film transistor Tr and the pixel electrode 138, and has a first thickness of about 3000 μm to 4000 μm and has a first protective layer. 140 is formed.

An etch stopper 145 is formed on the first passivation layer 140 by patterning a transparent conductive material using the same exposure mask used to form the pixel electrode 138 as a characteristic configuration of the present invention. Formed. At this time, the etch stopper 145 is preferably about 200 ~ 500Å thickness. This is because when the thickness is thicker than this, the driving voltage is increased by increasing the separation distance between the common electrode 160 and the pixel electrode 138 to be formed later.

Next, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), has a second thickness of about 2000 μs to 3000 μs and a second protective layer 150 is formed on the etch stepper 145. have.

  Accordingly, in each pixel area P, the first and second passivation layers 140 and 150 have a structure separated from the etch stopper 145, but other than the pixel area P, namely, In the boundary region of the pixel region P in which the gate and the data line (not shown) 130 are formed and the element region TrA, they are formed in contact with each other to form one protective layer. In this case, the thickness of the first and second protective layers 140 and 150 in direct contact with each other is at least 6000 μs.

Next, a common electrode 160 having a plurality of bar-shaped first openings op1 spaced apart from each other by a predetermined distance on the second passivation layer 150 as a transparent conductive material. It is formed on the entire display area. In this case, the common electrode 160 has a second opening op2 also corresponding to the device region TrA. This is to minimize the influence on the channel region and to minimize the parasitic capacitance generated by overlapping the source and drain electrodes 133 and 136.

Next, as another characteristic structure in the first embodiment of the present invention, the second protective layer 150 is removed from the first opening op1 of the common electrode 160 to form a groove, and the etch stopper It is characterized by forming the form to expose (145).

In this case, the common electrode 160 and the second passivation layer 150 are formed with the first opening op1 and the groove, thereby increasing the intensity of the electric field with the pixel electrode 138. That is, the second protective layer 150 having a second thickness of about 2000 μs to 3000 μs is removed to correspond to the first opening op1 of the common electrode 160, so that the common electrode is formed through the first opening op1. The fringe field strength formed between the 160 and the pixel electrode 138 is improved. By removing part of the material layers (first and second protective layers) that hinder the electric field formation, a fringe field having a greater intensity is formed for application of the same driving voltage, thereby forming a fringe field of the same intensity as in the prior art. In this case, the driving voltage can be lowered.

On the other hand, removing the second protective layer 150 corresponding to the first opening op1 provided in the common electrode 160 causes the common electrode 160 itself to be an etching prevention mask, and the first opening ( By performing dry etching in a reaction gas atmosphere capable of etching the inorganic insulating material in a state in which the common electrode 160 having the op1) is formed, it can be achieved without a separate mask process.

During the dry etching process, since the etch stopper 145 is formed in each pixel area P, the first protective layer 140 positioned below the substrate is not affected at all. Therefore, it is a feature that the display quality can be fundamentally prevented from being caused by unevenness caused by the difference in the fringe field strength due to the difference in depth of the groove corresponding to the first opening op1.

Meanwhile, when the etch stopper 145 is not formed as described above, when the first and second protective layers 140 and 150 are made of the same inorganic insulating material, an etch rate difference may occur for each position during dry etching. As a result, a difference in fringe field strength may occur, which may cause display quality deterioration, such as spot defects caused by partial luminance differences. In addition, due to the characteristics of the inorganic insulating material, when the dry etching is stopped in the middle to adjust the thickness, staining occurs due to the difference in uniformity of the thickness.

However, in the case of the first embodiment of the present invention, since the etch stopper 145 is provided, only the second protective layer 150 can be exactly removed, so that the etching error due to the dry etching process does not occur, the occurrence of stain defects is fundamental. It is a feature that can be prevented.

In this case, since the common electrode 160 is formed to correspond to the portion where the data line 130 is formed, since the second protective layer 150 is not etched, both the first and second protective layers 140 and 150 are formed. Maintain thickness more than 6000. Therefore, it can be seen that the parasitic capacitance generated by the data line 130 and the common electrode 160 is the same level as in the related art.

6 is a cross-sectional view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display device according to a modification of the first embodiment of the present invention. Only the parts which differ from the first embodiment will be described. The same reference numerals are given to the same components as those in the first embodiment by adding 100.

A configuration different from that of the first embodiment is that the pixel electrode 238 and the etch stopper 245 formed on and under the first protective layer 240 are provided in the first protective layer 240. It is formed to be in contact with each other through the first contact hole 241. Other components have the same configuration as that of the first embodiment.

In the modified example of the first embodiment having the above configuration, the etch stopper 245 having the same shape as that of the pixel electrode 238 and formed for each pixel region P is formed from the drain electrode 236 through the pixel electrode 238. Since the signal voltage is input, the signal voltage substantially serves as the second pixel electrode.

Therefore, the gap between the common electrode 260 and the etch stopper 245 serving as the second pixel electrode is reduced compared to the gap between the common electrode 260 and the pixel electrode 238, thereby further increasing the maximum transmittance. The driving voltage can be reduced.

At this time, since the first and second passivation layers 240 and 250 are still present between the data line 230 and the common electrode 260, there is a separation interval of 6000 μs or more, and thus the parasitic capacitance is the same as before. Becomes In addition, the separation interval between the common electrode 260 forming the fringe field and the etch stopper 245 serving as the second pixel electrode may be about 2000 kPa to about 3000 kPa, which is the second thickness of the second protective layer 250. Since a groove is formed in the second passivation layer 250 to expose the etch stopper 245 serving as the second pixel electrode, corresponding to the first opening op1 provided in the common electrode 260. It is a characteristic that the driving voltage can be significantly reduced.

Since other components are the same as those of the first embodiment described above, the description thereof will be omitted.

7 is a transmittance characteristic curve according to a change in driving voltage.

As shown, in the case of a conventional array substrate for a fringe field switching mode liquid crystal display device having a protective layer having a thickness of about 6000 mA, a driving voltage that maximizes transmittance is 4.5 V, but is about 2000 mA. In the case of the array substrate (denoted as the first embodiment) for a fringe-filled switching mode liquid crystal display device according to the first embodiment of the present invention, in which a second protective layer having a thickness of 9 is removed corresponding to the first opening of the common electrode, It can be seen that the driving voltage is lowered as compared with the prior art as the driving voltage is maximized to 3.4V.

In addition, in the modified example (denoted as the modified example) of the first embodiment in which the etch stopper is connected to the pixel electrode, the driving voltage for maximizing the transmittance becomes 2.9 V, indicating that the driving voltage is significantly lower than in the related art.

When the driving voltage for forming the fringe field is reduced, power consumption can be reduced, and when applied to an application product such as a notebook or a mobile phone, the battery life can be improved.

8 is a cross-sectional view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to a second exemplary embodiment of the present invention. In this case, the same components as those of the first embodiment are denoted by the reference numerals by adding 200, and the description will be mainly given on the parts having a difference from the first embodiment.

In the second embodiment of the present invention, the most distinctive configuration that is different from the first embodiment is that the pixel electrode 346 also serves as an etch stopper.

Referring to the drawing, as in the first embodiment, the device region TrA is connected to a gate and data line (not shown) 330 which defines a pixel region P by crossing each other with a gate insulating layer 315 interposed therebetween. And a thin film transistor (Tr), and a first protection having a first thickness of 3000 kPa to 4000 kPa as an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the thin film transistor Tr. Layer 240 is formed.

In the first embodiment, although the pixel electrode (138 in FIG. 5) is formed on the gate insulating film 115 in direct contact with the drain electrode (136 in FIG. 5) of the thin film transistor (Tr in FIG. 5). In the second embodiment, the first protective layer 340 is formed on the gate insulating layer 315.

In this case, the first protective layer 340 is characterized in that the drain contact hole 342 for exposing one end of the drain electrode 336 of the thin film transistor (Tr) is provided.

Next, each pixel region P may be in contact with the drain electrode 336 through the drain contact hole 342 as a transparent conductive material over the first protective layer 340 having the drain contact hole 342. Each pixel electrode 346 is formed.

In addition, a second passivation layer 340 having a second thickness of about 2000 μs to 3000 μs is formed on the entire surface of the pixel electrode 346, and a transparent conductive material is formed on the entire surface of the display area on the second passivation layer 340. As a result, a common electrode 360 having a plurality of first openings op1 having a bar shape spaced apart from each other by a predetermined interval corresponding to each pixel region P is formed.

In this case, the second passivation layer 340 is provided with a groove for exposing the pixel electrode 346 by being removed corresponding to the plurality of first openings op1 of the common electrode 360 as in the first embodiment. It is characterized by being.

In the case of the array substrate 301 for the fringe field switching mode liquid crystal display device according to the second embodiment having the above-described configuration, the parasitic capacitance of the data line 330 and the common electrode 360 is the same as in the modification of the first embodiment. Since the first and second protective layers 340 and 350 having a thickness of 6000 Å or more are formed between these two components 330 and 360, the same level as that of the conventional fringe field switching mode liquid crystal display array substrate is maintained. The second protective layer 350 having a first thickness of 2000 μs to 3000 μs may be formed between the pixel electrode 346 and the common electrode 360, and may be formed in the first opening op1 of the common electrode 360. Correspondingly, since the grooves from which the second protective layer 350 is removed are provided, the driving voltage can be reduced to the level of the array substrate for the fringe-filled switching mode liquid crystal display device according to the modification of the first embodiment. All.

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention having the aforementioned structural features will be described with reference to FIGS. 4 and 5. In this case, the modifications of the first embodiment and the second embodiment will simply refer only to the parts that differ from the first embodiment in each process step. Meanwhile, for convenience of description, a region in which the thin film transistor Tr is formed in each pixel region P is defined as an element region TrA.

First, a first metal material having low resistance on the transparent insulating substrate 101, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), molybdenum (Mo) Forming a first metal layer (not shown) by attaching a selected material, and subsequently applying a photoresist, exposing the photoresist, developing the exposed photoresist, etching the first metal layer (not shown), and photoresist. A mask process including a series of unit processes, such as a strip of metal, is performed to pattern the first metal layer (not shown), thereby forming a plurality of gate lines 105 extending in a first direction, and simultaneously A gate electrode 108 connected to the gate line (not shown) is formed in the device region TrA.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 105 and the gate electrode 108 to form a gate insulating film 115 on the entire surface of the substrate 101. .

Next, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed on the gate insulating layer 115, and a second metal material such as aluminum (not shown) is formed on the impurity amorphous silicon layer (not shown). A second metal layer (not shown) is formed by depositing one of Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy. Subsequently, first and second photoresist patterns (not shown) having different thicknesses are formed by forming a photoresist layer (not shown) on the second metal layer (not shown), and performing and developing halftone or diffraction exposure. To form.

Next, the gate wiring line may be formed by etching and removing the second metal layer (not shown) and impurities and lower pure silicon layers (not shown) exposed to the outside of the first and second photoresist patterns (not shown). And a plurality of data wires 130 defining a plurality of pixel areas P extending in a second direction and intersecting in the second direction, and simultaneously connected to the data wires 130 in the device area TrA. A source drain pattern (not shown) and an ohmic contact pattern (not shown) sequentially stacked below the active layer 120a are formed.

 Next, the second photoresist pattern (not shown) having a thin thickness is removed, whereby the ohmic contact pattern (not shown) positioned below and in the center of the newly exposed source drain pattern (not shown) is removed. Etching and removal remove the source and drain electrodes 133 and 136 from each other, and form an ohmic contact layer 120b exposing the active layer 120a below the source and drain electrodes 133 and 136. do. In this case, the active layer 120a and the ohmic contact layer 120b form a semiconductor layer 120, and the gate electrode 108, the gate insulating layer 115, and the semiconductor layer (sequentially stacked in the device region TrA). 120, the source and drain electrodes 133 and 136 spaced apart from each other form a thin film transistor Tr.

Meanwhile, in the first exemplary embodiment, the semiconductor layer 120, the data line 130, and the source and drain electrodes 133 and 136 are simultaneously formed through a single mask process, thereby lowering the data line 130. Although the first and second dummy patterns 121a and 121b made of the same material forming the semiconductor layer 120 are formed, the semiconductor layer 120, the data line 130, the source and drain electrodes ( 133 and 136 may be formed through different mask processes, and in this case, the first and second dummy patterns 121a and 121b made of a semiconductor material are not formed below the data line 130.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the substrate 101 on the gate insulating layer, and then patterned by a mask process. A pixel electrode 138 is formed in the pixel region P in direct contact with the drain electrode 136 of the thin film transistor Tr.

On the other hand, in the case of the second embodiment, no pixel electrode is formed on the gate insulating film in this step.

Next, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the thin film transistor Tr, the data line 130, and the pixel electrode 138. The first passivation layer 140 is formed by depositing the same.

On the other hand, in the modified example of the first embodiment, a mask process is performed on the first protective layer 240 (in FIG. 6) to pattern the pixel electrode (238 in FIG. 6) corresponding to the drain electrode (236 in FIG. 6). The first contact hole 241 of FIG. 6 is formed to be exposed, and in the second embodiment, the thin film transistor (Tr of FIG. 8) is formed by performing a mask process on the first protective layer 340 of FIG. A drain contact hole 342 of FIG. 8 is formed to expose the drain electrode 336 of FIG. 8.

In the first embodiment, the first protective layer 140 is maintained without being patterned and deposited on the entire surface.

Next, when a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the first passivation layer 140, and the pixel electrode 138 is formed thereon. By performing the mask process using the used exposure mask as it is and patterning, the etch stopper 145 having the same planar shape as that of the pixel electrode 138 and overlapping the island is formed.

In this case, in the modified example of the first embodiment, the etch stopper 245 of FIG. 6 comes into contact with the pixel electrode 238 of FIG. 6 through the first contact hole 241 of FIG. 6.

On the other hand, in the case of the second embodiment, each pixel region (P in FIG. 8) on the first protective layer (340 in FIG. 8) in the same manner as the etch stopper (245 in FIG. 6) of the first embodiment by the above-described process. A pixel electrode 346 of FIG. 8 is formed within the pixel electrode 346 of FIG. 8. The pixel electrode 346 of FIG. 8 forms the drain contact hole 342 of FIG. 8 in the first passivation layer 340 of FIG. 8. The drain electrode (336 of FIG. 8) of the thin film transistor (Tr of FIG. 8) is brought into contact with each other.

Next, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the etch stopper 345 (the pixel electrode in the second embodiment) to have a second thickness of about 3000 to 4000 Å. The second protective layer 350 is formed.

Thereafter, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the second protective layer 350 to form a transparent conductive material layer (not shown). Thereafter, the transparent conductive material layer (not shown) is patterned by forming a mask process to form a plurality of first openings op1 having a bar shape spaced apart from each other by a predetermined interval corresponding to each pixel region P. A second opening op2 is formed to expose the thin film transistor Tr, including a spaced area between the source and drain electrodes 133 and 136 to correspond to the device region TrA. In this case, the second protective layer 250 is exposed to correspond to the plurality of first openings op1 and the second openings op2.

Next, a dry type using a reaction gas having a characteristic of reacting with and removing an inorganic insulating material with respect to the substrate 101 on which the common electrode 160 having the plurality of first openings op1 and the second openings op2 is formed. By etching to remove the second protective layer 160 exposed through the plurality of first openings (op1) to form a groove to expose the etch stopper 145 (pixel electrode in the second embodiment) The array substrate 101 for a fringe-filled switching mode liquid crystal display device according to the first embodiment is completed. In this case, the second passivation layer 150 exposed through the second opening op2 is also removed to expose the first passivation layer 140, but the portion of the device region Tr that forms the fringe field may be formed. Since the first protective layer 140 is not completely removed and a part of thickness is reduced, this is not a problem.

Meanwhile, the present invention is not limited to the above-described embodiments and modifications, and various changes and modifications are possible without departing from the spirit of the present invention.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views showing operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

3 is a cross-sectional view of one pixel area of an array substrate of a conventional fringe field switched mode liquid crystal display device.

4 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention;

FIG. 5 is a cross-sectional view of a portion cut along the cutting line VV of FIG. 4. FIG.

FIG. 6 is a cross-sectional view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display device according to a modification of the first embodiment of the present invention; FIG.

7 is a transmittance characteristic curve according to a change in driving voltage.

8 is a cross-sectional view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display device according to a second embodiment of the present invention.

<Brief description of the main parts of the drawing>

101: array substrate 108: gate electrode

115: gate insulating film 120: semiconductor layer

120a: active layer 120b: ohmic contact layer

130: data wiring 133: source electrode

136: drain electrode 138: pixel electrode

140: first protective layer 145: etch stopper

150: second protective layer 160: common electrode

op1, op2: first and second openings P: pixel area

Tr: Thin Film Transistor TrA: Device Area

Claims (9)

A gate wiring formed extending in one direction on the transparent substrate; A gate insulating film formed over the gate wiring; A data line over the gate insulating layer, the data line crossing the gate line and defining a pixel area; A thin film transistor electrically connected to the gate line and the data line and formed near an intersection point of the two lines; A pixel electrode on the gate insulating layer and in contact with the drain electrode of the thin film transistor and formed in the pixel region; A first passivation layer formed on the entire surface of the substrate over the pixel electrode and having a first thickness; An etch stopper formed in each pixel area over the first passivation layer; A second protective layer having a second thickness on the entire surface of the substrate above the etch stopper; The common electrode formed with a plurality of first openings having a bar shape spaced apart from each other in the pixel area over the second passivation layer. And the second passivation layer is formed with a groove for exposing the etch stopper corresponding to the plurality of first openings. The method of claim 1, The first passivation layer includes a first contact hole exposing the pixel electrode, and the etch stopper contacts the pixel electrode through the first contact hole. . A gate wiring formed extending in one direction on the transparent substrate; A gate insulating film formed over the gate wiring; A data line over the gate insulating layer, the data line crossing the gate line and defining a pixel area; A thin film transistor electrically connected to the gate line and the data line and formed near an intersection point of the two lines; A first protective layer having a first thickness on the entire surface of the substrate over the thin film transistor; A pixel electrode formed in contact with the drain electrode of the thin film transistor on each pixel area over the first passivation layer; A second protective layer formed on the entire surface of the substrate over the pixel electrode and having a second thickness; The common electrode formed with a plurality of first openings having a bar shape spaced apart from each other in the pixel area over the second passivation layer. And the second passivation layer is formed with a groove for exposing the etch stopper corresponding to the plurality of first openings. The method of claim 1, The first protective layer includes a drain contact hole exposing the drain electrode of the thin film transistor, wherein the pixel electrode is in contact with the pixel electrode through the drain contact hole, array for a fringe field switching mode liquid crystal display device Board. 4. The method according to any one of claims 1 to 3, The first thickness is 3000 kPa to 4000 kPa, The second thickness is 2000 kPa to 3000 kPa, And a sum of the first and second thicknesses is 6000 Å or more. The method of claim 5, And the first and second protective layers are formed of an inorganic insulating material, silicon oxide (SiO ₂ ) or silicon nitride (SiNx). 4. The method according to any one of claims 1 to 3, And a second opening formed in the common electrode corresponding to the thin film transistor. 4. The method according to any one of claims 1 to 3, And the pixel electrode is formed of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material. The method according to claim 1 or 2, The etch stopper is made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, and has the same planar shape as that of the pixel electrode. Array substrate.

Images