JP5458486B2 - Array substrate, display device, and manufacturing method thereof - Google Patents

Description

  The present invention relates to an array substrate on which a plurality of thin film patterns are formed, a display device, and a manufacturing method thereof. For example, it can be suitably used for a liquid crystal display device.

  In recent years, liquid crystal display devices are thin, lightweight, and have low power consumption and are used as typical display devices. As a method for reducing the manufacturing cost of the liquid crystal display device, it is effective to reduce the photolithography process in the manufacturing process of the array substrate on which the thin film transistor (hereinafter, TFT) is formed. Therefore, in a single photoengraving process, the region of the resist film thickness that is not exposed, the region that is completely exposed to remove the resist, and the region of the intermediate resist film thickness that is an intermediate exposure amount that does not completely expose the resist. There is a method called gray tone (hereinafter referred to as GT) exposure or half tone (hereinafter referred to as HT) exposure. In GT exposure, an intermediate exposure amount is given by arranging a thin thin film pattern below the resolution limit of an exposure apparatus on a photomask. In HT exposure, a semi-transmissive film is formed on a photomask to give an intermediate exposure amount. In particular, as described in Japanese Patent Laid-Open No. 2004-260, a method for reducing the photolithography process by performing GT exposure or HT exposure on the channel portion of the channel etch TFT has been put into practical use.

  In addition, as described in JP-A No. 2004-228688, in a single photoengraving process, an intermediate resist film thickness is obtained by performing a two-step exposure in which a second exposure having an intermediate exposure amount is added to the first exposure. There is also a method of obtaining the area. In Japanese Patent Laid-Open Publication No. 2003-259542, the drain electrode is made of a multilayer film containing Al as an upper layer, and the drain corresponding to the contact hole portion is used to suppress contact resistance between the pixel electrode made of a conductive oxide film such as ITO and the drain electrode. It has been shown that two-step exposure or HT exposure is used in the area where Al is removed from the upper layer of the electrode.

JP 2000-66240 A (FIGS. 25 to 30) Japanese Patent Laying-Open No. 2006-41161 (FIG. 4)

  In the photoengraving process, when intermediate exposure that does not completely expose the resist is performed, the effects of photomask accuracy (transmission variation), exposure device illuminance distribution, resist coating resist film thickness distribution, development variation, etc. The intermediate resist film thickness is likely to vary. However, as in Patent Document 1, if it is applied only to the channel portion of the TFT, since one kind of thin film pattern has the same film configuration, the variation in the thickness of the intermediate resist is not so much of a problem. . However, in addition to the contact portion of the drain electrode shown in Patent Document 2, intermediate exposure is also performed in the same photoengraving process on contact portions with wiring, terminals or electrodes having various other thin film patterns. In this case, various thin film patterns formed on the substrate have different heights from the substrate depending on the underlying film configuration. As a result, since the resist film thickness was not uniform, the variation of the intermediate resist film thickness after photolithography was further increased. As a result, in the region where the intermediate resist film thickness is thin, the thin film pattern required in the subsequent etching process disappears. Conversely, in the region where the intermediate resist film thickness is thick, an unnecessary thin film pattern remains as the remaining film in the subsequent process. There was a problem.

  The present invention has been made to solve the above-described problems, and in particular, in the case where intermediate exposure is performed in the same photolithography process in a region where a plurality of types of thin film patterns are formed, photolithography is performed. To provide a low-cost array substrate, a display device, and a method for manufacturing the same by reducing variations in the thickness of the intermediate resist film later, increasing the margin of the process for forming and processing the intermediate resist film thickness, and increasing the yield. For the purpose.

The array substrate of the present invention includes a substrate, a first conductive film on the substrate, an insulating film formed on the first conductive film, and a second conductive film formed on the insulating film. The second conductive film has a plurality of types of thin film patterns that are processed by forming an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist, These multiple types of thin film patterns are configured so that the height from the substrate is almost the same, and the heights of the multiple types of thin film patterns are almost the same in almost the entire region below the multiple types of thin film patterns. The first conductive film is configured to include the thin film pattern .

The manufacturing method of the array substrate of the present invention includes
Forming a first conductive film on the substrate;
Forming an insulating film on the upper layer of the first conductive film;
Forming a second conductive film on the insulating film;
Forming a plurality of types of thin film patterns by patterning the second conductive film ;
A method of manufacturing an array substrate comprising :
The process of forming multiple types of thin film patterns
Forming a resist;
A step of forming an intermediate resist film thickness and processing with an intermediate exposure amount that does not completely expose the resist ,
The step of forming the first conductive film includes:
Almost the entire area of the lower layer of the plurality of types of thin film pattern, so that the height of the plurality of types of thin film pattern is substantially the same, as engineering of forming a thin film pattern
It contains.

  According to the present invention, since the resist film thickness can be made substantially uniform in a plurality of types of regions to be processed by forming the intermediate resist film thickness, the intermediate resist film thickness after photoengraving can be made uniform, and the subsequent processes can be performed. The margin can be increased, the yield can be improved, and an inexpensive array substrate, display device, and manufacturing method thereof can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking an array substrate of a liquid crystal display device as an example. Note that in all the drawings for explaining the following embodiments, the same reference numerals denote the same or corresponding parts, and redundant explanations are omitted in principle.

Embodiment 1 FIG.
FIG. 1 is a plan view showing an array substrate of the liquid crystal display device in the first embodiment. FIG. 2 is a plan view showing the pixel of FIG. 3 is a cross-sectional view taken along the line AA in FIG. FIG. 4 is a plan view showing an enlarged portion of the source terminal of FIG. 5 is a cross-sectional view taken along the line BB in FIG. FIG. 6 is a plan view showing an enlarged portion of the common wiring conversion portion of FIG. 7 is a cross-sectional view taken along the line CC of FIG.

  In FIG. 1, an array substrate 100 constituting a main part of the liquid crystal display device includes a display unit 50 including a plurality of pixels 40 arranged in a matrix on a substrate 1 such as glass, and the periphery of the display unit 50. In the part, a gate terminal 60, a source terminal 62, and a common connection terminal 64 are formed. Further, the common wiring 3 constituting the storage capacitor of the pixel 40 is drawn out by the common connection wiring 46 through the common wiring conversion unit 44 and connected to the common connection terminal 64.

  Although not shown, the array substrate 100 is bonded to a counter substrate, liquid crystal is sealed between them, and display is performed by applying a voltage to the liquid crystal. Although not shown, the array substrate 100 and the counter substrate are attached with polarizing plates, and a backlight is disposed on the back surface of the array substrate 100 to form a liquid crystal display device.

  Next, in FIGS. 2 and 3, the pixel 40 includes a gate line 2, a common line 3, a source line 6, a TFT, a pixel electrode 11, and the like. A gate wiring 2 and a common wiring 3 which are a first conductive film and are made of Al, Mo, Cr, Ti, Ta, Mo, W, or the like are formed in parallel with a space therebetween. A gate insulating film 4 made of a SiN film, a SiO2 film, or the like is formed on the entire upper layer. A source wiring 6 is formed in a direction orthogonal to the gate wiring 2, and a semiconductor film 5 constituting a TFT is formed in the vicinity of the intersection. The semiconductor film 5 is a multilayer film in which a semiconductor film 5b doped with impurities is stacked on a semiconductor film 5a to be a channel. Here, the semiconductor film 5 is continuously arranged along the shape of the source wiring 6 in the lower layer of the source wiring 6, but it is not always necessary to arrange the semiconductor film 5 under the source wiring 6.

  A source electrode 7 extends from the source line 6 on the gate line 2 in the direction of the gate line 2 and overlaps the semiconductor film 5. Similarly, the drain electrode 8 partially overlaps the semiconductor film 5 and extends in a direction perpendicular to the gate wiring 2. The source wiring 6, the source electrode 7, and the drain electrode 8 are formed of a lower layer film 6a, 7a, 8a made of Cr, Ti, Ta, Mo, W or the like and an upper layer film 6b, 7b, 8b made of a metal film such as Al. The second conductive film is formed of a multilayer film.

  Between the source electrode 7 and the drain electrode 8, the semiconductor film 5 serving as a TFT channel is only the semiconductor film 5a, from which the semiconductor film 5b doped with impurities is removed.

  In the region H1 indicated by dots in FIG. 2, the upper layer film 8b of the drain electrode 8 is removed, and the lower layer film 8a is exposed. The interlayer insulating film 9 is formed so as to cover the entire pixel 40, and the contact hole 10 is formed so as to overlap the region H 1 of the drain electrode 8.

  The pixel electrode 11 made of a transparent conductive oxide film such as ITO is connected to the lower layer film 8a of the drain electrode 8 through the contact hole 10. Generally, the conductive oxide film ITO is easily oxidized with Al. Since the contact resistance is high, the upper layer film 8b in the vicinity of the contact hole 10 is removed to suppress the contact resistance. Here, the region H1 from which the contact hole 10 and the upper layer film 8b have been removed has a slightly shifted shape.

  In addition, the storage capacitor region CS where the common line 3 and the pixel electrode 11 overlap constitutes a storage capacitor that holds the liquid crystal applied voltage.

  Here, the hatched region in FIG. 2 was processed by forming an unexposed resist in the photolithography process for forming the source wiring 6, the source electrode 7, the drain electrode 8 and the like made of the second conductive film. It is a thin film pattern. A region H1 indicated by a dot is a thin film pattern formed by processing an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist. A thin film pattern 12 formed of the first conductive film which is the same layer as the gate wiring 2 and the common wiring 3 is formed on almost the entire lower layer of the region H1.

  Next, the details of the source terminal 62 in FIG. 1 will be described. As shown in FIGS. 4 and 5, the source terminal 62 includes a source terminal film 13 formed of a second conductive film that is the same layer as the source wiring 6, the source electrode 7, the drain electrode 8, and the like. . The source terminal film 13 is composed of a multilayer film of a lower layer film 13a made of Cr, Ti, Ta, Mo, W or the like and an upper layer film 13b made of a metal film such as Al.

  In order to improve the corrosion resistance of the source terminal 62, the surface of the terminal is covered with the surface terminal film 16 made of the same conductive oxide film such as ITO as the pixel electrode 11. Here, the contact hole 14 provided in the interlayer insulating film 9 is connected to the lower layer film 13a in the region H2 where the upper layer film 13b of the source terminal film 13 is removed.

  The source terminal film 13 is formed in the same process as the source wiring 6, the source electrode 7, the drain electrode 8, and the like. The hatched area in FIG. 4 is a thin film pattern formed by processing a resist that is not exposed in the photolithography process for forming the source terminal film 13. A region H2 indicated by a dot is a thin film pattern formed by processing an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist. In the region H2, the upper layer film 13b of the source terminal film 13 is removed. A thin film pattern 15 formed of a first conductive film that is the same layer as the gate wiring 2 and the common wiring 3 is formed in the lower layer of the region H2 so as to have the same height as the region H1.

  Next, details of the common wiring conversion unit 44 of FIG. 1 will be described. As shown in FIGS. 6 and 7, the common wiring 3 constituting the storage capacitor region CS of the pixel 40 is connected to the common connection wiring 46 orthogonal to the common wiring 3 outside the display unit 50. Connected through. A common connection terminal 64 is formed at one end of the common connection wiring 46. The common connection wiring 46 is composed of a multilayer film of a lower layer film 46a made of Cr, Ti, Ta, Mo, W or the like and an upper layer film 46b made of a metal film such as Al, and is formed of a second conductive film. The common connection terminal 64 has the same layer structure as the source terminal 62.

  Here, the common wiring 3 and the common connection wiring 46 are connected through the contact holes 18 and 19 by the connection film 17 formed of the same conductive oxide film such as ITO as the pixel electrode 11. The contact hole 18 is a portion connected to the common wiring 3 by removing the gate insulating film 4 and the interlayer insulating film 9, and the contact hole 19 is a portion connected to the common connecting wiring 46 by removing the interlayer insulating film 9.

  Here, the common connection wiring 46 is formed in the same process as the source wiring 6, the source electrode 7, the drain electrode 8, the source terminal film 13, and the like. 6 is a thin film pattern formed by processing a resist that is not exposed in the photolithography process for forming the common connection wiring 46. In FIG. A region H3 indicated by a dot is a thin film pattern that has been processed by forming an intermediate resist film thickness. In the region H3, the upper layer film 46b of the common connection wiring 46 is removed, and the common wiring 3 is formed below the region H3 so as to overlap the common connection wiring 46. The configuration in which the common wiring 3 is disposed below the common connection wiring 46 and the common wiring conversion unit 44 is a configuration that has been implemented in the past in order to reduce the resistance of the common connection wiring 46.

  As a result, the thin film patterns 12 and 15 formed from the first conductive film or the common wiring 3 are formed in almost all the lower layers of the regions H1, H2 and H3 processed by forming the intermediate resist film thickness. Therefore, the heights of the drain electrode 8, the source terminal film 13, and the common connection wiring 46 formed from the second conductive film from the substrate 1 are substantially the same.

  1 also, the gate wiring 2 is converted to a gate terminal film formed from the second conductive film and connected to the gate terminal 60, and the first conductive film is formed below the gate terminal 60. By forming the thin film pattern to be formed, the same layer configuration as that of the source terminal 62 can be obtained.

  Next, the effect of making the plurality of types of thin film patterns processed by forming the intermediate resist film thickness substantially the same height from the substrate will be described. FIG. 8 is a cross-sectional view showing a process of processing a plurality of types of thin film patterns by forming an intermediate resist film thickness.

  FIG. 8A shows an exposure process of the photolithography process. It is assumed that the thin film 22 formed on the substrate 1 has regions Ha, Hb, Hc, and Hd that are processed by forming an intermediate resist film thickness. Under the regions Ha and Hb, thin film patterns 20a and 20b having the same film thickness are formed so that the thin film 22 has substantially the same height from the substrate 1. On the other hand, a thin film pattern 20c thicker than the thin film patterns 20a and 20b is formed below the region Hc. Such a thin film pattern is not formed below the region Hd.

  An insulating film 21 and a thin film 22 processed with an intermediate resist film thickness are formed over the entire surface. The thin film 22 is composed of a two-layer film of a lower layer film 22a and an upper layer film 22b. In order to pattern the thin film 22, a resist 30 is applied by spin coating or the like. After the application of the resist 30, the surface of the resist 30 becomes substantially flat, so that the resist film thicknesses Sa, Sb, Sc, Sd in the regions Ha, Hb, Hc, Hd are different. That is, the resist thicknesses Sa and Sb of the regions Ha and Hb are equal, but the resist thickness Sc of the region Hc is thinner than the resist thicknesses Sa and Sb, and the resist thickness Sd is thicker than the resist thicknesses Sa and Sb. .

  The GT mask 200 used in this photolithography process has minute slits 210 corresponding to the areas Ha, Hb, Hc and Hd where GT exposure is performed. The resist 30 is exposed through the GT mask 200.

  FIG. 8B is a step of developing the exposed resist 30 to form a resist pattern. In regions Ha, Hb, Hc, and Hd that have been subjected to GT exposure using the GT mask 200, the intermediate resist film thicknesses Ta, Tb, Tc, and Td of the intermediate resists 30a, 30b, 30c, and 30d are different. . That is, the intermediate resist film thicknesses Ta and Tb in the regions Ha and Hb are equal, but the resist film thickness Tc in the region Hc is thinner than the resist film thicknesses Ta and Tb, and the resist film thickness Td is thicker than the resist film thicknesses Ta and Tb. Become.

  FIG. 8C shows an etching process in which both the lower layer film 22a and the upper layer film 22b of the thin film 22 are removed by wet etching or dry etching using the resist pattern formed in FIG. 8B.

  FIG. 8D is a process of ashing with oxygen plasma or the like to remove the intermediate resists 30a, 30b, 30c, and 30d remaining in the etching process of FIG. 8C. Here, assuming that the optimum ashing processing time for removing the intermediate resists 30a and 30b in the regions Ha and Hb, not only the intermediate resist 30c but also all the resists 30 around the region Hc disappear in the region Hc. In the region Hd, the intermediate resist 30d still remains.

  FIG. 8E shows a step of removing the resist by removing the upper layer film 22b of the regions Ha, Hb, Hc, and Hd by selective etching. As a result, a normal thin film pattern in which the upper layer film 22b is removed is formed in the regions Ha and Hb, but the region Hc is a defective thin film pattern in which the upper layer film 22b around the region Hc to be originally left is also removed. Become. The region Hd becomes a defective thin film pattern in which the upper layer film 22b to be removed remains. That is, if the intermediate resist film thicknesses Tc and Td are significantly different from the intermediate resist film thicknesses Ta and Tb, even if the ashing processing time of the intermediate resists 30a, 30b, 30c, and 30d is adjusted, the region Hc or the region Hd Since either one is defective, there is no process margin.

  As described above, in the first embodiment, in the drain electrode 8, the source terminal 62, and the common wiring conversion unit 44 formed of the second conductive film, the intermediate resist film is subjected to an intermediate exposure amount that does not completely expose the resist. The thin film patterns 12 and 15 formed of the first conductive film which is the same layer as the gate wiring 2 and the common wiring 3 or the common in almost all the lower layers of the regions H1, H2 and H3 to be processed with the thickness formed Since the wiring 3 is formed and the height from the substrate 1 is substantially the same, the intermediate resist film thickness of the resist 30 can be made uniform. Further, since the process margin can be increased in the ashing processing time of the intermediate resist and the like, defective thin film patterns are reduced, and the yield can be improved.

Embodiment 2. FIG.
In the first embodiment, the first conductive film is formed in almost all regions below the regions H1, H2, and H3 to be processed by forming an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist. Although the formed thin film patterns 12 and 15 or the common wiring 3 are formed, conversely, in the second embodiment, as shown in FIGS. 9 to 14 with respect to FIGS. 2 to 7 of the first embodiment. The height from the substrate 1 can be made substantially the same by forming a flat structure in which the thin film pattern formed of the first conductive film is not formed in almost all regions below the regions H1, H2, and H3. it can.

  In this case, as shown in FIG. 9 to FIG. 12, the thin film pattern formed of the first conductive film is formed in almost all the lower layers of the regions H1 and H2 of the drain electrode 8 and the source terminal 62 of the first embodiment. 12 and 15 are not arranged. As shown in FIGS. 13 and 14, in the common wiring conversion unit 44, a removal unit 48 is provided in the common wiring 3 in almost the entire region below the region H <b> 3 of the common connection wiring 46. The part is removed. As described above, even in a flat configuration in which the thin film patterns 12 and 15 formed of the first conductive film and the common wiring 3 are not formed in almost all regions below the regions H1, H2, and H3, the intermediate resist film thickness is reduced. Uniformity can be achieved. Further, since the process margin can be increased, the number of defective thin film patterns can be reduced and the yield can be improved.

Embodiment 3 FIG.
In the first embodiment, the first conductive film is formed in almost all regions below the regions H1, H2, and H3 to be processed by forming an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist. Although the formed thin film patterns 12 and 15 or the common wiring 3 are formed, even if a thin film pattern formed of the same layer as the semiconductor film 5 is formed instead of the first conductive film, the thin film patterns are aligned at substantially the same height. be able to. Alternatively, if the gate wiring 2 and the semiconductor film 5 have substantially the same film thickness, the height from the substrate 1 can be made substantially the same even when a thin film pattern in which the first conductive film and the semiconductor film 5 are mixed is disposed. The intermediate resist film thickness can be made uniform. Further, since the process margin can be increased, the number of defective thin film patterns can be reduced and the yield can be improved.

Embodiment 4 FIG.
In the first to third embodiments, the three regions H1, H2, and H3 have been described, but the present invention can be applied to other locations. 15 is a plan view showing an enlarged portion of the electrostatic protection circuit according to the fourth embodiment, and FIG. 16 is a cross-sectional view taken along line DD and EE in FIG. The reference numerals in parentheses in FIG. 16 are those taken along the line E-E, and both the cross-sectional structures are basically the same. The fourth embodiment shows an electrostatic protection circuit for the gate wiring 2 provided outside the display portion. The static electricity protection circuit for the gate wiring 2 is a short-circuit wiring 66 made of a second conductive film when static charges such as static electricity are applied to the gate wiring 2 at a high voltage of several tens of volts or more. This is a circuit composed of two diodes having different rectification directions for dispersion into the two. The diode can be formed in the same process as the pixel TFT. A diode can be formed by connecting the gate electrodes 71 and 72 made of the first conductive film to one of the source electrode 7 and the drain electrode 8 made of the second conductive film.

  Regions H4 and H5 indicated by dots in FIG. 15 are thin film patterns formed by processing an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist. In the region H4, the upper layer film 7b of the source electrode 7 is removed, and the lower layer film 7a is exposed. In the region H5, the upper layer film 8b of the drain electrode 8 is removed, and the lower layer film 8a is exposed. As shown in FIG. 16, thin film patterns 74 and 75 formed of the first conductive film are formed in almost all regions below the regions H4 and H5, which are the same as the regions H1, H2, and H3 in the first embodiment. It is height. Then, the gate electrodes 71 and 72 made of the first conductive film, the source electrode 7 made of the second conductive film, and the lower layer films 7a and 8a of the drain electrode 8 are made of the same conductive oxide such as ITO as the pixel electrode 11. They are connected by connection films 81 and 82 formed of films.

  Although the electrostatic protection circuit for the gate wiring 2 has been described here, the electrostatic protection circuit for the source wiring 6 can also have the same configuration. That is, outside the display portion, the source line 6 has a shape corresponding to the short-circuit line 66 in FIG. 15, and the short-circuit line 66 is made of the first conductive film and has a shape corresponding to the gate line 2 in FIG. It only has to have.

Embodiment 5 FIG.
As an application place other than the above, the gate wiring 2 formed from the first conductive film is connected to the second conductive so that the gate terminal 60 has the same structure and the same height as the source terminal 62. It can be applied to a connection portion that is converted to a gate terminal film formed from a film and connected to the gate terminal 60. Alternatively, the source wiring 6 formed from the second conductive film is formed from the first conductive film outside the display portion so that the source terminal 62 has the same structure and the same height as the gate terminal 60. The present invention can be applied to a connection portion that is converted into a source terminal film and connected to the source terminal 62. Thus, in the connection portion for connecting the first conductive film and the second conductive film, the intermediate resist film thickness is formed and processed by the intermediate exposure amount that does not completely expose the resist. The cross-sectional structure may be the same height as the region H3 of the common wiring conversion portion 44 and the regions H4 and H5 of the electrostatic protection circuit that have the same connection structure.

  In the above embodiments, the array substrate of the liquid crystal display device has been described. However, the present invention is also applied to an array substrate of a display device such as an electroluminescence (EL) display device, an electrochromic display device, and electronic paper using fine particles or oil droplets. The invention is applicable.

4 is a plan view showing an array substrate of the liquid crystal display device in Embodiment 1. FIG. FIG. 2 is a plan view illustrating a pixel of the display unit in FIG. 1 according to Embodiment 1. FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2 in the first embodiment. FIG. 3 is a plan view showing an enlarged part of the source terminal of FIG. 1 in the first embodiment. FIG. 3 is a cross-sectional view taken along the line BB in FIG. 2 in the first embodiment. FIG. 3 is a plan view showing an enlarged portion of the common wiring conversion portion of FIG. 1 in the first embodiment. FIG. 7 is a cross-sectional view taken along the line CC of FIG. 6 in the first embodiment. It is sectional drawing which shows the process of forming multiple types of thin film patterns, forming an intermediate resist film thickness. FIG. 10 is a plan view illustrating a pixel of a display portion in Embodiment 2. FIG. 10 is a cross-sectional view taken along the line AA in FIG. 9 in the second embodiment. 6 is a plan view showing an enlarged part of a source terminal in Embodiment 2. FIG. FIG. 12 is a cross-sectional view taken along the line BB in FIG. 11 in the second embodiment. FIG. 10 is a plan view showing an enlarged part of a common wiring conversion unit in the second embodiment. FIG. 14 is a cross-sectional view taken along the line CC of FIG. 13 in the second embodiment. FIG. 10 is a plan view showing an enlarged part of an electrostatic protection circuit in a fourth embodiment. FIG. 16 is a cross-sectional view taken along the line DD and EE of FIG. 15 in the fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate wiring 3 Common wiring 4 Gate insulating film 5 Semiconductor film 6 Source wiring 8 Drain electrode 9 Interlayer insulating film 10 Contact hole 11 Pixel electrode 12 Thin film pattern 13 Source terminal film 15 Thin film pattern 17 Connection film 20 Thin film 30 Resist 30a, 30b, 30c, 30d Intermediate resist 44 Common wiring conversion section 46 Common connection wiring 48 Removal section 60 Gate terminal 62 Source terminal 64 Common connection terminal 66 Short circuit wiring 71, 72 Gate electrodes 74, 75 Thin film pattern 81, 82 Connection film 100 Array substrate 200 GT masks H1, H2, H3, H4, H5, Ha, Hb, Hc, Hd Regions Sa, Sb, Sc, Sd processed by forming an intermediate resist film thickness Resist film thicknesses Ta, Tb, Tc, Td Intermediate Resist film thickness

Claims (5)

A substrate,
A first conductive film formed on the substrate;
An insulating film formed on an upper layer of the first conductive film;
An array substrate comprising a second conductive film formed on an upper layer of the insulating film,
The second conductive film includes a plurality of types of thin film patterns processed by forming an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist,
The plurality of types of thin film patterns are configured to have substantially the same height from the substrate ,
A thin film pattern formed so that the height of the plurality of types of thin film patterns is substantially the same in almost the entire lower layer of the plurality of types of thin film patterns,
The first conductive film is array substrate including the thin film pattern. The array substrate according to claim 1, wherein the first conductive film is the same layer as the gate wiring. The array substrate according to claim 1, wherein the second conductive film is the same layer as the drain electrode. A substrate,
A first conductive film;
An insulating film formed on an upper layer of the first conductive film;
An array substrate comprising a second conductive film formed on an upper layer of the insulating film,
The second conductive film includes a plurality of types of thin film patterns processed by forming an intermediate resist film thickness with an intermediate exposure amount that does not completely expose the resist,
The plurality of types of thin film patterns are configured to have substantially the same height from the substrate ,
A thin film pattern formed so that the height of the plurality of types of thin film patterns is substantially the same in almost the entire lower layer of the plurality of types of thin film patterns,
The first conductive film is a display device using the array substrate including the thin film pattern. Forming a first conductive film on the substrate;
Forming an insulating film on an upper layer of the first conductive film;
Forming a second conductive film on the insulating film;
Patterning the second conductive film to form a plurality of types of thin film patterns ;
A method of manufacturing an array substrate comprising :
The step of forming the plurality of types of thin film patterns includes:
Forming a resist;
The intermediate exposure not completely exposing the resist, a step of processing to form an intermediate resist film thickness,
With
The step of forming the first conductive film includes:
Almost the entire area of the lower layer of the plurality of types of thin film pattern, wherein as the height of a plurality of kinds of thin film pattern is substantially the same, as engineering of forming a thin film pattern
An array substrate manufacturing method comprising:

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