JP2010049288A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-domain vertical alignment liquid crystal display which has a wide view angle by dropping a liquid crystal. <P>SOLUTION: The liquid crystal display includes: a sealing material for holding the liquid crystal dropped between a first substrate and a second substrate; a pixel part which is surrounded by the sealing material and arranged on the first substrate; an IC chip which is arranged on the first substrate on the outside of the sealing material in an area where the IC chip is not superposed on the second substrate; an anisotropic conductive film which is arranged on the first substrate on the outside of the sealing material in an area where the anisotropic conductive film is not superposed on the second substrate and which electrically connects the pixel part to the IC chip; and a wire which is extended from the pixel part to an anisotropic conductive film-arranged area so that the wire and the sealing material are made to cross each other and which electrically connects the pixel part arranged on the first substrate to the IC chip. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a liquid crystal display device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.

In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

Conventionally, a liquid crystal display device is known as an image display device. Active matrix liquid crystal display devices are often used because high-definition images can be obtained compared to passive liquid crystal display devices. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is recognized by the observer as a display pattern.

Applications of such an active matrix electro-optical device are expanding, and the demand for higher definition, higher aperture ratio, and higher reliability is increasing as the screen size increases. At the same time, demands for improved productivity and lower costs are increasing.

Conventionally, as an alignment mode of a liquid crystal layer used in a transmissive liquid crystal display device, a TN mode in which the alignment of liquid crystal molecules is twisted by 90 ° from the incident light to the outgoing direction is generally used. It was.

In manufacturing the TN mode liquid crystal display device, alignment film formation, rubbing treatment, or the like is performed on one substrate and the other substrate in order to determine the alignment direction of the liquid crystal. And it bonds so that the rubbing direction of a board | substrate may orthogonally cross. A liquid crystal display device that twists in a predetermined direction is formed by injecting a liquid crystal material mixed with a chiral material that determines the rotation direction of the twist between the pair of substrates.

At this time, the liquid crystal molecules are arranged so that the major axis is parallel to the substrate surface so as to have the most stable arrangement in terms of energy, and several degrees to 10 degrees with respect to the substrate surface depending on the rubbing conditions and the alignment film material. Arrange them at an angle of around.

This angle is referred to as a pretilt angle. By securing this angle, the alignment of the both ends of the long axis of the liquid crystal molecule is aligned at the both ends of the liquid crystal molecule when an electric field is applied.
As a result, the orientation during operation becomes continuous, and orientation defects such as a reverse tilt domain during display can be prevented.

However, in the TN mode, there are problems that the contrast characteristics are extremely deteriorated outside the specific viewing angle range, and the phenomenon that the gradation is inverted occurs.

This is because when the orientation state of the liquid crystal molecules is deformed by the electric field into an alignment that is perpendicular to the substrate surface, the distance of light traveling through the liquid crystal layer and the passage of light depending on the angle and orientation at which the observer views the liquid crystal display device This is because the refractive index inside changes, so that the light optically modulated differently is seen.

In this mode, the liquid crystal molecules near the substrate interface receive a strong alignment regulating force, and the initial alignment state is substantially maintained. For this reason, even if a considerably high liquid crystal saturation voltage (5 V or more) is applied, the liquid crystal molecules in the vicinity thereof are not vertical.

  These are considered to be factors that narrow the visual field characteristics of the TN mode.

As another liquid crystal display mode, a vertical alignment liquid crystal mode is known. This vertical alignment type liquid crystal mode is an alignment mode in which the initial alignment of the liquid crystal is perpendicular to the substrate. This mode uses an n-type liquid crystal material having negative dielectric anisotropy. In this mode as well, display is realized by applying an electric field between the electrodes provided on the substrate.

However, since this mode uses the birefringence of the liquid crystal, a slight variation in pretilt is conspicuous as a variation in the amount of transmitted light or the amount of reflected light. There is a problem that streak-like display unevenness is likely to occur due to a slight difference in how the hair tips contact during the rubbing process.

In addition, the rubbing process itself is a source of dust generation due to the process of rubbing the alignment film surface on the substrate with soft hair. Furthermore, it is necessary to take sufficient measures against stress and destruction of elements on the substrate due to generation of static electricity.

For this reason, a method for achieving uniform alignment and aligning liquid crystals without rubbing is generally sought. For example, by forming a structure on the substrate, adjusting the physical parameters such as the inclination, spacing, and height of the surface in contact with the liquid crystal of this structure, and further aligning the effect of the electric field due to the dielectric constant of the structure Means for controlling the above and manufacturing a liquid crystal display device are known. By this method, a wide viewing angle of 160 ° or more is realized. However, this method eliminates the need for the conventional rubbing process, but requires a complicated additional process for aligning the liquid crystal.

Conventionally, an active matrix type electro-optical device has been used for photolithography.
Due to the technology, TFTs were fabricated on a substrate using at least five photomasks, and the manufacturing cost was high. In order to improve productivity and improve yield, reducing the number of steps is considered as an effective means.

Specifically, it is necessary to reduce the number of photomasks required for manufacturing TFTs.
A photomask is used in photolithography to form a photoresist pattern as a mask for an etching process on a substrate.

By using one photomask, the steps such as resist coating, pre-baking, exposure, development, and post-baking, and the steps before and after that, such as film formation and etching, resist stripping, cleaning, and drying are performed. The process is added and becomes complicated,
It was a problem.

In addition, since the substrate is an insulator, static electricity is generated due to friction during the manufacturing process. When this static electricity is generated, a short circuit occurs at the intersection of the wirings provided on the substrate, or the TFT is deteriorated or destroyed by the static electricity, resulting in display defects or image quality deterioration in the electro-optical device. In particular, static electricity is generated during the rubbing process of the liquid crystal alignment process performed in the manufacturing process, which is a problem.

The present invention answers such a problem. The rubbing process is reduced to produce an electro-optical device typified by an active matrix liquid crystal display device, and the number of steps for producing TFTs is further reduced to reduce the manufacturing cost. It is an object to realize a reduction in yield and an improvement in yield.

  In addition, an object is to improve the visual field characteristics of the liquid crystal display device.

The configuration of the invention disclosed in this specification is a liquid crystal display device including a pair of substrates and a liquid crystal held between the pair of substrates, and one of the pair of substrates includes a gate wiring. When,
An insulating film on the gate wiring; an amorphous semiconductor film on the insulating film; a source region and a drain region on the amorphous semiconductor film; and a source wiring or an electrode on the source region or the drain region. A pixel electrode formed on the electrode, and a gap holding material for keeping a distance between the pair of substrates constant, and controlling the pretilt angle of the liquid crystal by a side surface of the gap holding material. Is a liquid crystal display device characterized by aligning.

According to another aspect of the invention, there is provided a liquid crystal display device including a pair of substrates and a liquid crystal held between the pair of substrates, wherein one substrate of the pair of substrates includes a gate wiring, An insulating film on the gate wiring; an amorphous semiconductor film on the insulating film; a source region and a drain region on the amorphous semiconductor film; and a source wiring or an electrode on the source region or the drain region. A pixel electrode formed on the electrode, and a gap holding material for keeping a distance between the pair of substrates constant, a side surface of the gap holding material, and a surface provided on at least one substrate The liquid crystal display device is characterized in that the liquid crystal is aligned by controlling a pretilt angle of the liquid crystal by a concave portion or a convex portion.

In each of the above structures, at least one of the substrates has an alignment film for vertical alignment.

In each of the above configurations, the gap retaining material has a certain taper angle.
The taper angle is 75.0 ° to 89.9 °, preferably 82 ° to 87 °. Also,
The gap retaining material is an organic resin material mainly composed of at least one of acrylic, polyimide, polyimide amide, and epoxy, or any one of silicon oxide, silicon nitride, and silicon oxynitride, or It is an inorganic material made of these laminated films.

Further, in each of the above-described configurations, there is an alignment regulating force in the vicinity of the side surface of the gap retaining material so that the major axis direction of the liquid crystal molecules is substantially parallel to the side surface.

  In each of the above structures, the liquid crystal has negative dielectric anisotropy.

In each of the above configurations, one end face of the drain region or the source region is
It substantially coincides with the end face of the amorphous semiconductor film and the end face of the electrode.

In each of the above configurations, one end face of the drain region or the source region is
The end face of the amorphous semiconductor film and the end face of the electrode are substantially coincident with each other, and the other end face is substantially coincident with the end face of the pixel electrode and the other end face of the electrode.

In each of the above structures, the source region and the drain region are formed of an amorphous semiconductor film containing an impurity element imparting n-type conductivity.
Liquid crystal display device.

In each of the above structures, the insulating film, the amorphous semiconductor film, the source region, and the drain region are formed continuously without being exposed to the atmosphere.

In each of the above structures, the insulating film, the amorphous semiconductor film, the source region, or the drain region is formed by a sputtering method.

In each of the above structures, the insulating film, the amorphous semiconductor film, the source region, or the drain region is formed by a plasma CVD method.

In each of the above structures, the source region and the drain region are formed using the same mask as the amorphous semiconductor film and the electrode.

In each of the above structures, the source region and the drain region are formed using the same mask as the source wiring.

In each of the above structures, the source region and the drain region are formed using the same mask as the source wiring and the pixel electrode.

In each of the above structures, the pixel electrode is in contact with the insulating film.

In each of the above structures, in the amorphous semiconductor film, a film thickness in a region in contact with the source region and the drain region is a film in a region between a region in contact with the source region and a region in contact with the drain region. It is characterized by being thicker than the thickness, and functions as an active layer of a channel etch type TFT.

In each of the above structures, a region between the region in contact with the source region and the region in contact with the drain region of the amorphous semiconductor film is covered and protected by the gap holding material made of an inorganic insulating film. It is characterized by that.

Further, the configuration of the invention for realizing the above structure includes a first step of forming a gate wiring on a first substrate with a first mask, a second step of forming an insulating film covering the gate wiring, A third step of forming a first amorphous semiconductor film over the insulating film; and a second step of forming a second semiconductor film containing an impurity element imparting n-type over the first amorphous semiconductor film. 4 steps and the second
A fifth step of forming a first conductive film on the amorphous semiconductor film, patterning the first amorphous semiconductor film with a second mask, and the second non-mask with the second mask. A sixth step of patterning the crystalline semiconductor film and patterning the first conductive film with the second mask to form a wiring made of the first conductive film; and a second step overlapping with the wiring. A seventh step of forming a conductive film; patterning the second conductive film with a third mask; forming a pixel electrode made of the second conductive film; and patterning the wiring with the third mask. Forming a source wiring and an electrode, patterning the second amorphous semiconductor film with the third mask to form a source region and a drain region made of the second amorphous semiconductor film, and 3 of the first amorphous semiconductor film with the mask 3 An eighth step of removing, a ninth step of forming an alignment film on the pixel electrode, a tenth step of forming a gap retaining material on the alignment film, the first substrate and the second substrate, And a twelfth step of injecting liquid crystal between the first substrate and the second substrate.

The said structure WHEREIN: The said gap holding material keeps the space | interval of a said 1st board | substrate and a said 2nd board | substrate constant, It is characterized by the above-mentioned.
A method for manufacturing a liquid crystal display device.

In the above configuration, the liquid crystal is aligned by controlling the pretilt angle of the liquid crystal by the side surface of the gap retaining material. The pretilt angle of the liquid crystal is controlled by the alignment film. The alignment film may be provided on one or both of the first substrate and the second substrate.

According to the present invention, a pixel TFT portion having an inverted staggered n-channel TFT and a storage capacitor are formed using three photomasks by three photolithography processes, and without further rubbing treatment. It is possible to realize a multi-domain vertical alignment type liquid crystal display device with a wide viewing angle display in which cell gaps are uniform and the switching direction of liquid crystal molecules is controlled by forming wall spacers by a single photolithography process. it can.

The figure which shows the sectional view of this invention, and the orientation state of a liquid crystal molecule. Sectional drawing which shows the manufacturing process of an active matrix substrate. Sectional drawing which shows the manufacturing process of an active matrix substrate. FIG. 6 is a top view illustrating a manufacturing process of an active matrix substrate. FIG. 6 is a top view illustrating a manufacturing process of an active matrix substrate. FIG. 6 is a top view illustrating a manufacturing process of an active matrix substrate. 4 is a top view illustrating an arrangement of a pixel portion and an input terminal portion of a liquid crystal display panel. Sectional drawing which shows the mounting structure of a liquid crystal display panel. The top view and sectional drawing of an input terminal part. The top view of a manufacturing apparatus. The top view of a manufacturing apparatus. The figure which shows mounting of a liquid crystal display panel. Sectional drawing which shows the mounting structure of a liquid crystal display panel. The figure which shows the sectional view of this invention, and the orientation state of a liquid crystal molecule. The figure which shows the sectional view of this invention, and the orientation state of a liquid crystal molecule. The figure which shows the sectional view of this invention, and the orientation state of a liquid crystal molecule. The figure which shows the perspective view of the wall-shaped spacer of this invention. The figure which shows the top view of the wall-shaped spacer of this invention. The top view and circuit diagram of a protection circuit. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device.

  Embodiments of the present invention will be described below.

In order to solve the above problems, the present invention employs a channel-etch type bottom gate TFT structure, and patterning of a source region and a drain region and patterning of a pixel electrode are performed using the same photomask.

  The production method of the present invention will be briefly described below.

  First, the gate wiring 102 is formed using a first mask (first photomask).

Next, the insulating film (gate insulating film) 104a, the first amorphous semiconductor film 105, the second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity, and the first conductive film 107 are sequentially formed. Laminate. (FIG. 2A) Note that a microcrystalline semiconductor film may be used instead of an amorphous semiconductor film, or an n-type semiconductor layer is provided instead of an amorphous semiconductor film containing an impurity element imparting n-type conductivity. A microcrystalline semiconductor film containing an impurity element may be used. Further, these films (104a, 105, 10
6, 107) can be formed in a plurality of chambers or in the same chamber without being continuously exposed to the atmosphere by using a sputtering method or a plasma CVD method. By not exposing to the atmosphere, contamination of impurities can be prevented.

Next, the first conductive film 107 is patterned with a second mask (second photomask) to form a wiring made of the first conductive film (to be a source wiring and an electrode (drain electrode) later) 1
11, the second amorphous semiconductor film 106 is patterned to form a second amorphous semiconductor film 110 containing an impurity element imparting n-type conductivity, and the first amorphous semiconductor film 105 is patterned to form a first amorphous semiconductor film 109. (Fig. 2 (B))

After that, a second conductive film 112 is formed over the entire surface. (FIG. 2D) The second conductive film 1
As 12, a transparent conductive film may be used, or a reflective conductive film may be used.

Next, the second conductive film 112 is patterned with a third mask (third photomask) to form a pixel electrode 119 made of the second conductive film, and the wiring is patterned to form the source wiring 117 and the electrode. (Drain electrode) 118 is formed, and the second amorphous semiconductor film 110 containing an impurity element imparting n-type is patterned to provide a second element containing an impurity element imparting n-type.
A source region 115 and a drain region 116 made of an amorphous semiconductor film are formed, and the first region is formed.
The first amorphous semiconductor film 114 is formed by removing a part of the amorphous semiconductor film 109. (Fig. 3
(A))

With such a structure, when the pixel TFT portion is manufactured, the number of photomasks used in the photolithography technique can be three.

Further, in the present invention, a liquid crystal display device is manufactured without increasing the number of steps and without performing a rubbing process.

In the present invention, as shown in FIG. 1, a gap holding material is provided to keep a constant distance between a pair of substrates (substrate 100 and counter substrate 124). Here, as the gap holding material, the wall spacers 121 and 122 have inclined side surfaces, the pretilt angle of the liquid crystal having negative dielectric anisotropy is controlled, and the liquid crystal is aligned.

In the present specification, the cross-sectional shape of the wall spacers 121 and 122 is, for example, FIG. 17A or FIG. In particular, as shown in FIG. 17A, the taper angle α is defined as an angle formed by a bottom surface and a side surface of a trapezoid that is a cross section thereof. In the present invention, the taper angle α is 75.0 ° to 8 °.
It is desirable that the angle is 9.9 °, preferably 82 ° to 87 °.

The alignment of the liquid crystal molecules in FIG. 1 shows a schematic diagram when no voltage is applied. Note that the blacked out portions indicate the end portions of the liquid crystal molecules close to the counter substrate.

When no voltage is applied, the liquid crystal molecules receive a regulating force from the side surface of the wall spacer, and are aligned substantially parallel to the side surface and have a certain pretilt angle, and are aligned perpendicular to the substrate surface. Oriented parallel to the substrate surface.

That is, by using the wall-like spacer having the side surface with the taper angle α, the switching direction of the liquid crystal molecules can be controlled.

The wall spacer is formed by a photolithography method or a printing method. Also,
An alignment film for vertical alignment is formed before or after the wall spacer is formed.

Further, the wall spacer may be provided only on the substrate 100 or the counter substrate 124.
You may provide only. The wall spacer may be provided on both the substrate 100 and the counter substrate 124. If priority is given to reducing the number of photomasks at the time of manufacturing the active matrix substrate, it is preferable to use a formation method by a printing method or to provide only on the counter substrate. When a liquid crystal display device provided with a wall spacer on the counter substrate is applied in the normally white mode, the alignment disorder part around the wall spacer and the non-uniform threshold voltage due to the alignment disorder are not recognized by the display recognizer. The light is concealed by the wall spacer itself and light leakage can be reduced. Therefore, a liquid crystal display device with high contrast and good display quality can be obtained by suppressing light leakage due to the wall spacer.

As the wall spacer, an organic resin material mainly containing at least one of acrylic, polyimide, polyimideamide, and epoxy, or any one material of silicon oxide, silicon nitride, and silicon oxynitride Or the inorganic material which consists of these laminated films can be used.

Further, a wall-like spacer using an inorganic material, for example, silicon nitride is used as the channel etch type T.
If the FT, in particular, the portion where the amorphous semiconductor film 114 is exposed is covered, an effect as a protective film can be obtained and the reliability can be improved.

In addition, both of the convex and concave portions formed by appropriately arranging the wiring and electrodes such as the gate wiring, the source wiring, and the capacitor wiring at predetermined positions, and the wall spacers appropriately disposed at the predetermined positions, The liquid crystal may be aligned by controlling the pretilt angle of the liquid crystal.

When the present invention is used, it is possible to omit an alignment process corresponding to a rubbing process that causes electrostatic breakdown, and since the wall spacer has a role of maintaining the substrate interval, it is possible to omit the spherical spacer spraying step. , Improve productivity. Furthermore, it has an advantage that the occurrence of display unevenness can be predicted only by inspecting the uniformity of the wall spacer formed on the substrate.

Further, the shape of the wall-like spacer viewed from the top surface can be a stripe shape, a T-shape, or a ladder shape, but the present embodiment is not limited to these shapes.

The present invention having the above-described configuration will be described in more detail with the following examples.

An embodiment of the present invention will be described with reference to FIGS. 1 to 7, 9, and 17. This embodiment shows a method for manufacturing a liquid crystal display panel, and a method for forming a TFT of a pixel portion on a substrate in an inverted staggered type and manufacturing a storage capacitor connected to the TFT will be described in detail according to steps. In addition, the same drawing shows a manufacturing process of a terminal portion provided at an end portion of the substrate and electrically connected to wiring of a circuit provided on another substrate.

In FIG. 2A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass can be used for the light-transmitting substrate 100. In addition, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used.

Next, after a conductive layer is formed over the entire surface of the substrate, a first photolithography step is performed, a resist mask is formed, unnecessary portions are removed by etching, and wirings and electrodes (a gate wiring 102 including a gate electrode, a capacitor wiring) 103 and terminal 101). At this time, etching is performed so that a tapered portion is formed at least at the end portion of the gate electrode 102. A top view at this stage is shown in FIG.

The gate wiring 102 including the gate electrode, the capacitor wiring 103, and the terminal 101 of the terminal portion are preferably formed of a low-resistance conductive material such as aluminum (Al) or copper (Cu).
Since the simple substance is inferior in heat resistance and easily corroded, it is formed in combination with a heat resistant conductive material. Further, an AgPdCu alloy may be used as the low resistance conductive material. Examples of heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and chromium (Cr).
, Nd (neodymium), an alloy containing the element as a component, an alloy film combining the elements, or a nitride containing the element as a component.
For example, a laminate of Ti and Cu and a laminate of TaN and Cu can be given. Ti, Si, C
When formed in combination with a heat-resistant conductive material such as r or Nd, the flatness is improved, which is preferable. Moreover, you may form only such a heat resistant conductive material, for example, combining Mo and W.

In order to realize a liquid crystal display device, it is desirable to form the gate electrode and the gate wiring by combining a heat-resistant conductive material and a low-resistance conductive material. A suitable combination at this time will be described.

If the screen size is up to about 5 inches, a two-layer structure in which a conductive layer (A) made of a nitride of a heat-resistant conductive material and a conductive layer (B) made of a heat-resistant conductive material are laminated. The conductive layer (B) is Al,
The conductive layer (A) may be formed of an element selected from Cu, Ta, Ti, W, Nd, Cr, an alloy containing the element as a component, or an alloy film combining the elements.
aN) film, tungsten nitride (WN) film, titanium nitride (TiN) film or the like. For example, a two-layer structure in which Cr as the conductive layer (A) and Al containing Nd as the conductive layer (B) are stacked is preferable. The conductive layer (A) is 10 to 100 nm (preferably 20 to 50 n)
m), and the conductive layer (B) is 200 to 400 nm (preferably 250 to 350 nm).

On the other hand, for application to a large screen, a conductive layer (A) made of a heat resistant conductive material, a conductive layer (B) made of a low resistance conductive material, and a conductive layer (C) made of a heat resistant conductive material are laminated. It is preferable to have a three-layer structure. The conductive layer (B) made of a low resistance conductive material is made of aluminum (Al
) In addition to pure Al, 0.01-5 atomic% scandium (S
c) Al containing Ti, Nd, silicon (Si) or the like is used. The conductive layer (C) has an effect of preventing hillocks from being generated in Al of the conductive layer (B). The conductive layer (A) is 10 to 100
nm (preferably 20 to 50 nm), the conductive layer (B) is 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (C) is 10 to 100 nm (preferably 20 to 50 nm).
nm). In this embodiment, the conductive layer (A) is formed with a Ti film to a thickness of 50 nm by sputtering using Ti as a target, and the conductive layer (B) is formed by sputtering using Al as a target.
Is formed with an Al film to a thickness of 200 nm, and a conductive layer (by a sputtering method using Ti as a target)
C) was formed to a thickness of 50 nm with a Ti film.

Next, an insulating film 104a is formed over the entire surface. The insulating film 104a is formed by sputtering and has a thickness of 50 to 200 nm.

For example, a silicon nitride film is used as the insulating film 104a and is formed with a thickness of 150 nm.
Of course, the gate insulating film is not limited to such a silicon nitride film, and other insulating films such as a silicon oxide film, a silicon oxynitride film, and a tantalum oxide film are used, and a single layer or a stacked layer made of these materials is used. It may be formed as a structure. For example, a stacked structure in which the lower layer is a silicon nitride film and the upper layer is a silicon oxide film may be used.

Next, a first amorphous semiconductor film 105 with a thickness of 50 to 200 nm (preferably 100 to 150 nm) is formed over the entire surface of the insulating film 104a by a known method such as a plasma CVD method or a sputtering method ( Not shown). Typically, an amorphous silicon (a-Si) film is formed to a thickness of 100 nm by a sputtering method using a silicon target. Additional, this first amorphous semiconductor film, a microcrystalline semiconductor film, an amorphous silicon germanium film _{(Si X Ge (1-X} ), (0
<X <1)), a compound semiconductor film having an amorphous structure such as amorphous silicon carbide (Si _X C _Y ) can also be applied.

Next, a second amorphous semiconductor film containing an impurity element of one conductivity type (n-type or p-type) is formed as 2
It is formed with a thickness of 0 to 80 nm. The second amorphous semiconductor film containing an impurity element imparting one conductivity type (n-type or p-type) is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. In this embodiment, the second amorphous semiconductor film 106 containing an n-type impurity element is formed using a silicon target to which phosphorus (P) is added. Alternatively, the film may be formed by sputtering in an atmosphere containing phosphorus using a silicon target. Alternatively, the second amorphous semiconductor film containing an impurity element imparting n-type conductivity may be a hydrogenated microcrystalline silicon film (μc-Si
: H).

Next, a first conductive film 107 made of a metal material is formed by a sputtering method or a vacuum evaporation method. The material of the first conductive film 107 is not particularly limited as long as it is a metal material that can be in ohmic contact with the second amorphous semiconductor film 106. An element selected from Al, Cr, Ta, Ti,
Alternatively, an alloy containing the element as a component, an alloy film combining the elements, or the like can be given. In this embodiment, a sputtering method is used, and a Ti film formed with a thickness of 50 to 150 nm is formed as the first conductive film 107, and aluminum (Al) is formed with a thickness of 300 to 400 nm on the Ti film. Further, a Ti film having a thickness of 100 to 150 nm was formed thereon. (Fig. 2 (A))

The insulating film 104a, the first amorphous semiconductor film 105, the second containing an impurity element imparting n-type conductivity
The amorphous semiconductor film 106 and the first conductive film 107 are both formed by a known method, and can be manufactured by a plasma CVD method or a sputtering method. In this example, these films (104a, 105, 106, 107) were continuously formed by a sputtering method by appropriately switching the target and the sputtering gas. At this time, in the sputtering apparatus, it is preferable to use the same reaction chamber or a plurality of reaction chambers and to continuously laminate these films without exposing them to the atmosphere. In this way, mixing of impurities can be prevented by not exposing to the atmosphere.

Next, a second photolithography step is performed to form a resist mask 108, and unnecessary portions are removed by etching to form a wiring 111 (which will be a source wiring and a drain electrode in a later step). As an etching method at this time, wet etching or dry etching is used. At this time, the first conductive film 107, the second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity, and the first amorphous semiconductor film 105 are sequentially etched using the resist mask 108 as a mask. In the pixel TFT portion, a wiring 111 made of a first conductive film, a second amorphous semiconductor film 110 containing an impurity element imparting n-type conductivity, and a first amorphous semiconductor film 109 are formed. The In this embodiment, SiCl ₄ , Cl ₂ and BCl
The first conductive film 107 in which a Ti film, an Al film, and a Ti film are sequentially stacked is etched by dry etching using a mixed gas of ₃ as a reactive gas, and the reactive gas is changed to a mixed gas of CF ₄ and O ₂ . The first amorphous semiconductor film 105 and the second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity were selectively removed. (FIG. 2B) Further, the capacitor wiring 103 and the insulating film 104a are left in the capacitor portion, and similarly, the terminal 101 and the insulating film 104a are left in the terminal portion.

Next, after removing the resist mask 108, a resist mask is formed using a shadow mask, and the insulating film 104 a covering the pad portion of the terminal portion is selectively removed to remove the insulating film 10.
After forming 4b, the resist mask is removed. (Fig. 2 (C)
In addition, instead of the shadow mask, a resist mask may be formed by screen printing to form an etching mask.

Next, a second conductive film 112 made of a transparent conductive film is formed on the entire surface. (FIG. 2D) A top view at this time is shown in FIG. However, for simplification, the second conductive film 112 formed on the entire surface is not shown in FIG.

As the material of the second conductive film 112, indium oxide (In ₂ O ₃ ), indium oxide tin oxide alloy (abbreviated as In ₂ O ₃ —SnO ₂ , ITO) or the like is used by sputtering or vacuum evaporation. Form. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, since etching of ITO is likely to generate a residue, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and excellent thermal stability as compared with ITO, even if the wiring 111 in contact with the second conductive film 112 is formed of an Al film, a corrosion reaction occurs. Can be prevented. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.

Next, a third photolithography process is performed to form resist masks 113a to 113c. Unnecessary portions are removed by etching, so that the first amorphous semiconductor film 114, the source region 115, the drain region 116, and the source electrode are removed. 117, a drain electrode 118, and a pixel electrode 119 are formed. (Fig. 3 (A))

In the third photolithography step, the second conductive film 112 is patterned, and at the same time, the wiring 111 and the second amorphous semiconductor film 110 containing an impurity element imparting n-type and the first conductive film 112 are formed.
A part of the amorphous semiconductor film 109 is removed by etching to form an opening. In this embodiment, first, the second conductive film 112 made of ITO is mixed with a mixed solution of nitric acid and hydrochloric acid or a chlorinated second solution.
The second amorphous semiconductor film 110 containing an impurity element imparting n-type by dry etching is selectively removed by wet etching using an iron-based solution and the wiring 111 is selectively removed by wet etching. A part of the amorphous semiconductor film 109 was etched. In this embodiment, wet etching and dry etching are used. However, the practitioner may appropriately select the reaction gas and perform only dry etching, or the practitioner may appropriately select the reaction solution and perform wet etching. You may do it alone.

Further, the bottom of the opening reaches the first amorphous semiconductor film, and the first amorphous semiconductor film 114 having a recess is formed. By this opening, the wiring 111 is separated into the source wiring 117 and the drain electrode 118, and the second amorphous semiconductor film 110 containing the impurity element imparting n-type is separated into the source region 115 and the drain region 116. In addition, the second conductive film 120 in contact with the source wiring covers the source wiring and serves to prevent static electricity generated in a subsequent manufacturing process, particularly a rubbing process. In this embodiment, the second conductive film 120 is formed over the source wiring, but the second conductive film 120 may be removed.

In the third photolithography process, the insulating film 104b in the capacitor portion is also formed.
As a dielectric, a storage capacitor is formed by the capacitor wiring 103 and the pixel electrode 119.

Further, in the third photolithography process, the second conductive film made of the transparent conductive film which is covered with the resist mask 113c and formed in the terminal portion is left.

Next, the resist masks 113a to 113c were removed. A cross-sectional view of this state is shown in FIG.
It was shown to. FIG. 6 is a top view of one pixel, and cross-sectional views along the line AA ′ and the line BB ′ correspond to FIG. 3B, respectively.

FIG. 9A shows the gate wiring terminal portion 501 and the source wiring terminal portion 5 in this state.
A top view of 02 is shown. In addition, the same code | symbol is used for the location corresponding to FIGS. 1-3. FIG. 9B corresponds to a cross-sectional view taken along line EE ′ and FF ′ in FIG. In FIG. 9A, reference numeral 503 made of a transparent conductive film denotes a connection electrode that functions as an input terminal. In FIG. 9B, reference numeral 504 denotes an insulating film (extending from 104b), 505 denotes a first amorphous semiconductor film (extending from 114), and 506 contains an impurity element imparting n-type conductivity. A second amorphous semiconductor film (extending from 115).

In this manner, the pixel TFT portion having the inverted staggered n-channel TFT 201 and the storage capacitor 202 can be completed using three photomasks by three photolithography processes. Then, by arranging these in a matrix corresponding to each pixel to form a pixel portion, one substrate for manufacturing an active matrix type electro-optical device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

Next, alignment films 131 and 132 are formed on the active matrix substrate. Here JA
LS-2021 (manufactured by JSR) was formed by a printing method and fired.

After the alignment film was formed, a gap holding material for maintaining the gap between the substrates, in this example, a wall spacer 127 as shown in FIG. 17A was formed by performing a fourth photolithography process. Moreover, you may use the process of exposing negative type resin from a board | substrate back surface. Further, it is possible to form a wall-shaped spacer having the above-described shape even using a dry etching method or a plasma etching method.

First, NN700 (manufactured by JSR), a material mainly composed of a photosensitive acrylic material, was formed on the entire surface of the substrate with a film thickness of 4.2 μm using a spinner. An acrylic resin was used for ease of formation. The dielectric constant of the acrylic resin NN700 used in the present invention is 3.4. Next, a resist mask is formed, and unnecessary portions are removed by etching to form a wall-like spacer having a shape as shown in FIG. When the top of the head was flat, the mechanical strength as a liquid crystal display panel could be secured. As a result of SEM observation, the height of the wall spacer was 4 μm. The taper angle of the wall spacer is desirably 75.0 ° to 89.9 °, preferably 82 ° to 87 °.

Next, after the active matrix substrate and the counter substrate 124 provided with the wall spacer 122 formed in the same manner as the wall spacer are bonded to each other with a sealant while maintaining the substrate interval with the wall spacers 121 and 122. A liquid crystal material 125 is injected between the active matrix substrate and the counter substrate. As the liquid crystal material 125, a liquid crystal material having negative dielectric anisotropy (n-type liquid crystal), MLC-2038 (manufactured by Merck) is used in this embodiment. When the pretilt angle was measured, the pretilt angle could be controlled within a range of 2 to 5 °, and the display region became almost uniform at 3 °. Therefore, in the vicinity of the surface of NN700, an alignment regulating force is applied so that the major axis direction of the liquid crystal molecules is substantially parallel to the surface.

  Next, after injecting the liquid crystal material, the injection port is sealed with a resin material.

Through the above steps, a state as shown in FIG. 1 is obtained. In FIG. 1, for simplification,
Only three wall spacers and the state of liquid crystal molecules between them are shown.

When no voltage is applied in this state, the wall spacers 121 and 122 are affected by the side surfaces,
Liquid crystal molecules are arranged almost parallel to the side surface. Liquid crystal molecules other than those near the side surfaces are also affected by these liquid crystal molecules. Thus, a stable orientation having a pretilt angle of several degrees over the entire pixel is obtained. By applying a voltage equal to or higher than the threshold value of the liquid crystal, a uniform operation is performed in the tilt direction determined by the pretilt angle. That is, the wall spacers 121, 122
By using, the orientation of the entire display unit is controlled.

FIG. 18A shows a top view of the wall spacers 121 and 122 provided on both substrates. The plane cut along the dotted line XX ′ corresponds to the cross-sectional view of FIG.

Next, the flexible printed circuit board (Flexible Printed Circuit) is connected to the input terminal 101 of the terminal section.
cuit: FPC). The FPC has a copper wiring 128 formed on an organic resin film 129 such as polyimide, and is connected to a transparent conductive film covering an input terminal with an anisotropic conductive adhesive.
The anisotropic conductive adhesive is composed of an adhesive 126 and particles 127 having a conductive surface with a diameter of several tens to several hundreds μm mixed therein and plated with gold or the like.
By making contact with the transparent conductive film on 01 and the copper wiring 128, electrical contact is formed at this portion. Further, a resin layer 130 is provided to increase the mechanical strength of this portion. (Fig. 3
(C))

FIG. 7 is a diagram for explaining the arrangement of the pixel portion and the terminal portion of the active matrix substrate. Board 2
10 is provided with a pixel portion 211, and a gate wiring 208 and a source wiring 207 are formed so as to intersect with each other, and an n-channel TFT 201 connected to the gate wiring 208 and the source wiring 207 is provided corresponding to each pixel. On the drain side of the n-channel TFT 201, a pixel electrode 119 and a storage capacitor 20 are provided.
2 is connected, and the other terminal of the storage capacitor 202 is connected to the capacitor wiring 209. The structure of the n-channel TFT 201 and the storage capacitor 202 is the n-channel TFT 20 shown in FIG.
1 and the storage capacitor 202 are the same.

An input terminal portion 205 for inputting a scanning signal is formed at one end of the substrate, and the connection wiring 2
06 is connected to the gate wiring 208. Further, an input terminal portion 203 for inputting an image signal is formed at the other end portion, and is connected to the source wiring 207 by the connection wiring 204. A plurality of gate wirings 208, source wirings 207, and capacitor wirings 209 are provided in accordance with the pixel density. Further, an input terminal portion 212 for inputting an image signal and a connection wiring 213 may be provided, and the input terminal portion 203 may be alternately connected to the source wiring. Input terminal portions 203 and 205
, 212 may be provided in an arbitrary number, and the practitioner may make an appropriate decision.

Thus, in this embodiment, an active matrix liquid crystal display panel can be manufactured by using four photomasks through four photolithography processes.

In this embodiment, the wall-shaped spacer is used, but the periphery thereof may be multi-domain aligned using a column spacer.

FIG. 8 shows an example of a method for mounting a liquid crystal display panel. In the liquid crystal display panel, an input terminal portion 302 is formed at an end portion of a substrate 301 on which a TFT is manufactured, and this is formed by a terminal 303 formed of the same material as the gate wiring as shown in the first embodiment. Is done. Then, they are bonded together by a sealing agent 305 containing the counter substrate 304 and the spacer 306, and further polarizing plates 307, 3
08, a color filter (not shown) is provided. Then, the spacer 322 is fixed to the housing 321.

Note that the TFT in which the active layer is formed of the amorphous silicon film obtained in Example 1 has a small field-effect mobility and can be obtained only about 1 cm ² / Vsec. For this purpose, a driving circuit for displaying an image is formed of an IC chip, and a TAB (tape automated bonding) method or a COG (COG)
chip on glass) method. In this embodiment, an example in which a driver circuit is formed on an IC chip 313 and mounted by a TAB method is shown. This includes flexible printed wiring boards (Flexib
le Printed Circuit (FPC) is used, and the FPC has a copper wiring 310 formed on an organic resin film 309 such as polyimide, and is connected to the input terminal 302 with an anisotropic conductive adhesive. The input terminal is a transparent conductive film provided in contact with the wiring 303. The anisotropic conductive adhesive is composed of an adhesive 311 and particles 312 having a conductive surface with a diameter of several tens to several hundreds μm mixed therein and plated with gold or the like. And copper wiring 310
By making contact with this, an electrical contact is formed at this part. A resin layer 318 is provided to increase the mechanical strength of this portion.

The IC chip 313 is connected to the copper wiring 310 with bumps 314 and sealed with a resin material 315. The copper wiring 310 is connected at a connection terminal 316 to a printed circuit board 317 on which other signal processing circuits, amplifier circuits, power supply circuits, and the like are formed.
In the transmissive liquid crystal display panel, a light source 319 and a light guide 320 are provided on the counter substrate 304 and used as a backlight.

Thus, by using the liquid crystal display panel of Example 1, it was possible to obtain a multi-domain vertical alignment type liquid crystal display device with a wide viewing angle display with little gap unevenness.

In this embodiment, an example of forming a liquid crystal display panel by forming a protective film is shown in FIG. In addition,
Since this embodiment is the same up to the state of FIG. 3B of the first embodiment, different points will be described below. Further, the same reference numerals are used for the portions corresponding to FIG.

First, after obtaining the state of FIG. 3B according to Example 1, a thin inorganic insulating film is formed on the entire surface. As the thin inorganic insulating film, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a tantalum oxide film formed by a sputtering method or a plasma CVD method is used. It may be formed as a structure.

Next, a fourth photolithography step is performed, a resist mask is formed, unnecessary portions are removed by etching, and an insulating film 402 is formed in the pixel TFT portion and an inorganic insulating film 401 is formed in the terminal portion. The inorganic insulating films 401 and 402 function as a passivation film. In the terminal portion, the thin inorganic insulating film 401 is removed by a fourth photolithography process, and the second conductive film made of a transparent conductive film formed on the terminal 101 in the terminal portion is exposed.

If the following steps are performed according to Example 1, the state shown in FIG. 14 can be obtained. However, the fourth photolithography process at the time of manufacturing the wall-shaped spacer in Example 1 is referred to as a fifth photolithography process.

Thus, in this embodiment, an inverted staggered n-channel TFT protected by an inorganic insulating film and a storage capacitor can be completed by using five photomasks through five photolithography processes. In addition, an active matrix liquid crystal display panel in which a substrate including a pixel portion in which these are arranged in a matrix corresponding to each pixel is used as one substrate can be obtained.

Note that this embodiment can be freely combined with the configuration of Embodiment 1 or Embodiment 2.

In Example 1, the insulating film, the first amorphous semiconductor film, the second containing an impurity element imparting n-type conductivity
Although an example in which the amorphous semiconductor film and the first conductive film are stacked by sputtering is shown, in this embodiment, an example using plasma CVD is shown.

In this embodiment, the insulating film, the first amorphous semiconductor film, and the second amorphous semiconductor film containing an impurity element imparting n-type conductivity are formed by a plasma CVD method.

In this embodiment, a silicon oxynitride film is used as the insulating film, and is formed by plasma CVD.
It is formed with a thickness of 0 nm. At this time, in the plasma CVD apparatus, the power supply frequency is 13 to 70.
It may be performed at MHz, preferably 27 to 60 MHz. By using a power supply frequency of 27 to 60 MHz, a dense insulating film can be formed, and a withstand voltage as a gate insulating film can be increased. Further, a silicon oxynitride film manufactured by adding N ₂ O to SiH ₄ and NH ₃ is a preferable material for this application because the fixed charge density in the film is reduced. Of course, the gate insulating film is not limited to such a silicon oxynitride film, and other insulating films such as a silicon oxide film, a silicon nitride film, and a tantalum oxide film are used, and a single layer or a stacked layer made of these materials is used. It may be formed as a structure. Alternatively, a stacked structure in which the lower layer is a silicon nitride film and the upper layer is a silicon oxide film may be used.

For example, when a silicon oxide film is used, tetraethyl orthosilicate (TEOS) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 250 to 350 ° C., and a high frequency (13.56 MHz). ) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 300 to 400 ° C. thereafter.

As the first amorphous semiconductor film, a hydrogenated amorphous silicon (a-Si: H) film is typically formed to a thickness of 100 nm by a plasma CVD method. At this time, in the plasma CVD apparatus, the power supply frequency may be 13 to 70 MHz, preferably 27 to 60 MHz. By using a power supply frequency of 27 to 60 MHz, it becomes possible to improve the deposition rate, and the deposited film is preferable because it becomes an a-Si film with a low defect density. In addition, a compound semiconductor film having an amorphous structure such as a microcrystalline semiconductor film or an amorphous silicon germanium film can be applied to the first amorphous semiconductor film.

In addition, in the formation of the insulating film and the first amorphous semiconductor film by a plasma CVD method, if pulse modulated discharge of 100 to 100 kHz is performed, generation of particles due to a gas phase reaction of the plasma CVD method can be prevented. This is preferable because pinholes can be prevented from being generated during film formation.

In this embodiment, as the semiconductor film containing one conductivity type impurity element, a second amorphous semiconductor film containing an impurity element imparting n-type is formed to a thickness of 20 to 80 nm. For example,
An a-Si: H film containing an n-type impurity element may be formed. For this purpose, silane (Si
Phosphine (PH ₃ ) is added at a concentration of 0.1 to 5% with respect to H ₄ ). Alternatively, a hydrogenated microcrystalline silicon film (μc-Si: H) may be used instead of the second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity.

These films can be continuously formed by appropriately switching the reaction gas. In the plasma CVD apparatus, the same reaction chamber or a plurality of reaction chambers can be used, and these films can be continuously stacked without being exposed to the atmosphere.
In this manner, the continuous film formation without being exposed to the air can prevent impurities from being mixed into the first amorphous semiconductor film.

  Note that this embodiment can be combined with any one of Embodiments 1 to 3.

In Example 1 or Example 4, the insulating film, the first amorphous semiconductor film, the second amorphous semiconductor film containing an impurity element imparting n-type conductivity, and the first conductive film are sequentially and continuously formed. An example of stacking was shown.
FIG. 10 shows an example of an apparatus provided with a plurality of chambers used in the case where films are continuously formed as described above.

FIG. 10 shows an outline of the apparatus (continuous film forming system) shown in this embodiment as viewed from the upper surface. FIG.
10 to 15 are airtight chambers. Each chamber is provided with a vacuum exhaust pump and an inert gas introduction system.

The chambers 10 and 15 are load lock chambers for loading the sample (processing substrate) 30 into the system. Reference numeral 11 denotes a first chamber for forming the insulating film 104. Reference numeral 12 denotes a second chamber for forming the first amorphous semiconductor film 105. Reference numeral 13 denotes a third chamber for forming the second amorphous semiconductor film 106 imparting n-type conductivity.
Reference numeral 14 denotes a fourth chamber for forming the first conductive film 107. Reference numeral 20 denotes a common chamber for samples arranged in common for each chamber.

  An example of the operation is shown below.

Initially, all chambers are once evacuated to a high vacuum and then further inert gas,
Here, a state of purging with nitrogen (normal pressure) is assumed. In addition, all the gate valves 22 to
27 is closed.

First, the processing substrate is carried into the load lock chamber 10 together with the cassette 28 in which a large number of substrates are stored. After loading the cassette, the door of the load lock chamber (not shown) is closed. In this state,
The gate valve 22 is opened and one processing substrate 30 is taken out from the cassette and taken out into the common chamber 20 by the robot arm 21. At this time, alignment is performed in the common room. In addition, this board | substrate 30 used what formed wiring 101,102,103 obtained according to Example 1. FIG.

Here, the gate valve 22 is closed, and then the gate valve 23 is opened. Then, the processing substrate 30 is transferred to the first chamber 11. In the first chamber, film formation is performed at a temperature of 150 ° C. to 300 ° C. to obtain the insulating film 104. Note that as the insulating film, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, a stacked film of these, or the like can be used. In this embodiment, a single layer silicon nitride film is used, but a laminated structure of two layers or three or more layers may be used. Note that although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.

After completion of the formation of the insulating film, the processing substrate is drawn out to the common chamber by the robot arm and transferred to the second chamber 12. 150 in the second chamber as in the first chamber.
A film formation process is performed at a temperature of from about 0 to 300 ° C., and the first amorphous semiconductor film 105 is formed by a plasma CVD method.
Get. Note that as the first amorphous semiconductor film, a microcrystalline semiconductor film, an amorphous germanium film, an amorphous silicon germanium film, a stacked film of these, or the like can be used. Further, the formation temperature of the first amorphous semiconductor film may be set to 350 ° C. to 500 ° C., and the heat treatment for reducing the hydrogen concentration may be omitted. Note that although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.

After completion of the formation of the first amorphous semiconductor film, the processing substrate is drawn out to the common chamber and transferred to the third chamber 13. In the third chamber, it is 150 ° C. to 30 ° like the second chamber.
A film formation process is performed at a temperature of 0 ° C., and a second amorphous semiconductor film 106 containing an impurity element imparting n-type (P or As) is obtained by a plasma CVD method. Note that although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.

After the formation of the second amorphous semiconductor film containing the impurity element imparting n-type conductivity, the treatment substrate is drawn into the common chamber and transferred to the fourth chamber 14. In the fourth chamber, the first conductive film 107 is obtained by a sputtering method using a metal target.

The substrate to be processed on which the four layers are continuously formed in this way is transferred to the load lock chamber 15 by the robot arm and stored in the cassette 29.

Needless to say, the apparatus shown in FIG. 10 is merely an example. Further, this embodiment needs to be freely combined with any one of Embodiments 1 to 4.

In the fifth embodiment, an example in which a plurality of chambers are used for continuous lamination is shown. In this embodiment, the apparatus shown in FIG. 11 is used for continuous lamination while maintaining a high vacuum in one chamber. did.

In this example, the apparatus system shown in FIG. 11 was used. In FIG. 11, 40 is a processing substrate, 50 is a common chamber, 44 and 46 are load lock chambers, 45 is a chamber, and 42 and 43 are cassettes. In this embodiment, in order to prevent contamination that occurs when the substrate is conveyed, the layers are formed in the same chamber.

  This embodiment can be freely combined with any one of Embodiments 1 to 4.

However, when applying to Example 1, a plurality of targets are prepared in the chamber 45,
Sequentially, the insulating gas 104, the first amorphous semiconductor film 105, the second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity, and the first conductive film 107 are stacked by changing the reaction gas. That's fine.

Further, in the case of applying to the fourth embodiment, the reaction gas is sequentially replaced with the insulating film 104, the first film.
Amorphous semiconductor film 105, second amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity
May be laminated.

In the first embodiment, an example in which the second amorphous semiconductor film containing an impurity element imparting n-type conductivity is formed by a sputtering method is shown, but in this embodiment, an example in which the second amorphous semiconductor film is formed by a plasma CVD method is shown. Note that this example is the same as Example 1 except for the method for forming the second amorphous semiconductor film containing the impurity element imparting n-type conductivity.
Only the differences will be described below.

If phosphine (PH ₃ ) is added at a concentration of 0.1 to 5% with respect to silane (SiH ₄ ) as a reaction gas using a plasma CVD method, a second amorphous material containing an impurity element imparting n-type conductivity A quality semiconductor film can be obtained.

In Example 7, the second amorphous semiconductor film containing the impurity element imparting n-type is formed by plasma CV.
Although an example of formation by the D method is shown, this embodiment shows an example using a microcrystalline semiconductor film containing an impurity element imparting n-type conductivity.

The forming temperature is set to 80 to 300 ° C., preferably 140 to 200 ° C., and a gas mixture of silane gas (SiH ₄ : H ₂ = 1: 10 to 100) diluted with hydrogen and phosphine (PH ₃ ) is used as a reaction gas. A microcrystalline silicon film can be obtained by setting the pressure to 0.1 to 10 Torr and the discharge power to 10 to 300 mW / cm ² . Alternatively, phosphorus may be formed by plasma doping after the microcrystalline silicon film is formed.

FIG. 12 is a diagram schematically showing how the electro-optical device is assembled using the COG method. A pixel region 803, an external input / output terminal 804, and a connection wiring 805 are formed on the first substrate. A region surrounded by a dotted line is an IC chip bonding region 801 on the scanning line side and an IC chip bonding region 802 on the data line side. A counter electrode 809 is formed over the second substrate 808 and is bonded to the first substrate 800 with a sealant 810. Liquid crystal is sealed inside the sealant 810 to form a liquid crystal layer 811. The first substrate and the second substrate are bonded to each other with a predetermined interval. The nematic liquid crystal is 3 to 8 μm, and the smectic liquid crystal is 1 to 2.
4 μm.

The IC chips 806 and 807 have different circuit configurations on the data line side and the scanning line side. The IC chip is mounted on the first substrate. An FPC (Flexible Printed Circuit) 812 for inputting power and control signals from the outside is attached to the external input / output terminal 804. In order to increase the adhesive strength of the FPC 812, a reinforcing plate 813 may be provided. Thus, the electro-optical device can be completed. If the IC chip is subjected to electrical inspection before being mounted on the first substrate, the yield in the final process of the electro-optical device can be improved and the reliability can be improved.

As a method for mounting the IC chip on the first substrate, a connection method using an anisotropic conductive material, a wire bonding method, or the like can be employed. An example is shown in FIG. FIG.
(A) shows an example in which the IC chip 908 is mounted on the first substrate 901 using an anisotropic conductive material. A pixel region 902, a lead line 906, a connection wiring, and an input / output terminal 907 are provided over the first substrate 901. The second substrate is bonded to the first substrate 901 with a sealant 904, and a liquid crystal layer 905 is provided therebetween.

Further, an FPC 912 is bonded to one end of the connection wiring and the input / output terminal 907 with an anisotropic conductive material. The anisotropic conductive material is a resin 915 and several tens to several hundreds of μ with Au or the like plated on the surface.
The conductive particles 914 are connected to the connection wiring and the input / output terminals 90 by the conductive particles 914.
7 and a wiring 913 formed in the FPC 912 are electrically connected. IC chip 90
8 is similarly bonded to the first substrate with an anisotropic conductive material, and the conductive particles 910 mixed in the resin 911 are used to connect the input / output terminals 909 and the lead wires 906 or connection wirings provided on the IC chip 908. The input / output terminal 907 is electrically connected.

Further, as shown in FIG. 13B, an IC chip is fixed to the first substrate with an adhesive 916,
The input / output terminals of the IC chip and the lead wires or connection wirings may be connected by Au wires 917. Then, the resin 918 is sealed.

The mounting method of the IC chip is not limited to the method based on FIG. 12 and FIG.
In addition to those described here, a known COG method, wire bonding method, or TAB method can be used.

  This embodiment can be freely combined with any one of Embodiments 1, 3 to 8.

This embodiment shows an example in which a plastic substrate (or plastic film) is used as a substrate. Since this embodiment is almost the same as the first embodiment except that a plastic substrate is used as the substrate, only differences will be described below.

As a material for the plastic substrate, PES (polyethylene sulfite), PC (polycarbonate), PET (polyethylene terephthalate), or PEN (polyethylene naphthalate) can be used.

An active matrix substrate is completed when manufactured according to Embodiment 1 using a plastic substrate. Note that the insulating film, the first amorphous semiconductor film, and the second amorphous semiconductor film containing an impurity element imparting n-type conductivity can be formed by a sputtering method with a relatively low deposition temperature. desirable.

A TFT having good characteristics can be provided over a plastic substrate, and the display device can be further reduced in weight. Further, since the substrate is made of plastic, a flexible electro-optical device can be obtained. Moreover, assembly becomes easy.

In addition, a present Example can be freely combined with any one of Examples 1-3, or Example 9. FIG.

In the first embodiment, an example in which wall-like spacers are formed on both the substrate 100 and the counter substrate 124 is shown. However, in this embodiment, an example in which the wall-like spacers are formed only on the counter substrate is shown in FIG. Note that this embodiment is the same as the first embodiment except that the wall spacer 1501 is formed only on the counter substrate 124, and therefore only different points will be described.

In this embodiment, an inverted staggered n-channel TFT and a storage capacitor can be completed using three photomasks by three photolithography processes. In addition, an active matrix liquid crystal display panel in which a substrate including a pixel portion in which these are arranged in a matrix corresponding to each pixel is used as one substrate can be obtained.

FIG. 18B shows a top view of the wall spacer provided on the counter substrate. The plane cut along the dotted line YY ′ corresponds to the cross-sectional view of FIG.

Further, when a liquid crystal display device provided with a wall spacer on the counter substrate is applied to a normally white mode, an alignment disorder portion around the wall spacer 1501 and a non-uniform threshold voltage due to the alignment disorder are: From the display recognizer, it is hidden by the wall spacer itself and light leakage can be reduced. Therefore, by suppressing light leakage due to the wall-shaped spacer, a multi-domain vertical alignment type liquid crystal display device having a good display quality with high contrast can be obtained.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 10.

FIG. 16 shows an example in which an alignment film is formed after forming a convex portion on an active matrix substrate. Note that this embodiment is the same as the first embodiment except that the alignment films 1601 and 1602 and the protrusions 1603 are formed, and therefore only different points will be described.

  First, an active matrix substrate is formed according to the first embodiment.

Next, a convex portion 1603 having a shape different from that of the wall spacer of the first embodiment is formed.
The protrusion 1603 is made of an organic resin material containing at least one of acrylic, polyimide, polyimideamide, and epoxy as a main component, or any one material of silicon oxide, silicon nitride, silicon oxynitride, or An inorganic material made of these laminated films may be used.

FIG. 16 shows an example in which the wiring is formed on the pixel electrode. However, the wiring is arranged at a desired position, a convex portion is formed on the surface of the insulating film covering the wiring, and the liquid crystal is aligned using the convex portion. It is good also as a structure.

Next, an alignment film 1601 (JALS-2021; JSR) for vertical alignment is formed on the convex portion 1603.
Formed). Wall-like spacers similar to those in Example 1 are formed on the counter substrate. An alignment film 1602 for vertical alignment is also formed on the counter substrate 124 provided with the counter electrode. Thereafter, the two substrates are bonded together with a sealant while maintaining the distance between the substrates with a wall-like spacer provided on the counter substrate, and then an n-type liquid crystal material is injected between the substrates. After injecting the liquid crystal material, the injection port is sealed with a resin material.

Thereafter, according to the first embodiment, wiring for electrical connection to the outside is connected to complete the liquid crystal display panel.

When no voltage is applied, the alignment of the n-type liquid crystal in a certain direction is controlled by the wall spacer and alignment film 1601 on the active matrix substrate and the wall spacer and alignment film 1602 on the counter substrate. By using the liquid crystal display panel of this embodiment, a multi-domain vertical alignment type liquid crystal display device with a wide viewing angle display with little gap unevenness can be obtained.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 10.

A top view of the wall spacer shown in the first embodiment is shown in FIG. In this embodiment, an arrangement of wall spacers different from that in Embodiment 1 is shown.

The wall spacer shown in FIG. 18B is an example in which a linear wall spacer is formed on only one substrate as shown in the eleventh embodiment.

The wall spacer shown in FIG. 18C has a branched shape. Adjacent wall spacers may be provided on one substrate, or may be provided on both substrates.

Further, the wall-like spacer shown in FIG. 18 (d) has a lattice shape. In the case of the wall spacer shown in FIG. 18D, the wall spacer is provided on one substrate. In the case of the wall-shaped spacer shown in FIG. 18D, after the liquid crystal is dropped, it is bonded to the other substrate.

Note that the present invention is not limited to the top surface arrangement shown in FIG. 18 and may be any arrangement that can align the n-type liquid crystal. For example, a T-shaped or ladder-shaped arrangement may be used.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 12.

In this embodiment, an example in which a protective circuit is provided in a region other than the pixel portion by using the same material film as the pixel electrode will be described with reference to FIG.

In FIG. 19A, reference numeral 701 denotes a wiring, which indicates a gate wiring, a source wiring, or a capacitor wiring extended from the pixel portion. Further, the electrode 701 made of the second conductive film is formed so as to fill a region where the wiring 701 is not formed and so as not to overlap with the wiring 701. In this embodiment, an example in which a protective circuit is formed without increasing the number of masks is shown, but it is needless to say that the present invention is not limited to the structure in FIG. For example, the protection circuit may be formed of a protection diode or TFT by increasing the mask.

  FIG. 19B shows an equivalent circuit diagram.

With such a configuration, generation of static electricity due to friction between the manufacturing apparatus and the insulating substrate in the manufacturing process can be prevented. In particular, the TFT and the like can be protected from static electricity generated during rubbing of the liquid crystal alignment treatment performed in the manufacturing process.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 13.

The bottom gate type TFT formed by implementing any one of the above-described Examples 1 to 14 can be applied to various electro-optical devices (active matrix type liquid crystal display, active matrix type E).
L display, active matrix EC display)
Can be used. That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.

Such electronic devices include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book). An example of them is shown in FIGS.
It is shown in 1.

FIG. 20A illustrates a personal computer, which includes a main body 2001, an image input unit 2002,
A display portion 2003, a keyboard 2004, and the like are included. The present invention can be applied to the display portion 2003.

FIG. 20B illustrates a video camera, which includes a main body 2101, a display portion 2102, and an audio input portion 21.
03, an operation switch 2104, a battery 2105, an image receiving unit 2106, and the like. The present invention can be applied to the display portion 2102.

FIG. 20C illustrates a mobile computer (mobile computer), which includes a main body 2201.
, A camera unit 2202, an image receiving unit 2203, an operation switch 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 20D illustrates a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 2401, a display portion 2402, a speaker portion 2403, and a recording medium 2404 are illustrated.
Operation switch 2405 and the like. This player uses a DVD (Di as a recording medium).
gial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games, and the Internet.
The present invention can be applied to the display portion 2402.

FIG. 20E illustrates a digital camera, which includes a main body 2501, a display portion 2502, and an eyepiece portion 250.
3, an operation switch 2504, an image receiving unit (not shown), and the like. Display unit 2502 of the present invention
Can be applied to.

FIG. 21A illustrates a mobile phone, which includes a main body 2901, an audio output unit 2902, and an audio input unit 29.
03, a display portion 2904, an operation switch 2905, an antenna 2906, and the like. The present invention can be applied to the display portion 2904.

FIG. 21B illustrates a portable book (electronic book), which includes a main body 3001 and display portions 3002 and 300.
3, a storage medium 3004, an operation switch 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.

FIG. 21C illustrates a display, which includes a main body 3101, a support base 3102, and a display portion 3103.
Etc. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-14.

Claims (9)

A first substrate having a pixel portion in which a plurality of thin film transistors are formed;
A second substrate facing the first substrate;
A liquid crystal material having negative dielectric anisotropy sandwiched between the first substrate and the second substrate;
A plurality of gap retainers provided on the second substrate for maintaining an interval between the first substrate and the second substrate;
A vertical alignment film which is provided on each of the plurality of thin film transistors and on the gap retaining material and is not subjected to rubbing;
A protection circuit including a thin film transistor formed in a region other than the pixel portion of the first substrate;
Have
The gap retaining material has a shape in which a surface on the first substrate side is smaller than a surface on the second substrate side, and a surface on the first substrate side is flat. Liquid crystal display device. A first substrate having a pixel portion in which a plurality of thin film transistors are formed;
A second substrate facing the first substrate;
A liquid crystal material having negative dielectric anisotropy sandwiched between the first substrate and the second substrate;
A gap holding material provided on the second substrate for holding a gap between the first substrate and the second substrate;
A vertical alignment film which is provided on each of the plurality of thin film transistors and on the gap retaining material and is not subjected to rubbing;
A protection circuit including a thin film transistor formed in a region other than the pixel portion of the first substrate;
Have
The gap holding material has a shape in which a surface on the first substrate side is smaller than a surface on the second substrate side, and a surface on the first substrate side is flat, and the gap holding material A side surface of the liquid crystal display device is provided with a taper angle of 75.5 ° to 89.9 °.   3. The liquid crystal display device according to claim 1, wherein a surface of the gap holding member on the first substrate side has a stripe shape.   3. The liquid crystal display device according to claim 1, wherein a surface of the gap holding member on the first substrate side is linear.   5. The liquid crystal display device according to claim 1, wherein the gap retaining material is made of a material mainly composed of a photosensitive acrylic material. 6.   6. The thin film transistor formed in a region other than the plurality of thin film transistors and the pixel portion is an inverted staggered type and a channel etch type thin film transistor according to claim 1. Liquid crystal display device.   A personal computer using the liquid crystal display device according to any one of claims 1 to 6.   A display using the liquid crystal display device according to claim 1.   An electronic book using the liquid crystal display device according to any one of claims 1 to 6.

Images