JP2003234354A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in a conventional liquid crystal display that high manufacturing cost is involved for manufacturing an TFT because it requires the use of at least 5 or more photomasks. <P>SOLUTION: An insulating film 104, an amorphous semiconductor film 105 for channel formation, an n-type semiconductor film 106 formed as source and drain regions, and a conductive film 107 formed as source wiring and drain electrode are stacked (Fig. (A)), and then subjected to patterning operation with an identical photomask (Fig. (B)). A conductive film 118 formed as a pixel electrode is formed (Fig. (C)) and subjected to patterning operation using the same photomask to form a pixel electrode 127, source wiring 125, a drain electrode 126, a source region 123, a drain region 124 and an amorphous semiconductor film 122 for channel formation (Fig. (D)). Since terminal parts are formed at a time, the pixel and terminal of a liquid crystal display can be manufactured in four photolithographic steps. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electro-optical device represented by a liquid crystal display panel and an electronic device in which such an electro-optical device is mounted as a component.

[0002] In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundreds nm) formed on a substrate having an insulating surface has been receiving attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and their development is urgently needed especially as a switching element for image display devices.

Conventionally, a liquid crystal display device has been known as an image display device. Active-matrix liquid crystal display devices have come to be widely used because high-definition images can be obtained as compared with passive liquid crystal display devices. In an active matrix type liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. More specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, the liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated. The optical modulation is recognized by the observer as a display pattern.

The applications of such an active matrix type liquid crystal display device are widespread, and the demand for high definition, high aperture ratio and high reliability is increasing along with the increase in screen size. At the same time, demands for improved productivity and cost reduction are also increasing.

Conventionally, an amorphous silicon film is preferably used as the amorphous semiconductor film because it can be formed on a large-sized substrate at a low temperature of 300 ° C. or lower. Further, an inverted stagger type (or bottom gate type) TFT having a channel formation region formed of an amorphous semiconductor film is often used.

[0007]

Conventionally, in the active matrix type liquid crystal display device, the TFT is formed on the substrate by the photolithography technique using at least five photomasks. The manufacturing cost was high. In order to improve productivity and yield, reducing the number of steps is considered as an effective means.

Specifically, it is necessary to reduce the number of photomasks required for manufacturing the TFT. The photomask is used in the photolithography technique to form a photoresist pattern as a mask for an etching process on a substrate.

By using one photomask, the steps of resist coating, pre-baking, exposure, development, post-baking and the like, and the steps before and after the steps of forming a film and etching, and further removing the resist, A washing and drying process is added, which is complicated and has been a problem.

Further, since the substrate is an insulator, static electricity is generated due to friction during the manufacturing process. When this static electricity is generated, a short circuit occurs at the intersection of the wirings provided on the substrate, or the TFT is deteriorated or destroyed by the static electricity to cause a display defect or image quality deterioration in the liquid crystal display device. In particular, static electricity is generated during the rubbing of the liquid crystal alignment treatment performed in the manufacturing process, which is a problem.

The present invention addresses such a problem, and in a semiconductor device typified by an active matrix liquid crystal display device, the number of steps for manufacturing a TFT is reduced to reduce the manufacturing cost and improve the yield. The challenge is to achieve it.

Further, the destruction of the TFT due to static electricity and the TFT
It is an object of the present invention to provide a structure and a method for manufacturing the structure capable of solving the problem of characteristic deterioration of.

[0013]

In order to solve the above problems, in the present invention, first, a gate wiring is formed on the first photomask.

Then, a gate insulating film, a non-doped amorphous silicon film (hereinafter referred to as an a-Si film), and an amorphous silicon film containing an impurity element imparting n-type (hereinafter referred to as n ⁺ a
-Referred to as a Si film) and a conductive film are continuously formed.

Then, a gate insulating film, an active layer made of an a-Si film, a source wiring (including a source electrode) and a drain electrode are patterned and formed on the second photomask.

Then, after forming the transparent conductive film, a pixel electrode made of the transparent conductive film is formed on the third photomask, and at the same time, a source region and a drain region made of the n ⁺ a-Si film are formed. A part of the a-Si film is removed.

With such a structure, the number of photomasks used in the photolithography technique can be three.

The source wiring is covered with a transparent conductive film made of the same material as the pixel electrode to protect the entire substrate from external static electricity. Further, a structure in which a protective circuit is formed using a transparent conductive film may be used. With such a configuration, it is possible to prevent generation of static electricity due to friction between the manufacturing apparatus and the insulating substrate in the manufacturing process. In particular, the TFT and the like can be protected from static electricity generated during rubbing in the liquid crystal alignment process performed in the manufacturing process.

The structure of the invention disclosed in this specification is a semiconductor device having a gate wiring, a source wiring, and a pixel electrode, and the gate wiring 102 formed on an insulating surface.
An insulating film 110 formed on the gate wiring, an amorphous semiconductor film 122 formed on the insulating film, a source region 123 and a drain region 124 formed on the amorphous semiconductor film. A source wiring 125 or an electrode 12 formed on the source region or the drain region
6 and a pixel electrode 127 formed on the electrode, the drain region 124 or the source region 12
3 is a semiconductor device in which one end surface of No. 3 substantially coincides with the end surface of the insulating film 110, the end surface of the amorphous semiconductor film 122, and the end surface of the electrode 126.

According to another aspect of the present invention, there is provided a gate wiring,
A semiconductor device having a source line and a pixel electrode, wherein a gate line 102 formed on an insulating surface, an insulating film 110 formed on the gate line, and an amorphous film formed on the insulating film. Semiconductor film 122, source region 123 and drain region 124 formed on the amorphous semiconductor film, source wiring 125 or electrode 126 formed on the source region or the drain region, and on the electrode One end face of the drain region 124 or the source 123 region having the formed pixel electrode 127 is substantially the same as the end face of the insulating film 110, the end face of the amorphous semiconductor film 122, and the end face of the electrode 126. Match and
The other end surface is substantially the same as the end surface of the pixel electrode 127 and the other end surface of the electrode 126.

Further, in each of the above structures, the source region and the drain region are formed of an amorphous semiconductor film containing an impurity element imparting n-type.

In each of the above structures, the insulating film,
The amorphous semiconductor film, the source region, and the drain region are formed continuously without being exposed to the atmosphere.

In each of the above structures, the insulating film,
The amorphous semiconductor film, the source region, or the drain region is formed by a sputtering method.

Further, in each of the above structures, as shown in FIG. 2D, the source region 123 and the drain region 124 are formed by the same mask as the amorphous semiconductor film 122 and the electrode 126. It is characterized by that. Further, the source region and the drain region are
It is characterized in that it is formed by the same mask as the source wiring 125.

Further, in each of the above structures, as shown in FIG. 2D, the source region 123 and the drain region 124 are formed by the same mask as the source wiring 125 and the pixel electrode 127. Is characterized by.

In each of the above structures, the amorphous semiconductor film of the amorphous semiconductor film is formed by the etching process of FIG.
A film thickness in a region in contact with the source region and the drain region is thicker than a film thickness in a region between the region in contact with the source region and the region in contact with the drain region, that is, a channel-etch type bottom gate structure. There is.

Further, the structure of the invention for realizing the above-mentioned structure includes a first step of forming the gate wiring 102 using the first mask and a second step of forming the insulating film 104 covering the gate wiring. A third step of forming a first amorphous semiconductor film 105 on the insulating film, and a second amorphous semiconductor containing an impurity element imparting n-type on the first amorphous semiconductor film. A fourth step of forming the film 106, a fifth step of forming the first conductive film 107 on the second amorphous semiconductor film, a step of forming the insulating film 104 and the first film by using a second mask.
Amorphous semiconductor film 105 and second amorphous semiconductor film 10
6, and the sixth step of selectively removing the first conductive film 107 to form the wiring 116 (source wiring and electrode), and the second conductivity which is in contact with and overlaps with the wiring 116 (source wiring and electrode). A seventh step of forming the film 118, and using the third mask, a part of the first amorphous semiconductor film 112, the second amorphous semiconductor film 114, and the first conductive film 1
16 and the second conductive film 118 are selectively removed to form the source region 12 made of the second amorphous semiconductor film.
3 and the drain region 124, and an eighth step of forming the pixel electrode 127 made of the second conductive film, the method for manufacturing a semiconductor device.

Further, in the above structure, the second step to the fifth step are characterized in that they are continuously formed without being exposed to the atmosphere.

Further, in each of the above-mentioned structures, the second step to the fifth step are continuously formed in the same chamber.

Further, in each of the above structures, the insulating film may be formed by a sputtering method or a plasma CVD method.

In each of the above structures, the first amorphous semiconductor film may be formed by a sputtering method or a plasma CVD method.

In each of the above structures, the second amorphous semiconductor film may be formed by a sputtering method or a plasma CVD method.

Further, in each of the above structures, the second conductive film is a transparent conductive film or a conductive film having reflectivity.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is an example of a plan view of an active matrix substrate of the present invention. Here, for simplification, one pixel configuration of a plurality of pixels arranged in a matrix is shown. 2 and 3 are views showing the manufacturing process.

As shown in FIG. 1, this active matrix substrate has a plurality of gate wirings arranged in parallel with each other and a plurality of source wirings orthogonal to each gate wiring.

A pixel electrode 127 made of a transparent conductive film is arranged in a region surrounded by the gate wiring and the source wiring. Further, the transparent conductive film 128 overlaps with the source wiring so as not to overlap with the pixel electrode 127.

Further, a capacitive wiring 103 is arranged in parallel with the gate wiring 102 between two adjacent gate wirings below the pixel electrode 127. This capacitance wiring 103
Is provided in all pixels, and the insulating film 1 shown in FIG.
A storage capacitor is formed by using 11 as a dielectric.

In addition, the gate wiring 102 and the source wiring 12
A TFT as a switching element is provided in the vicinity of the intersection of 5. This TFT is an inverted stagger type (or bottom gate type) TFT having a channel formation region formed of a semiconductor film having an amorphous structure (hereinafter referred to as an amorphous semiconductor film).

Further, this TFT has a gate electrode (which is formed integrally with the gate wiring 102) on the insulating substrate in order.
, A gate insulating film, an a-Si film, a source region and a drain region made of an n ⁺ a-Si film, a source electrode (formed integrally with the source wiring 125), and an electrode 126 (hereinafter also referred to as a drain electrode). ) And are laminated.

In the region of the gate wiring which does not overlap with the a-Si film, the gate insulating film does not exist on the gate wiring.

Therefore, the pixel electrode 12 overlapping the electrode 126
Reference numeral 7 is formed so as not to overlap the gate wiring.

At the intersection of the gate line and the source line, the transparent conductive film at the end of the source line is removed so as not to cause a short circuit. Further, the end portion of the electrode 117 is removed so that the capacitor wiring and the pixel electrode are not short-circuited.

Below the source wiring (including the source electrode) and the drain electrode 126, an insulating substrate is sequentially formed.
A gate insulating film, an a-Si film, and an n ⁺ a-Si film are laminated.

In the a-Si film, the region between the region in contact with the source region and the region in contact with the drain region is
The film thickness is thinner than other regions. The film thickness was reduced because part of the a-Si film was removed when the n ⁺ a-Si film was separated by etching to form the source region and the drain region. Further, the end surface of the pixel electrode, the end surface of the drain electrode, and the end surface of the drain region are aligned with each other by this etching.

Similarly, the end surface of the transparent conductive film covering the source electrode, the end surface of the source region, and the end surface of the source wiring are aligned.

The present invention having the above structure will be described in more detail with reference to the following embodiments.

[0048]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. 1 to 6 and 9. This example shows a method for manufacturing a liquid crystal display device, and a method for forming a TFT in a pixel portion in an inverted stagger type on a substrate and manufacturing a storage capacitor connected to the TFT will be described in detail in accordance with steps. Further, in the same drawing, a manufacturing process of an input terminal portion which is provided at an end portion of the substrate and is electrically connected to wiring of a circuit provided on another substrate is shown.

In FIG. 2A, the transparent substrate 100 is made of Corning # 7059 glass or # 173.
A glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by 7 glass can be used. Alternatively, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used.

Next, after forming a conductive layer on the entire surface of the substrate,
A first photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to form wirings and electrodes (a gate wiring 102 including a gate electrode, a capacitor wiring 103, and a terminal 101). At this time, etching is performed so that a tapered portion is formed at least at the end portion of the gate electrode 102. A top view at this stage is shown in FIG.
It was shown to.

The gate wiring 102 including the gate electrode, the capacitor wiring 103, and the terminal 101 of the terminal portion are made of aluminum (A
It is desirable to use a low resistance conductive material such as 1), but since Al alone has problems such as poor heat resistance and easy corrosion, it is formed in combination with a heat resistant conductive material. As the heat-resistant conductive material, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M
o), an element selected from chromium (Cr) and Nd (neodymium), or an alloy containing the above element, an alloy film in which the above elements are combined, or a nitride containing the above element. Further, when formed in combination with a heat resistant conductive material such as Ti, Si, Cr or Nd, flatness is improved, which is preferable. Alternatively, only such a heat-resistant conductive material may be formed by combining Mo and W, for example.

In order to realize a liquid crystal display device, it is desirable that the gate electrode and the gate wiring are formed by combining a heat resistant conductive material and a low resistance conductive material. A suitable combination at this time will be described.

If the screen size is up to about 5 inches, a two-layer structure is formed by laminating a conductive layer (A) made of a nitride of a heat resistant conductive material and a conductive layer (B) made of a heat resistant conductive material.
The conductive layer (B) may be formed of an element selected from Al, Ta, Ti, W, Nd, and Cr, an alloy containing the above element, or an alloy film in which the above elements are combined. Is formed of a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium nitride (TiN) film, or the like.
For example, it is preferable to have a two-layer structure in which Cr is stacked as the conductive layer (A) and Al containing Nd is stacked as the conductive layer (B). The conductive layer (A) is 10 to 100 nm (preferably 20 to 50 nm), and the conductive layer (B) is 200 to 40 nm.
It is set to 0 nm (preferably 250 to 350 nm).

On the other hand, for application to a large screen, a conductive layer (A) made of a heat resistant conductive material, a conductive layer (B) made of a low resistance conductive material, and a conductive layer (C) made of a heat resistant conductive material.
It is preferable to have a three-layer structure in which and are laminated. The conductive layer (B) made of a low resistance conductive material is made of aluminum (A
l) as a component, and in addition to pure Al, 0.0
1 to 5 atomic% of scandium (Sc), Ti, Nd,
Al containing silicon (Si) or the like is used. The conductive layer (C) has an effect of preventing hillocks from being generated in Al of the conductive layer (B). The conductive layer (A) is 10 to 100 nm (preferably 20 to 50 nm), and the conductive layer (B) is 200 nm.
~ 400 nm (preferably 250-350 nm),
The conductive layer (C) has a thickness of 10 to 100 nm (preferably 20 to 5 nm).
0 nm). In this embodiment, the conductive layer (A) is formed as a Ti film with a thickness of 50 nm by a sputtering method using Ti as a target, and the conductive layer (B) is formed as an Al film with a thickness of 200 nm by a sputtering method as an Al target. To form
Conductive layer (C) by sputtering targeting Ti
Was formed with a Ti film to a thickness of 50 nm.

Next, the insulating film 104 is formed on the entire surface.
The insulating film 104 is formed by a sputtering method and has a film thickness of 50 to 200.
nm.

For example, a silicon nitride film is used as the insulating film 104 and is formed to a thickness of 150 nm. Of course, the gate insulating film is not limited to such a silicon nitride film, and other insulating films such as a silicon oxide film, a silicon oxynitride film, and a tantalum oxide film are used, and a single layer or a laminated layer made of these materials is used. It may be formed as a structure. For example, a laminated structure may be used in which the lower layer is a silicon nitride film and the upper layer is a silicon oxide film.

Next, 50 to 200 nm is formed on the insulating film 104.
An amorphous semiconductor film 105 having a thickness (preferably 100 to 150 nm) is formed on the entire surface by a known method such as a plasma CVD method or a sputtering method (not shown). Typically,
An amorphous silicon (a-Si) film is formed to a thickness of 100 nm by a sputtering method using a silicon target. In addition, a compound semiconductor film having an amorphous structure such as a microcrystalline semiconductor film or an amorphous silicon germanium film can be applied to this amorphous semiconductor film.

Next, as the semiconductor film 106 containing an impurity element of one conductivity type, an amorphous semiconductor film 106 containing an impurity element imparting n-type is formed with a thickness of 20 to 80 nm. Amorphous semiconductor film 1 containing an impurity element imparting n-type
06 is formed on the entire surface by a known method such as a plasma CVD method or a sputtering method. Typically, an n ⁺ a-Si: H film may be formed, and for that purpose, a silicon target to which phosphorus (P) is added is used for film formation. Alternatively, a silicon target may be used for sputtering in an atmosphere containing phosphorus to form a film. Alternatively, the amorphous semiconductor film 106 containing an impurity element imparting n-type conductivity may be formed using a hydrogenated microcrystalline silicon film (μc-Si: H).

Next, a conductive metal film 107 is formed by a sputtering method or a vacuum evaporation method. The material of the conductive metal film 107 is not particularly limited as long as it is a metal material capable of making ohmic contact with the n ⁺ a-Si film 106, and Al, C
Examples include an element selected from r, Ta, and Ti, an alloy containing the above element, an alloy film in which the above elements are combined, and the like. However, as the conductive metal film 107, it is necessary to select one having a sufficient selection ratio with respect to the terminal and the gate wiring in a later etching step. In this example, a sputtering method was used to form a Cr film with a thickness of 300 to 600 nm as the metal film 107 (FIG. 2A).

The insulating film 104, the amorphous semiconductor film 105, the semiconductor film 106 containing an impurity element of one conductivity type, and the conductive metal film 107 are all manufactured by known methods, and the plasma CVD method is used. Or a sputtering method. In this embodiment, the sputtering method is used, and the target and the sputtering gas are switched appropriately to form continuously. At this time, in the sputtering apparatus, it is preferable to use the same reaction chamber or a plurality of reaction chambers and stack these films continuously without exposing them to the atmosphere. In this way, by not exposing to the atmosphere, it is possible to prevent the mixing of impurities.

Next, a second photolithography process is performed to form resist masks 108 and 109, and unnecessary portions are removed by etching to remove insulating films 110 and 11.
1. Form wiring and electrodes (source wiring). Wet etching or dry etching is used as an etching method at this time. By the second photolithography step, the insulating film 104, the amorphous semiconductor film 105, the semiconductor film 106 containing an impurity element of one conductivity type, and the conductive metal film 107 are etched, so that the pixel TFT portion is insulated. A film 110, an amorphous semiconductor film 112, a semiconductor film 114 containing an impurity element of one conductivity type, and a conductive metal film 116 are formed. Therefore, the end faces of these films are substantially coincident with each other. In addition, in the capacitor portion, the insulating film 11
1, an amorphous semiconductor film 113, a semiconductor film 115 containing an impurity element of one conductivity type, and a conductive metal film 117 are formed. Similarly, the end faces of these membranes are coincident.

In the second photolithography step, the terminal portion is etched leaving only the terminal 101. Further, the insulating film on the gate wiring is removed leaving only the intersection with other wiring. Therefore, terminal 1
01 and the material of the gate wiring and the insulating film must have a sufficient selection ratio, and the material of the terminal and the conductive metal film must also have a sufficient selection ratio. That is, it is necessary to select a material different from the material of the terminal and the gate wiring and the conductive metal film. In this embodiment, the metal film 107 is etched by dry etching using a mixed gas of Cl ₂ and O ₂ , and the reaction gas is replaced with the mixed gas of CF ₄ and O ₂ and a semiconductor containing an impurity element of one conductivity type is used. The film 106, the amorphous semiconductor film 105, and the insulating film 104 were selectively removed (FIG. 2B).

Next, after removing the resist mask 108, a transparent conductive film 118 is formed on the entire surface (FIG. 2).
(C)). A top view at this time is shown in FIG. However, the transparent conductive film 118 formed on the entire surface is not shown in FIG. 5 for simplification.

The material of the transparent conductive film 118 is indium oxide (In ₂ O ₃ ) or indium oxide-tin oxide alloy (I
n ₂ O ₃ —SnO ₂ , abbreviated as ITO) or the like is formed by using a sputtering method, a vacuum evaporation method or the like. The etching treatment of such a material is performed with a hydrochloric acid-based solution. But,
In particular, when ITO is etched, a residue is likely to be generated. Therefore, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium oxide-zinc oxide alloy is excellent in surface smoothness and thermal stability as compared with ITO, the electrode 116 to be contacted is
Even if is formed of an Al film, it is possible to prevent the corrosion reaction. Similarly, zinc oxide (ZnO) is a suitable material,
Further, zinc oxide (ZnO: Ga) to which gallium (Ga) is added can be used in order to increase visible light transmittance and conductivity.

Next, a third photolithography process is performed to form resist masks 119, 120 and 121, and unnecessary portions are removed by etching to remove the amorphous semiconductor film 122, the source region 123 and the drain region 12.
4, the source electrode 125, the drain electrode 126, and the pixel electrode 127 are formed (FIG. 2D).

The third photolithography step is
At the same time as patterning the transparent conductive film 118, a part of the conductive metal film 116, the n ⁺ a-Si film 114, and the amorphous semiconductor film 112 is removed by etching to form an opening. In this embodiment, first, the pixel electrode made of ITO is selectively removed by wet etching using a mixed solution of nitric acid and hydrochloric acid or a ferric chloride-based solution,
Metal film 116 having conductivity by wet etching
Then, the n ⁺ a-Si film 114 and a part of the amorphous semiconductor film 112 were etched by dry etching. Although wet etching and dry etching are used in the present embodiment, the practitioner may appropriately select a reaction gas and perform only dry etching, or the practitioner may select a reaction solution and perform wet etching. You may go alone.

The bottom of the opening reaches the amorphous semiconductor film, and an amorphous semiconductor film 114 having a recess is formed. Due to this opening, the conductive metal film 116 is separated into the source electrode 125 and the drain electrode 126, and n ⁺
The a-Si film 114 includes the source region 123 and the drain region 1.
It is separated into 24. Further, the transparent conductive film 128 in contact with the source electrode 125 covers the source wiring,
In particular, it plays the role of preventing static electricity generated in the rubbing process. Although the transparent conductive film 128 is formed on the source wiring in the present embodiment, the transparent conductive film 128 may be removed when the ITO film is etched. In addition, the above IT
When the O film is etched, the ITO film may be used to form a circuit for protecting it from static electricity.

Although not shown, since the transparent conductive film formed on the gate wiring by the third photolithography step is selectively removed, the gate wiring is selected from the amorphous semiconductor film and the metal film 116. A ratio is needed. However, the transparent conductive film is partially left on the gate wiring terminal portion.

Next, the resist masks 119 to 121 were removed. A cross-sectional view of this state is shown in FIG. Note that FIG. 1 is a top view of one pixel, and cross-sectional views taken along lines AA ′ and BB ′ correspond to FIG. 3A, respectively.

Further, FIG. 9A shows a top view of the gate wiring terminal portion 501 and the source wiring terminal portion 502 in this state, respectively. The same reference numerals are used for the parts corresponding to those in FIGS. Further, FIG. 9B corresponds to a cross-sectional view taken along lines EE ′ and FF ′ in FIG. 9A. In FIG. 9A, a transparent conductive film 503 is an electrode for connection which functions as an input terminal.
In FIG. 9B, 504 is an insulating film (extending from 110), 505 is an amorphous semiconductor film (extending from 122), and 506 is an n ⁺ a-Si film (extending from 123). ).

In the capacitor portion, the insulating film 111 serves as a dielectric, and the capacitor wire 103 and the metal film 117 (or the n ⁺ a-Si film 115 or the semiconductor film) form a storage capacitor.

In this way, the pixel TFT section having the inverted stagger type n-channel TFT 201 and the storage capacitor 202 can be completed by using the three photomasks by the three photolithography steps. By arranging these in a matrix corresponding to individual pixels to form a pixel portion, one substrate for manufacturing an active matrix liquid crystal display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

Next, the alignment film 130 is selectively formed only on the pixel portion of the active matrix substrate. Alignment film 130
As a method for selectively forming, a screen printing method may be used, or a method of forming a resist mask by using a shadow mask and then removing after applying an alignment film may be used. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element.

Next, the alignment film 130 is subjected to rubbing treatment so that liquid crystal molecules are aligned with a certain pretilt angle.

Then, the counter substrate 1 provided with the active matrix substrate, the counter electrode 132 and the alignment film 131.
33 and 33 are bonded together with a sealant while maintaining the substrate distance by a spacer, and then a liquid crystal material 134 is injected between the active matrix substrate and the counter substrate. Liquid crystal material 134
A known material may be applied as the material, and TN liquid crystal is typically used. After injecting the liquid crystal material, the injection port is sealed with a resin material.

Next, a flexible printed circuit (FPC) is attached to the terminal 101 of the terminal portion.
Connect. The FPC has a copper wiring 137 formed on an organic resin film 138 such as polyimide, and is connected to an input terminal 129 (corresponding to 503 in FIG. 9) made of a transparent conductive film with an anisotropic conductive adhesive. The anisotropic conductive adhesive is an adhesive 135 and particles 136 having a conductive surface with a diameter of several tens to several hundreds μm mixed therein and plated with gold or the like.
The particles 136 come into contact with the input terminal 129 and the copper wiring 137 to form an electrical contact at this portion. Further, a resin layer 139 is provided to increase the mechanical strength of this portion (FIG. 3 (B)).

FIG. 6 is a diagram for explaining the arrangement of the pixel portion and the terminal portion of the active matrix substrate. A pixel portion 211 is provided on the substrate 210, and a gate wiring 208 is provided in the pixel portion.
And a source wiring 207 are formed so as to intersect with each other, and an n-channel TFT 201 connected to the source wiring 207 is provided corresponding to each pixel. The pixel electrode 127 and the storage capacitor 202 are connected to the drain side of the n-channel TFT 201, and the other terminal of the storage capacitor 202 is connected to the capacitor wiring 209. The structures of the n-channel TFT 201 and the storage capacitor 202 are the same as those of the n-channel TFT 201 and the storage capacitor 202 shown in FIG.

An input terminal portion 205 for inputting a scanning signal is formed at one end of the substrate and is connected to a gate wiring 208 by a connection wiring 206. In addition, an input terminal portion 203 for inputting an image signal is formed at the other end portion and is connected to a source wiring 207 by a connection wiring 204. Gate wiring 208, source wiring 207, capacitance wiring 2
A plurality of 09 are provided according to the pixel density.
The number is as described above. Alternatively, an input terminal portion 212 for inputting an image signal and a connection wiring 213 may be provided, and the input terminal portion 203 may be alternately connected to the source wiring. The input terminal portions 203, 205, and 212 may be provided in arbitrary numbers, and may be appropriately determined by the practitioner.

[Embodiment 2] FIG. 7 shows an example of a method of mounting a liquid crystal display device. In the liquid crystal display device, an input terminal portion 302 is formed at an end portion of a substrate 301 on which a TFT is formed, and this is formed by a terminal 303 formed of the same material as the gate wiring as shown in the first embodiment. . And the counter substrate 30
4 and the spacer 306 are attached by a sealant 305, and polarizing plates 307 and 308 are further provided. Then, it is fixed to the housing 321 by the spacer 322.

The TFT having the active layer formed of the amorphous silicon film obtained in Example 1 has a small field effect mobility, and only about 1 cm ² / Vsec is obtained. Therefore, a drive circuit for displaying an image is formed of an LSI chip, and a TAB (tape automated bonding) method or a CO method is used.
It is mounted by the G (chip on glass) method. In this embodiment, a drive circuit is formed on the LSI chip 313 and
An example of implementing the method is shown below. A flexible printed circuit (FPC) is used for this, and the FPC is an organic resin film 30 such as polyimide.
A copper wiring 310 is formed on the wiring 9 and is connected to the input terminal 302 with an anisotropic conductive adhesive. Input terminal is wiring 303
It is a transparent conductive film provided in contact with the top. The anisotropic conductive adhesive is composed of an adhesive 311 and particles 312 having a conductive surface with a diameter of several tens to several hundreds of μm mixed therein and plated with gold or the like.
By making contact with 2 and the copper wiring 310, an electrical contact is formed at this portion. A resin layer 318 is provided to increase the mechanical strength of this portion.

The LSI chip 313 is connected to the copper wiring 310 with bumps 314 and is sealed with a resin material 315.
The copper wiring 310 is connected to a printed circuit board 317 on which other signal processing circuits, amplifier circuits, power supply circuits, etc. are formed at connection terminals 316. In the transmissive liquid crystal display device, the light source 319 and the light guide 32 are provided on the counter substrate 304.
0 is provided and used as a backlight.

[Embodiment 3] In this embodiment, an example of forming a protective film is shown in FIG. The present embodiment is the same up to the state of FIG. 2D of the first embodiment, and therefore the different points will be described below. In addition, the same reference numerals are used for the portions corresponding to FIG.

First, after obtaining the state of FIG. 2D according to the first embodiment, a thin inorganic insulating film is formed on the entire surface. As the thin inorganic insulating film, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a tantalum oxide film may be used, and may be formed as a single layer or a laminated structure made of these materials.

Next, a fourth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching, and the insulating film 4 is formed in the pixel TFT portion.
02, the inorganic insulating film 401 is formed in each terminal portion. The inorganic insulating films 401 and 402 function as a passivation film. Further, in the terminal portion, the thin inorganic insulating film 4 is formed by the fourth photolithography process.
01 is removed to expose the terminal 101 of the terminal portion.

In this way, in this embodiment, the reverse stagger type n-channel TFT protected by the inorganic insulating film and the storage capacitor can be completed by using four photomasks by four photolithography steps. it can. And
Arrange these in a matrix corresponding to each pixel,
By forming the pixel portion, the substrate can be used as one substrate for manufacturing an active matrix liquid crystal display device.

It should be noted that this embodiment can be freely combined with the configuration of the first or second embodiment.

[Embodiment 4] In Embodiment 1, an example is shown in which an insulating film, an amorphous semiconductor film, an amorphous semiconductor film containing an impurity element imparting n-type conductivity, and a metal film are laminated by a sputtering method. However, in this embodiment, an example using the plasma CVD method is shown.

In this embodiment, an insulating film, an amorphous semiconductor film,
And an amorphous semiconductor film containing an impurity element imparting n-type conductivity were formed by a plasma CVD method.

In this embodiment, a silicon oxynitride film is used as the insulating film and is formed by plasma CVD to a thickness of 150 nm. At this time, in the plasma CVD apparatus,
Power frequency 13-70MHz, preferably 27-60M
It may be performed in Hz. By using a power supply frequency of 27 to 60 MHz, a dense insulating film can be formed and the breakdown voltage as a gate insulating film can be increased. Also, Si
Since the silicon oxynitride film produced by adding O ₂ to H ₄ and N ₂ O has a reduced fixed charge density in the film,
It is the preferred material for this application. Of course, the gate insulating film is not limited to such a silicon oxynitride film, and other insulating films such as a silicon oxide film, a silicon nitride film, and a tantalum oxide film may be used, and a single layer or a laminated layer made of these materials may be used. It may be formed as a structure. Further, a laminated structure in which the lower layer is a silicon nitride film and the upper layer is a silicon oxide film may be used.

For example, when a silicon oxide film is used, plasma CVD is used to mix tetraethyl orthosilicate (TEOS) and O ₂ at a reaction pressure of 40 Pa, a substrate temperature of 250 to 350 ° C., and a high frequency ( 13.56MHz) Power density 0.5-0.8W
It can be formed by discharging at / cm ² . The silicon oxide film produced in this way is then 300-400.
Good characteristics as a gate insulating film can be obtained by thermal annealing at ℃.

As the amorphous semiconductor film, hydrogenated amorphous silicon (a-S) is typically used by the plasma CVD method.
The i: H) film is formed to a thickness of 100 nm. At this time, in the plasma CVD apparatus, the power supply frequency is 13 to 70 MH
z, preferably 27 to 60 MHz. By using a power supply frequency of 27 to 60 MHz, the film formation rate can be improved, and the formed film is an a-Si film having a low defect density, which is preferable. In addition, a compound semiconductor film having an amorphous structure such as a microcrystalline semiconductor film or an amorphous silicon germanium film can be applied to this amorphous semiconductor film.

Further, in forming the insulating film and the amorphous semiconductor film by the plasma CVD method, 100 to 10
The pulse-modulated discharge of 0 kHz is preferable because generation of particles due to a gas phase reaction of a plasma CVD method can be prevented and generation of pinholes can be prevented in film formation.

Further, in this embodiment, one conductivity type impurity source is used.
As a semiconductor film containing an element, an impurity element imparting n-type
Forming an amorphous semiconductor film containing element with a thickness of 20 to 80 nm
To do. For example, it is sufficient to form an n-type a-Si: H film.
Therefore, silane (SiH _Four) To 0.1-5
Phosphine (PH₃) Is added. Some
Is an amorphous semiconductor film 1 containing an impurity element imparting n-type
06 is a hydrogenated microcrystalline silicon film (μc-Si: H)
You can do it.

These films can be continuously formed by appropriately switching the reaction gas. Further, in the plasma CVD apparatus, the same reaction chamber or a plurality of reaction chambers may be used, and these films may be continuously laminated without being exposed to the atmosphere. Thus, by continuously forming a film without exposing it to the air, impurities can be prevented from entering the amorphous semiconductor film.

It should be noted that this embodiment can be combined with the second embodiment.

[Fifth Embodiment] In the first or fourth embodiment, an example is shown in which an insulating film, an amorphous semiconductor film, an n ⁺ a-Si film, and a metal film are sequentially and continuously laminated. An example of an apparatus having a plurality of chambers used in the case of continuously forming a film is shown in FIG.

FIG. 10 shows an outline of the apparatus (continuous film forming system) shown in this embodiment as seen from the upper surface. In FIG.
10 to 15 are airtight chambers. A vacuum exhaust pump and an inert gas introduction system are arranged in each chamber.

The chambers 10 and 15 are load lock chambers for loading the sample (process substrate) 30 into the system. Reference numeral 11 is a first chamber for forming the insulating film 104. Reference numeral 12 is a second chamber for forming the amorphous semiconductor film 105. Reference numeral 13 is a third chamber for forming the amorphous semiconductor film 106 that imparts n-type conductivity. Reference numeral 14 is a fourth chamber for forming the metal film 107. Further, reference numeral 20 is a common chamber for samples which is commonly arranged for each chamber.

An example of the operation will be shown below.

Initially, all the chambers are once evacuated to a high vacuum state and then are further purged with an inert gas, here, nitrogen (normal pressure). Also,
All gate valves 22 to 27 are closed.

First, the processed substrate is loaded into the load lock chamber 10 together with the cassette 28 containing a large number of substrates. After loading the cassette, the door of the load lock chamber (not shown) is closed. In this state, the gate valve 22 is opened, one processing substrate 30 is taken out from the cassette, and the robot arm 21
To the common chamber 20 by. At this time, the alignment is performed in the common room. The substrate 30 used had the wirings 101, 102, 103 obtained according to the first embodiment.

Here, the gate valve 22 is closed, and then the gate valve 23 is opened. Then, the processing substrate 30 is transferred to the first chamber 11. 150 ° C in the first chamber
To 300 ° C., the insulating film 104 is obtained. As the insulating film, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, a laminated film of these, or the like can be used. Although a single-layer silicon nitride film is used in this embodiment, it may have a laminated structure of two layers or three layers or more. Although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.

After the insulating film is formed, the processing substrate is pulled out to the common chamber by the robot arm and transferred to the second chamber 12. Similar to the first chamber, the film formation process is performed in the second chamber at a temperature of 150 ° C. to 300 ° C., and the amorphous semiconductor film 105 is obtained by the plasma CVD method. Note that as the amorphous semiconductor film, a microcrystalline semiconductor film,
An amorphous germanium film, an amorphous silicon germanium film, a laminated film of these, or the like can be used.
Further, the formation temperature of the amorphous semiconductor film is set to 350 ° C to 500 ° C.
As a result, the heat treatment for reducing the hydrogen concentration may be omitted. Although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.

After the formation of the amorphous semiconductor film, the processed substrate is pulled out to the common chamber and transferred to the third chamber 13. An impurity element (P or As) that imparts n-type by plasma CVD is performed in the third chamber at a temperature of 150 ° C. to 300 ° C. as in the second chamber.
An amorphous semiconductor film 106 containing is obtained. Although a chamber capable of plasma CVD is used here, a chamber capable of sputtering using a target may be used.

After the formation of the amorphous semiconductor film containing the impurity element imparting n-type conductivity, the processed substrate is taken out to the common chamber,
Transferred to the fourth chamber 14. In the fourth chamber, the metal film 10 is formed by a sputtering method using a metal target.
Get 7.

The substrate to be processed on which four layers are continuously formed in this manner is loaded by the robot arm into the load lock chamber 1.
5, and is stored in the cassette 29.

Needless to say, the device shown in FIG. 10 is merely an example. Further, it is necessary to freely combine this embodiment with any one of Embodiments 1 to 4.

[Sixth Embodiment] In the fifth embodiment, an example in which a plurality of chambers are used to continuously stack layers is shown. However, in this embodiment, the apparatus shown in FIG. Was continuously laminated while maintaining the above.

In this example, the apparatus system shown in FIG. 11 was used. In FIG. 11, reference numeral 40 is a processing substrate, 50 is a common chamber, 44 and 46 are load lock chambers, 45 is a chamber, and 42 and 43 are cassettes. In this embodiment, the layers are formed in the same chamber in order to prevent contamination that occurs when the substrate is transported.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

However, in the case of being applied to the first embodiment, a plurality of targets are prepared in the chamber 45, and the reaction gas is sequentially changed to the insulating film 104 and the amorphous semiconductor film 10.
5, amorphous semiconductor film 1 containing an impurity element imparting n-type
06 and the metal film 107 may be laminated.

However, in the case of being applied to the third embodiment, the insulating gas 104, the amorphous semiconductor film 105, and the amorphous semiconductor film 106 containing the impurity element imparting n-type are sequentially stacked by changing the reaction gas. It may be formed.

[Embodiment 7] In Embodiment 1, n ⁺ a-Si
Although an example in which the film is formed by the sputtering method is shown, this example shows an example in which the film is formed by the plasma CVD method. Since this example is the same as example 1 except for the method of forming the n ⁺ a-Si film, only different points will be described below.

An n ⁺ a-Si film can be obtained by adding phosphine (PH ₃ ) at a concentration of 0.1 to 5% to silane (SiH ₄ ) as a reaction gas using the plasma CVD method. .

[Embodiment 8] In Embodiment 7, n ⁺ a-Si
Although an example in which the film is formed by a plasma CVD method is shown, this example shows an example in which a microcrystalline semiconductor film containing an impurity element imparting n-type conductivity is used.

The formation temperature is 80 to 300 ° C., preferably 1
Silane gas (Si
_{H 4: H 2 = 1:} 10~100) and phosphine (P
H ₃ ) mixed gas is used as a reaction gas, and the gas pressure is 0.1 to
A microcrystalline silicon film can be obtained by setting the discharge power to 10 Torr and the discharge power to 10 to 300 mW / cm ² . In addition, phosphorus may be plasma-doped after the formation of the microcrystalline silicon film.

[Embodiment 9] FIG. 12 is a diagram schematically showing how a liquid crystal display device is assembled using the COG method. A pixel region 803, an external input / output terminal 804, and a connection wiring 805 are formed on the first substrate. The area surrounded by the dotted line is the IC chip bonding area 80 on the scanning line side.
1 and an IC chip bonding area 802 on the data line side. A counter electrode 809 is formed on the second substrate 808,
The sealing material 810 is attached to the first substrate 800. Liquid crystal is enclosed inside the sealant 810 to form a liquid crystal layer 811. The first substrate and the second substrate are attached to each other with a predetermined gap, but in the case of nematic liquid crystal, 3 to 8
μm, and 1 to 4 μm in the case of smectic liquid crystal.

The IC chips 806 and 807 have different circuit configurations on the data line side and the scanning line side. The IC chip is mounted on the first substrate. The external input / output terminal 804 is an FPC (Flexible Printed Circuit) 812 for inputting power and control signals from the outside.
Paste. A reinforcing plate 813 may be provided to increase the adhesive strength of the FPC 812. Thus, the liquid crystal display device can be completed. If the IC chip is electrically inspected before being mounted on the first substrate, the yield in the final process of the liquid crystal display device can be improved and the reliability can be improved.

As a method of mounting the IC chip on the first substrate, a connection method using an anisotropic conductive material, a wire bonding method, or the like can be adopted. FIG. 13 shows an example thereof. FIG. 13A shows an IC on the first substrate 901.
An example in which the chip 908 is mounted using an anisotropic conductive material is shown. A pixel region 902, a lead wire 906, a connection wiring, and an input / output terminal 907 are provided over the first substrate 901. The second substrate is the sealant 904 and the first substrate 901.
And a liquid crystal layer 905 is provided between them.

An FPC 912 is bonded to one end of the connection wiring and the input / output terminal 907 with an anisotropic conductive material. The anisotropic conductive material is composed of a resin 915 and conductive particles 914 having a diameter of several tens to several hundreds μm and having a surface plated with Au or the like.
07 and the wiring 913 formed on the FPC 912 are electrically connected. Similarly, the IC chip 908 is also bonded to the first substrate with an anisotropic conductive material, and the conductive particles 910 mixed in the resin 911 are used to connect the input / output terminal 909 provided on the IC chip 908 to the lead wire 906 or connection. The wiring and the input / output terminal 907 are electrically connected.

Further, as shown in FIG. 13B, the IC chip is fixed to the first substrate with the adhesive 916, and the Au wire 917 connects the input / output terminal of the stick driver to the lead wire or the connection wiring. May be. And resin 918
Seal with.

The IC chip mounting method is shown in FIGS.
The method is not limited to the above-described method, and a known COG method, wire bonding method, or TAB method other than those described here can be used.

This embodiment can be combined with the first embodiment.

[Embodiment 10] In Embodiment 1, a method of manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device was shown. In this embodiment, FIG. 14 is used and the method is applied to a reflective liquid crystal display device. An example is shown.

First, as in the first embodiment, as shown in FIG.
The steps up to are shown. Then, an interlayer insulating film made of an organic resin film is formed. Next, the interlayer insulating film is roughened to form an interlayer insulating film 601 having a concave and convex portion. As the unevenness treatment, a method of applying an organic resin film containing fibers or spacers may be used, or a method of partially etching the organic resin film using a mask may be used. Alternatively, a method may be used in which the photosensitive resin is etched into a columnar shape using a mask, and then heated and reflowed.

Next, a contact hole reaching the source wiring and the drain electrode is formed in the interlayer insulating film 601 by the third photolithography process. Further, in the same step, a contact hole reaching the electrode is formed to form a storage capacitor, and the interlayer insulating film on the terminal portion is removed.

Then, a conductive film having reflectivity (Al, A
g)).

Then, a resist mask pattern is formed by a fourth photolithography process, and a pixel electrode 602 made of a conductive film having reflectivity is formed by etching. The pixel electrode 602 formed in this manner has a concavo-convex portion, can scatter light, and can prevent mirroring. At the same time, the lead wiring 603 reaching the source electrode is formed.

Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted. Thus, the active matrix substrate corresponding to the reflective liquid crystal display device can be manufactured by using the four photomasks by the four photolithography steps.

Further, this embodiment is the same as the second or third embodiment.
Can be combined with.

[Embodiment 11] The CMOS circuit and the pixel portion formed by implementing the present invention can be used in various electro-optical devices (active matrix type liquid crystal display, active matrix type EC display). That is, the invention of the present application can be implemented in all electronic devices in which the electro-optical device is incorporated in the display section.

Examples of such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, car stereos,
Examples thereof include personal computers and personal digital assistants (mobile computers, mobile phones, electronic books, etc.). Examples of those are shown in FIGS. 15, 16 and 17.

FIG. 15A shows a personal computer, which has a main body 2001, an image input section 2002, and a display section 20.
03, keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal drive circuits.

FIG. 15B shows a video camera, which includes a main body 2101, a display portion 2102, a voice input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
Including 6 etc. The present invention can be applied to the display portion 2102 and other signal driver circuits.

FIG. 15C shows a mobile computer (mobile computer), which includes a main body 2201, a camera portion 2202, an image receiving portion 2203, operation switches 2204, a display portion 2205, and the like. The present invention can be applied to the display portion 2205 and other signal driving circuits.

FIG. 15D shows a goggle type display, which includes a main body 2301, a display portion 2302 and an arm portion 230.
Including 3 etc. The present invention can be applied to the display portion 2302 and other signal driving circuits.

FIG. 15E shows a player using a recording medium (hereinafter, referred to as a recording medium) in which a program is recorded, which is a main body 2401, a display section 2402 and a speaker section 240.
3, a recording medium 2404, operation switches 2405 and the like. This player uses a DVD (D
optical Versatile Disc), CD
It is possible to play music, watch movies, play games, and use the internet. The present invention can be applied to the display portion 2402 and other signal driving circuits.

FIG. 15F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown) and the like. The present invention can be applied to the display section 2502 and other signal drive circuits.

FIG. 16A shows a front type projector including a projection device 2601, a screen 2602 and the like. The present invention can be applied to the liquid crystal display device 2808 which constitutes a part of the projection device 2601 and other signal drive circuits.

FIG. 16B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, screen 2704 and the like. The present invention is a projection device 2
The present invention can be applied to the liquid crystal display device 2808 which forms a part of 702 and other signal driving circuits.

Note that FIG. 16C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 16A and 16B. Projection device 2601, 27
02 is a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280.
9, a projection optical system 2810. Projection optical system 28
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference, and an IR film in the optical path indicated by the arrow in FIG. 16C. Good.

FIG. 16D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 16C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813, and a lens array 2813.
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 16D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, the projector shown in FIG. 16 shows a case where a transmissive electro-optical device is used, and an application example of a reflective electro-optical device is not shown.

FIG. 17A shows a mobile phone, which is a main body 29.
01, voice output unit 2902, voice input unit 2903, display unit 2904, operation switch 2905, antenna 2906
Including etc. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal drive circuits.

FIG. 17B shows a portable book (electronic book) including a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006.
Including etc. The present invention can be applied to the display portions 3002 and 3003 and other signal circuits.

FIG. 17C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103 and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when it has a large screen, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic device of the present embodiment can be realized by using a configuration including any combination of the first to tenth embodiments.

[0148]

According to the present invention, a liquid crystal display device having a pixel TFT section having an inverted stagger type n-channel TFT and a storage capacitor by using three photomasks by three photolithography processes. Can be realized.

When a protective film is formed,
A liquid crystal display device including a pixel TFT section having an inverted stagger type n-channel TFT protected by an inorganic insulating film and a storage capacitor by using four photomasks by four photolithography steps. can do.

[Brief description of drawings]

FIG. 1 is a diagram showing a top view of the present invention.

2A to 2C are cross-sectional views illustrating a manufacturing process of an AM-LCD.

FIG. 3 is a cross-sectional view showing a manufacturing process of an AM-LCD.

FIG. 4 is a top view illustrating a manufacturing process of an AM-LCD.

FIG. 5 is a top view illustrating a manufacturing process of an AM-LCD.

FIG. 6 is a top view illustrating an arrangement of a pixel portion and an input terminal portion of a liquid crystal display device.

FIG. 7 is a sectional view showing a mounting structure of a liquid crystal display device.

FIG. 8 is a cross-sectional view showing a manufacturing process of an AM-LCD.

9A and 9B are a top view and a cross-sectional view of an input terminal portion.

FIG. 10 is a top view of the manufacturing apparatus.

FIG. 11 is a top view of the manufacturing apparatus.

FIG. 12 is a diagram showing mounting of a liquid crystal display device.

FIG. 13 is a sectional view showing a mounting structure of a liquid crystal display device.

FIG. 14 is a structural cross-sectional view of an active matrix substrate.

FIG. 15 illustrates examples of electronic devices.

FIG. 16 illustrates an example of an electronic device.

FIG. 17 illustrates an example of an electronic device.

Continued front page    F-term (reference) 2H092 GA48 GA50 GA59 GA60 JA26                       JA28 JB57 JB69 MA05 MA08                       MA14 NA27 RA05 RA10                 5F110 AA16 BB04 CC07 DD01 DD02                       DD03 EE01 EE02 EE03 EE04                       EE06 EE09 EE14 EE15 EE23                       EE44 FF01 FF02 FF03 FF04                       FF09 FF28 GG01 GG02 GG03                       GG14 GG15 GG25 GG43 GG45                       HK03 HK04 HK06 HK07 HK09                       HK22 HK32 HK33 HK35 NN02                       NN03 NN22 NN23 NN24 NN72                       NN73 PP35 QQ04 QQ09

Claims (4)

[Claims] 1. A pixel portion having a thin film transistor, a gate wiring connected to the thin film transistor, a source wiring, and a pixel electrode, a first terminal electrically connected to the gate wiring of the pixel portion, and the source wiring. A method of manufacturing a semiconductor device, comprising: forming a terminal portion having a second terminal electrically connected on the same substrate, wherein the gate wiring and the first terminal are formed on the substrate; An insulating film is formed on the first terminal, an amorphous first semiconductor film is formed on the insulating film, and a second conductivity type impurity-containing second film is formed on the first semiconductor film. Forming a semiconductor film, forming a first conductive film on the second semiconductor film, using a first mask, the first conductive film, the second semiconductor film, the first semiconductor film And etching the insulating film, A first laminated film including the first conductive film, the second semiconductor film, the first semiconductor film, and the insulating film is formed to expose the surface of the first terminal, As a terminal of the second conductive film, the second conductive film, the second semiconductor film, the first semiconductor film, and the second insulating film.
And forming a second conductive film and etching the second conductive film and the first stacked film using a second mask. An opening is formed in the first conductive film to separate the first conductive film into a drain electrode and a source wiring, and the second semiconductor film into a region below the drain electrode and a region below the source wiring. To form a recess in the first semiconductor film,
And a conductive film that covers the first terminal and the pixel electrode on the drain electrode is formed by the second conductive film. Method. 2. A pixel portion having a thin film transistor, a gate wiring connected to the thin film transistor, a source wiring, and a pixel electrode, a first terminal electrically connected to the gate wiring of the pixel portion, and the source wiring. A method of manufacturing a semiconductor device, comprising: forming a terminal portion having a second terminal electrically connected on the same substrate, wherein the gate wiring and the first terminal are formed on the substrate; An insulating film is formed on the first terminal, an amorphous first semiconductor film is formed on the insulating film, and a second conductivity type impurity-containing second film is formed on the first semiconductor film. Forming a semiconductor film, forming a first conductive film on the second semiconductor film, using a first mask, the first conductive film, the second semiconductor film, the first semiconductor film And etching the insulating film to form the pixel And a first portion formed of the first conductive film, the second semiconductor film, the first semiconductor film, and the insulating film.
A laminated film is formed to expose the first terminal, and the second terminal is formed of the first conductive film, the second semiconductor film, the first semiconductor film, and the insulating film. A second laminated film is formed, the insulating film is selectively removed to expose the surface of the first terminal, a second conductive film is formed, and a second mask is used to form the second film. Etching the conductive film and the first laminated film to form an opening in the first laminated film to separate the first conductive film into a drain electrode and a source wiring; The second semiconductor film is divided into a region below the drain electrode and a region below the source wiring, and a recess is formed in the first semiconductor film;
The conductive film on the drain electrode, the conductive film on the source wiring, and the first conductive film,
And a conductive film covering the second terminal are formed of the second conductive film. 3. The insulating film according to claim 1,
The first semiconductor film, the second semiconductor film, and the first semiconductor film.
2. The method for manufacturing a semiconductor device, characterized in that each of the conductive films is continuously formed without exposing the formation surface to the atmosphere. 4. The insulating film according to claim 1,
The first semiconductor film, the second semiconductor film, and the first semiconductor film.
2. The method for manufacturing a semiconductor device, characterized in that the conductive films are sequentially formed in the same chamber.