TW536655B - Liquid crystal display device - Google Patents
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- TW536655B TW536655B TW88113987A TW88113987A TW536655B TW 536655 B TW536655 B TW 536655B TW 88113987 A TW88113987 A TW 88113987A TW 88113987 A TW88113987 A TW 88113987A TW 536655 B TW536655 B TW 536655B
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五、發明說明(/ ) 、本發明是關於一種液晶顯示裝置,尤指一種低成本、 寬視角、w i質的大畫面主動式矩陣型液晶顯示裝置。 如第一、二圖所示,係習用液晶顯示裝置中主動式元 件基板的剖面圖。該習用的主動式矩陣式液晶顯示裝置在 形成主動式元件之-側的基板(1)㉟了周邊外,係在基 板(1)上全面沈積閘極絕緣膜(4)、半導體膜(5) y 6 )、護層膜(i 6 ),而在最先形成掃瞄線(2)的 製程中,Λ 了與驅動I C迴路接續,需要除去沈積於掃瞄 線端子部(3)上的閘極絕緣膜(4),另為了靜電對策 保濩電晶體之配線的接合,亦有必要除去閘極絕緣膜(4 如第一、二圖所示,以往ΤΝ*式的主動式元件基板 ,整個製程需要五次的光罩工程,而橫電場液晶方式之主 動式元件基板,整個製程也需要四次光罩工程。隨著液晶 顯示畫面的大型化,一片玻璃所能得到的液晶顯示元件數 目也相對減少,造成大型液晶顯示元件的價格變得非常的 鬲。且玻璃基板變大時所發生的靜電量也變得非常大,經 容易發生灰塵附著及靜電破壞的狀況,而降低了大型液晶 顯示元件的良率。 又光罩工程多時,昂貴的曝光裝置的數量需求增加, 初期投資的金額也相對提高,又因製造工廠的無塵室面積 變大,製造成本(RunningC〇st)也相對變大。且從投入玻 璃基板到完成主動式元件的時間如不儘可能的縮短,就會 需要大量的保管用倉庫。 3 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 536655 A7 B7 五、發明說明(丄) 再者,玻璃基板變大時,在以電漿化學氣相沈積(C v D )沈積SiNx膜、非晶矽半導體膜時,因膨脹係數與 玻璃基板相異之故,沈積後產生應力,造成基板整個扭曲 的問題。因為玻璃基板的中央部分與玻璃基板的周邊部分 的應力發生率不同,尺寸變化狀況在有效晝素區域全區域 不平均的出現,故光罩間有產生對位不良 (missalignment)的問題。 本發明主要在提供解決這些問題的手段,其目的在於 :提供一種可提高大型液晶顯示裝置製造工廠投資效率並 達成超大型、寬視角、低成本、高良率等功效的液晶顯示 裝置製造方法。 〔解決問題的手段〕 為解決前述問題及達成前述目的,本發明採用以下手 段: 該液晶顯示裝置包括有一主動式矩陣型基板、一與前 述主動式矩陣型基板成對向之對向基板、夾持於前述主動 式矩陣型基板與前述對向基板間的液晶層;其中:該主動 式矩陣型基板上分設有掃瞎信號配線及影像信號配線、於 前述掃瞄信號配線與影像信號配線的各交叉部上所形成的 薄膜電晶體、前述薄膜電晶體上所接續的畫素電極、至少 一部分與前述畫素電極呈相對方向構成的共通電極。 因此,本發明採取的手段丄,係於基板上沈積前述薄 膜電晶體元件的閘極絕緣膜時,僅部分的沈積在只含有效 畫素區域之局部,而薄膜電晶體元件的半導體層、護層膜 4 本紙張尺度過用T國國豕標準(CNS)A4規格(210 X 297公釐) ------1-----·!裝 (請先閱讀背面之注意事項5^寫本頁) I I I I 訂 — — — — — — — — 經濟部智慧財產局員工消費合作社印製 536655 A7 ~____________ 五、發明說明(j ) 保護膜層則在基板上全面沈積。 本發明採取的手段2,係於基板上沈積前述薄膜電晶 體几件的閘極絕緣膜及半導體層時,部分的沈積在僅含有 政晝素區域之部位,護層膜保護膜層則於基板上全面沈積 Ο 本發明採取的手段3,係前述薄膜電晶體元件的閘極 絕緣膜、護層膜保護膜層沈積在基板上時,局部的沈積在 僅含有效畫素區域之部位,半導體層則在基板上全面沈積 〇 本發明採取的手段4,在前述手段3所記載的製造方 法中,令護層膜沈積區域比部分沈積在僅含有效晝素區域 的閘極緣膜更廣。 本發明採取的手段5,係在基板上沈積前述薄膜電晶 體元件的閘極絕緣膜、半導體層及護層膜保護膜層時,部 分的沈積在僅含有效晝素區域之部位。 經濟部智慧財產局員工消費合作社印製 本發明採取的手段6,在前述手段5所記載的製造方 法中’令護層膜保護膜層沈積區域比部分沈積於僅含有效 晝素區域的閘極絕緣膜更廣。 本發明採取的手段7,在於根據本發明採取手段1〜 6所述製造方法製作的液晶顯示裝置,係將連結前述共通 電極與前述掃描線之靜電對策用保護電晶體元件、連結前 述共通電極與前述影像信號配線之靜電對策用保護電晶體 Κ牛等為護層膜保護膜層所完全覆蓋。 本發明採取的手段8,在於依手段1〜6所述製造方 _ 5 本紙張尺庋週用中國國家標準(CNS)A4規格(210 X 297公釐1 " " '—' 536655 A7 --------------- 五、發明說明(f) 法製造的液晶顯示裝置,係將連結前述共通電極與前述浐 t線之靜電對策用保護電晶體元件、連結前述共通電極: 刚述影像信號配線之靜電對策用保護電晶體元件配置在局 部性沈積之閘極絕緣膜境界周邊之兩邊以上。 σ 本發明採取的手段9,在於依手段i〜6所述製造方 法所製造的液晶顯示裝置,係將連結前述共通電極與前述 掃描線之靜電對策用保護主動式元件的接續部分、連結前 述共通電極與前述影像信號配線之靜電對策用保護主動式 π件的接續部分配置在局部性沈積之閘極絕緣膜的區域以 外。 本發明採取的手段1 〇,在於依手段i〜9所述製造 方法所製造的液晶顯示裝置,係將貼合二張基板形成液晶V. Description of the Invention (/) The present invention relates to a liquid crystal display device, in particular to a low-cost, wide viewing angle, large-screen active matrix liquid crystal display device of high quality. As shown in the first and second figures, it is a cross-sectional view of an active element substrate in a conventional liquid crystal display device. The conventional active matrix liquid crystal display device forms a gate insulating film (4) and a semiconductor film (5) on the substrate (1) on the substrate (1). y 6), protective film (i 6), and in the process of forming the scan line (2) first, Λ is connected to the drive IC circuit, and the gate deposited on the scan line terminal (3) needs to be removed Insulation film (4). In addition, in order to protect the connection of the wiring of the transistor with static electricity measures, it is necessary to remove the gate insulation film (4. As shown in the first and second figures, the conventional TN * type active element substrate, the entire The manufacturing process requires five mask processes, and the transverse field liquid crystal active element substrate also requires four mask processes. With the enlargement of the liquid crystal display screen, the number of liquid crystal display elements that can be obtained by one glass is also The relative decrease has caused the price of large-scale liquid crystal display elements to become very high. Moreover, the amount of static electricity that occurs when the glass substrate becomes large also becomes very large. The situation of dust adhesion and electrostatic damage is prone to reduce the large-scale liquid crystal display. element In the case of many photomask projects, the number of expensive exposure devices has increased, and the initial investment has also increased relatively. As the area of the clean room in the manufacturing plant has increased, the manufacturing cost (Running Cost) has also increased. . And if the time from the input of the glass substrate to the completion of the active components is not shortened as much as possible, a large number of storage warehouses will be required. 3 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 536655 A7 B7 V. Explanation of the invention (丄) Furthermore, when the glass substrate becomes larger, when the SiNx film and the amorphous silicon semiconductor film are deposited by plasma chemical vapor deposition (C v D), the expansion coefficient is different from that of the glass substrate. Therefore, stress is generated after deposition, which causes the entire substrate to be distorted. Because the stress occurrence rate of the central portion of the glass substrate and the peripheral portion of the glass substrate are different, the dimensional change occurs unevenly throughout the effective daylight region. There is a problem of misalignment between the hoods. The present invention is mainly to provide a solution to these problems, and the object thereof is to provide a method for improving Type liquid crystal display device manufacturing factory investment efficiency and a method for manufacturing a liquid crystal display device with ultra-large size, wide viewing angle, low cost, high yield, etc. [Means for Solving Problems] In order to solve the foregoing problems and achieve the foregoing objectives, the present invention adopts the following methods : The liquid crystal display device includes an active matrix substrate, an opposite substrate opposite to the active matrix substrate, and a liquid crystal layer sandwiched between the active matrix substrate and the opposite substrate; wherein: The active matrix substrate is provided with a scanning signal wiring and an image signal wiring, a thin film transistor formed on each intersection of the scanning signal wiring and the image signal wiring, and a picture connected to the thin film transistor. The pixel electrode and a common electrode having at least a part thereof facing the pixel electrode. Therefore, the method adopted in the present invention is that when the gate insulating film of the thin film transistor is deposited on a substrate, it is only partially deposited on a part containing only effective pixel regions, and the semiconductor layer and the protective layer of the thin film transistor are Laminated film 4 This paper has been used in the national standard (CNS) A4 specification (210 X 297 mm) ------ 1 ----- !! (Please read the precautions on the back 5 ^ (Write this page) IIII Order — — — — — — — — Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 536655 A7 ~ ____________ 5. Description of the invention (j) The protective film layer is fully deposited on the substrate. The method 2 adopted by the present invention is that when the gate insulating film and the semiconductor layer of the foregoing thin film transistors are deposited on the substrate, part of the film is deposited on the part containing only the daylight region, and the protective film layer is on the substrate. Fully deposited on the surface 0. The method 3 adopted by the present invention is the gate insulating film and the protective film of the thin film transistor element. When the protective film layer is deposited on the substrate, the semiconductor layer is locally deposited on a portion containing only effective pixel regions. Then, the substrate 4 is fully deposited. The method 4 adopted in the present invention, in the manufacturing method described in the aforementioned method 3, the area of the cover film deposition is wider than that of the gate edge film partially deposited on the region containing only effective daylight. The method 5 adopted in the present invention is to deposit the gate insulating film, the semiconductor layer, and the protective film protective film layer of the thin-film electric crystal element on the substrate, and the partial deposition is on the part containing only the effective daylight region. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the method 6 adopted by the present invention. In the manufacturing method described in the aforementioned method 5, 'make the protective film protective film deposition area more than partially deposited on the gate containing only the effective daylight region. Wider insulation film. Means 7 adopted by the present invention is that the liquid crystal display device manufactured by the manufacturing method according to Means 1 to 6 of the present invention is a protective transistor element for electrostatic countermeasures connecting the common electrode and the scanning line, and connects the common electrode and The aforementioned protective measures for the static electricity countermeasures of the video signal wiring are covered by a protective transistor, such as a protective film. The method 8 adopted by the present invention is the manufacturer according to the methods 1 to 6. _ 5 This paper is used in China National Standard (CNS) A4 size (210 X 297 mm 1 " " '—' 536655 A7- -------------- V. Description of the invention (f) The liquid crystal display device manufactured by the method is a protective transistor element for static electricity countermeasures connecting the common electrode and the 浐 t line, and connecting the foregoing. Common electrode: The protective transistor element for the electrostatic countermeasures of the video signal wiring just described is arranged at two or more sides around the boundary of the gate insulation film deposited locally. Σ Means 9 adopted by the present invention is the manufacturing method according to means i ~ 6 The manufactured liquid crystal display device is a connection part of a protection active element for electrostatic countermeasures connecting the common electrode and the scanning line, and a connection part of a protection active π element for electrostatic countermeasures connecting the common electrode and the video signal wiring. It is arranged outside the area where the gate insulating film is locally deposited. The means 10 adopted in the present invention is that the liquid crystal display device manufactured by the manufacturing method described in means i to 9 is to be bonded to two substrates. A liquid crystal
Cel 1的框膠線(seai)配置在局部性沈積的閘極絕緣膜周邊 境界上或閘極絕緣膜的區域以外,且位在護層膜沈積區域 以内。 本發明採取的手段11,在於使光罩的透光量有完全 透光、半透光及完全遮斷等三階段以上的變化,使正光阻 膜厚具有三階段以上的變化。 經濟部智慧財產局員工消費合作社印製 本發明採取的手段1 2,在於依手段1 1所記載的製 造方法’其掃瞄線、主動式元件的半導體區域、影像信號 配線及晝素電極等,令構成液晶顯示元件之各交叉電極、 相互重疊的段差部分光罩之透光量具有三階段以上的變化 ’而在正光阻顯影後,使光阻膜厚具有三階段以上的變化 〇 6 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 536655 A7 B7The frame rubber line (seai) of Cel 1 is arranged on the periphery of the gate insulating film which is locally deposited or outside the region of the gate insulating film, and is located within the region where the cover film is deposited. The method 11 adopted by the present invention is to change the light transmission amount of the photomask to three or more stages, such as complete light transmission, semi-light transmission, and full interruption, so that the positive photoresist film thickness has three or more stages. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the method 12 adopted by the present invention, which is based on the manufacturing method described in Method 11 'its scan line, the semiconductor area of the active element, the image signal wiring, and the day electrode, The light transmittance of each of the cross electrodes and the overlapping step masks constituting the liquid crystal display element is changed by more than three steps, and after the positive photoresist is developed, the photoresist film thickness is changed by more than three steps. Standards apply to China National Standard (CNS) A4 specifications (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 536655 A7 B7
五、發明說明(r) 本發明採取的手段1 3,在於依手段1 1所記載的方 法,增加連結影像信號配線及畫素電極的薄膜電晶體元件 通道部(Channel)光罩的透光量,當正光阻顯影後,使構 成薄膜電晶體元件的通道部(Channel)的正光阻膜厚變薄 〇 本發明採取的手段14,在於依手段3、4、5、β 或1 3所記載的方法,係將影像信號配線及晝素電極同時 分離形成’且除去通道部(Channel)的η+層,含此工程及 形成掃瞄線的光罩工程,以二次的光罩工程完成。 本發明採取的手段1 5,在於依手段1、2、1 3所 記載的方法,將影像信號配線及畫素電極同時形成,除去 通道部(Channel)的η+層後,於基板全面沈積護層膜,之 後開設與驅動ic回路接續之端子部接續洞(contacth〇le) 〇 本發明採取的手段1 6,在於依手段1 5所記載的方 法,令影像信號配線及汲極電極同時分別形成,並除去通 道部(Channel)的n+層後,於基板全面上沈積護層膜。之 後,同時形成與驅動1C回路接續之端子部接續洞 (Contacthole)及連結透明晝素電極與沒極電極之接續洞 (Contacthole),之後,沈積透明導電膜及形成畫素電極 與端子部電極。 本發明採取的手段1 7,在依手段3、4、5或6所 記載的方法,同時形成影像信號配線及晝素電極之後,除 去薄膜電晶體元件的通道部(Channel)的金屬膜及n+層,V. Description of the invention (r) Means 13 adopted by the present invention is to increase the light transmission amount of the channel mask of the thin film transistor element connecting the video signal wiring and the pixel electrode according to the method described in means 11. After the positive photoresist is developed, the thickness of the positive photoresist film constituting the channel portion of the thin film transistor element is reduced. The method 14 adopted in the present invention is the method described in the method 3, 4, 5, β, or 13 The method is to separate the image signal wiring and the day electrode at the same time to form the η + layer of the channel, and the mask process including this process and the formation of the scanning line is completed by a second mask process. Means 15 adopted in the present invention are to form the image signal wiring and the pixel electrode simultaneously according to the method described in means 1, 2, and 13. After removing the η + layer of the channel portion, the substrate is fully deposited and protected. Laminate a film, and then open a contact hole (contact hole) connected to the driver IC circuit. The method 16 adopted by the present invention is to form the image signal wiring and the drain electrode simultaneously according to the method described in the method 15. After removing the n + layer of the channel, a protective film is deposited on the entire surface of the substrate. After that, a contact hole for the terminal part connected to the driving 1C circuit and a contact hole for connecting the transparent day electrode and the non-electrode electrode are simultaneously formed, and then a transparent conductive film is deposited and the pixel electrode and the terminal electrode are formed. Means 17 adopted by the present invention, after the image signal wiring and the day electrode are formed simultaneously according to the method described in Means 3, 4, 5, or 6, the metal film and n + of the channel portion of the thin film transistor are removed. layer,
7 536655 A7 五、發明說明(厶 之後將護層膜保護膜局部的沈積在包含有效畫素區域之部 位上。 本發明採取的手段1 8,在依手段3、4、5或β所 5己載的方法,同時形成影像信號配線及汲極電極之後,沈 積透明導電膜,而在成形(Patterning)影像信號配線及畫 素電極時,除去薄膜電晶體元件的通道部(Channel)的金 屬膜及n+層,之後將護層膜保護膜局部的沈積在包含有效 晝素區域之部位上。 本發明採取的手段1 9,在依手段2、5或6所記載 的方法,將閘極絕緣膜局部的沈積在包含有效晝素區域之 P位上後,於基板的全面沈積半導體層,之後在同時形成 影像信號配線及畫素電極後,除去露出於表面的n+層,接 著將護層膜於基板上全面沈積或局部的沈積在包含有效晝 素區域之部位,之後為了形成薄膜電晶體元件的通道部 (Channel)及影像信號配線、畫素電極,除去多餘的護層 膜及半導體層。 本發明採取的手段2 0,在依手段丄、3或4所記載 的方法,將閘極絕緣膜局部的沈積在包含有效晝素區域之 部位上後,在基板的全面沈積半導體層,又在同時形成影 像信號配線及晝素電極之後,除去露出於表面的n+層,接 著,將遵層膜在基板上全面沈積或局部的沈積在包含有效 晝素區域之部位,之後除去多餘的護層膜及半導體層, 便形成薄膜電晶體元件的通道部(Channel)、影像信號 線、畫素電極。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)7 536655 A7 V. Description of the invention (After that, the protective film is partially deposited on the part containing the effective pixel area. Means taken by the present invention are 1 and 8. After the image signal wiring and the drain electrode are formed at the same time, a transparent conductive film is deposited. When the patterning of the image signal wiring and the pixel electrode is formed, the metal film and the channel portion of the thin film transistor are removed. n + layer, and then the protective film is partially deposited on the part containing the effective daylight region. Means 19 adopted in the present invention are to partially deposit the gate insulating film according to the method described in means 2, 5 or 6. After being deposited on the P site containing the effective daylight region, a semiconductor layer is deposited on the entire surface of the substrate, and after the image signal wiring and the pixel electrode are formed at the same time, the n + layer exposed on the surface is removed, and then a protective film is deposited on the substrate Fully or partially deposited on the part containing the effective daylight region, and in order to form the channel part of the thin film transistor element, the image signal wiring, and the pixel electrode, many The protective film and semiconductor layer of the present invention. In the method 20 adopted in the present invention, the gate insulating film is locally deposited on the part including the effective daylight region according to the method described in the method 丄, 3 or 4, and then is deposited on the substrate. After the semiconductor layer is completely deposited, and the image signal wiring and the day electrode are formed at the same time, the n + layer exposed on the surface is removed, and then the conformal film is deposited on the substrate in full or partially on the part containing the effective day region. After that, the redundant protective film and semiconductor layer are removed to form the channel portion of the thin film transistor, the image signal line, and the pixel electrode. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male) %)
請 先 閱 讀 背 © 之 注 意 事 填·· ί裝 頁I 訂 經濟部智慧財產局員工消費合作社印製 以 配 536655 Α7 ---- Β7 五、發明說明( 本發明採取的手段2 1,在依手段1 9或2 0所記載 的方法’在同時形成影像信號配線及汲極電極之後,除去 露出於表面的n+層,接著令護層膜於基板上全面沈積或局 部的沈積在包含有效畫素區域之部位,之後除去多餘的護 層膜及半導體層之後再形成透明畫素電極,以便形成薄膜 電晶體的通道部(Channel)及影像信號配線及汲極電極。 本發明採取的手段2 2,在依手段5或6所記載的方 法’將閘極絕緣膜及半導體層局部的沈積在包含有效畫素 區域之部位後,成形(Patterning)薄膜電晶體元件的通道 部(Channel),之後同時形成影像信號配線及畫素電極, 並在除去薄膜電晶體元件的通道部(Channel)的n+層之後 ’令護層膜局部的沈積在包含有效晝素區域之部位。 本發明採取的手段2 3,在依手段3或4所記載的方 法,將閘極絕緣膜局部的沈積在包含有效晝素區域之部位 後’接著令半導體層在基板上全面沈積,之後將薄膜電晶 體元件的通道部(Channel)成形(Patterning)後,同時形 成影像信號配線及畫素電極,接著除去薄膜電晶體的通道 部(Channel)的n+層,再將護層膜局部的沈積在包含有效 晝素區域之部位。 本發明採取的手段2 4,在依手段1或2所記載的方 法,將閘極絕緣膜局部的沈積在包含有效晝素區域之部位 後’將半導體層沈積於基板的全面或局部的沈積在包含有 效畫素區域之部位,接著令薄膜電晶體的通道部 (Channel)成形(Patterning)後,同時形成影像信號配線 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請 先 閱 讀 背Please read the notes of © © Fill in the page I. Order I Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to print 536655 Α7 ---- Β7 V. Description of the invention The method described in means 19 or 20 'after forming the image signal wiring and the drain electrode at the same time, remove the n + layer exposed on the surface, and then make the protective film be fully deposited on the substrate or partially deposited on the substrate containing effective pixels After removing the unnecessary protective film and semiconductor layer, the transparent pixel electrode is formed in order to form the channel of the thin film transistor, the image signal wiring, and the drain electrode. Means adopted by the present invention 22, After partially depositing the gate insulating film and the semiconductor layer on the portion including the effective pixel region according to the method described in the method 5 or 6, the channel portion of the thin film transistor is formed, and then formed simultaneously. Video signal wiring and pixel electrodes, and after removing the n + layer of the channel portion of the thin film transistor element, Part of the prime region. According to the method 2 or 3 of the present invention, the gate insulating film is partially deposited on the part containing the effective day prime region according to the method described in the means 3 or 4, and then the semiconductor layer is fully formed on the substrate. After deposition, the channel portion of the thin film transistor is patterned, and the image signal wiring and the pixel electrode are formed at the same time. Then, the n + layer of the channel portion of the thin film transistor is removed, and then the protective film is formed. Locally deposited on the site containing the effective daylight region. Means 24 adopted by the present invention is to deposit the gate insulating film locally on the site containing the effective daylight region according to the method described in means 1 or 2. The semiconductor layer is deposited on the substrate in whole or in part on the part containing the effective pixel area, and then the channel of the thin film transistor is formed (Patterning), and the image signal wiring is formed at the same time. This paper applies Chinese national standards ( CNS) A4 size (210 X 297 mm) Please read the back first
項 I» ί裝 頁I I 訂 經濟部智慧財產局員工消費合作社印製 536655 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(及) 及晝素電極,之後除去薄膜電晶體的通道部(Channel)的 n層’接著將護層膜沈積在基板的全面,而為了與驅動I c 接續’於端子部開設接續洞(Contacthole)。 本發明採取的手段2 5,在依手段5或6所記載的方 法中’將閘極絕緣膜及半導體層局部的沈積在包含有效晝 素區域之部位後,成形(Patterning)薄膜電晶體的通道部 (Channel),接著同時形成影像信號配線及畫素電極,之 後除去薄膜電晶體的通道部(Channel)的n+層,而將護層 膜沈積在包含有效畫素區域之部位,隨後於護層膜上形成 共通電極。 本發明採取的手段2 6,在使閘極絕緣膜局部的沈積 在包含有效畫素區域之部位後,將半導體層及蝕刻阻止層 層(EtchingStopper)在基板上全面沈積或局部沈積在包含 有效晝素區域之部位,為了得到歐姆接觸的n+層,如果是 採離子注入方式時,僅局部的注入於包含有效畫素區域之 部位;如層係以電漿化學氣相沈積法(CVD)沈積時, 則在基板上全面沈積,或局部的沈積在包含有效晝素區域 之部位。 本發明採取的手段2 7,係指手段2 6所記載的方法 ,其影像信號配線及晝素電極同時成形(Patterning)後, 以除去露出於表面的n+層及n+層以下的半導體層等二者, 將薄膜電晶體元件的通道部(Channel)及影像信號配線、 畫素電極等分別獨立的同時形成。 本發明採取的手段2 8,係指手段2 6、2 7所記載 ___ 10 本紙張尺度適用中國國家標準(CNS)A4規格---- (請先閱讀背面之注意事項再填寫本頁) ·! r·^^ I I —訂 111 — · — ··· #· 536655 A7 五、發明說明(< 的方法中,其影像信號配線及晝素電極同時形成後,將護 層膜在基板上全面沈積,或局部的沈積在包含有效畫素區 域之部位。接著為了與驅動Ic接續,除去接續端子部上 多餘的護層膜、n+層及半導體層。 本發明才木取的手段2 9,顯示—晝素,係將薄膜電晶 體的閘極電極配置成平行的二道以上,薄膜電晶體的通道 部⑽繼D也配置成平行的二道以上,附屬於二個以上 的各自的通道部(Channel)之没極電極被各自連結之晝素 電極所接合。 _ 本發明採取的手段3 0,係指根據手段1至6、手段 11至28所述方法所製作液晶顯示面板的方式是採用橫 電場方式。 本毛明採取的手段3 1,係指根據手段工6及2工所 述方法所作液晶顯示面板的方式是採用簡仏液 晶方式、強誘電液晶方式、反強誘電液晶方式或垂直配向 液晶方式。 經濟部智慧財產局員工消費合作社印製 本發明採取的手段3 2,係指根據手段,手段 1 1至2 8所述方法製作作的液晶顯示元件的掃晦線係紹 (或銘的合金)與鈦(或鈦的合金)的二層構造,或銘(或紹 合金)、鈦⑷太合金)及銦(或翻合金)的三層構造,或銘( 或銘合金)、鉻(或鉻合金)及翻(或銷合金)的三層構造構 成’與畫素電極成相對方向的共通電極採用鈦(或欽合金) 的單層構造,或由鈦(或鈦合金)及翻(或翻合金)的二層構 造構成’或為鉻(或鉻合金)及銦(或銦合金)的二層構造。Item I »tiling page II Order printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 536655 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The n-layer of the channel (channel) then deposits a protective film on the entire surface of the substrate, and a contact hole is opened in the terminal portion for connection with the driving IC. In the method 25 according to the present invention, in the method described in the method 5 or 6, the gate insulating film and the semiconductor layer are partially deposited on a portion including an effective daylight region, and then a channel of the thin film transistor is formed. Channel, and then simultaneously forming the image signal wiring and pixel electrodes, and then removing the n + layer of the channel portion of the thin film transistor, and depositing a protective film on the portion containing the effective pixel area, followed by the protective layer A common electrode is formed on the film. The method 26 adopted by the present invention is that after the gate insulating film is locally deposited on a portion containing an effective pixel area, a semiconductor layer and an etching stopper layer (EtchingStopper) are fully deposited on the substrate or partially In order to obtain the n + layer in the ohmic contact area, if it is an ion implantation method, it is only partially implanted in the part containing the effective pixel area; for example, when the layer is deposited by plasma chemical vapor deposition (CVD) , It is fully deposited on the substrate, or it is partially deposited on the part containing the effective daylight region. Means 27 adopted in the present invention refers to the method described in Means 26, in which the image signal wiring and the day electrode are patterned simultaneously to remove the n + layer and the semiconductor layer below the n + layer exposed on the surface. The channel portion of the thin film transistor element, the video signal wiring, and the pixel electrode are formed separately and simultaneously. Means 2 8 adopted in the present invention refer to means 2 6, 2 7 ___ 10 This paper size applies to China National Standard (CNS) A4 specifications ---- (Please read the precautions on the back before filling this page) ·! R · ^^ II —Order 111 — · — ··· # · 536655 A7 V. Description of the invention (< After the image signal wiring and the day electrode are formed at the same time, the protective film is placed on the substrate Full deposition, or partial deposition on the part containing the effective pixel area. Then, in order to connect with the driving IC, the excess protective film, n + layer and semiconductor layer on the connection terminal are removed. Display-day element, the gate electrode of the thin film transistor is arranged in two or more parallel, the channel part of the thin film transistor is also arranged in two or more parallel, attached to two or more respective channel parts The non-polar electrode of (Channel) is connected by the respective daylight electrode. _ Means 30 adopted in the present invention refer to the method of making a liquid crystal display panel according to the methods described in means 1 to 6, and means 11 to 28. Transverse electric field method. The method taken by means 31 means that the liquid crystal display panel made according to the methods described by means 6 and 2 is a simple liquid crystal method, a strongly induced liquid crystal method, an anti-strongly induced liquid crystal method, or a vertical alignment liquid crystal method. Means 3 2 adopted by the employee's consumer cooperative of the Property Bureau to print the present invention refers to the obscure lines of the liquid crystal display element produced by the method described in means 1 to 2 8 according to the means (or an alloy of the inscription) and titanium ( Or titanium alloy) two-layer structure, or three-layer structure of inscription (or Shao alloy), titanium alloy) and indium (or alloy), or inscription (or alloy), chromium (or chromium alloy) and The three-layer structure of the flip (or pin alloy) constitutes a common electrode in the opposite direction to the pixel electrode adopts a single layer structure of titanium (or chin alloy), or consists of titanium (or titanium alloy) and flip (or flip alloy). A two-layer structure 'or a two-layer structure of chromium (or chromium alloy) and indium (or indium alloy).
536655 A7 ^----- -B7______ 五、發明說明(/0 ) 本發明採取的手段3 3,係指根據手段}至6、手段 1 1至2 8所述方法製作的液晶顯示元件,其掃瞄線係由 鈦(或鈦合金)、銅(或銅合金)及鈦(或鈦合金)組成的三層 構造,或鉻(或鉻合金)、銅(或銅的合金)與鉬(或鉬合金) 組成的三層構造;又與畫素電極成相對方向的共通電極採 用鈦(或鈦合金)的單層構造構成,或鈦(或鈦合金)與鉬( 或鉬合金)組成的雙層構造,或由鉻(或鉻合金)與鉬(或鉬 合金)組成的雙層構造。 本發明採取的手段3 4,係指根據手段1至2 8中所 述方法製作的液晶顯示裝置,其影像信號配線是採用鈦( 或鈦合金)與鋁(或鋁合金)的雙層構造,或由鈦(或鈦合金 )與鉬(或鉬合金)的雙層構造,或由鉻(或鉻合金)與鉬(或 銦合金)組成的雙層構造。 經濟部智慧財產局員工消費合作社印製 本發明採取的手段3 5,係指根據手段1至2 8中所 述方法製作的液晶顯示裝置,其影像信號配線是採用由鈦 (或鈦合金)、鋁(或鋁合金)與鈦(或鈦合金)組成的三層構 造,或鈦(或鈦的合金)與鋁(或鋁的合金)與鉬(或鉬的合 金)的三層構造,或由鈦(或鈦合金)、鋁(或鋁合金)及鉻( 或鉻的合金)組成的三層構造,或由鈦(或鈦合金)、鉬(或 鉬合金)及鈦(或鈦合金)組成的三層構造,或由鈦(或鈦合 金)與鉻(或鉻合金)與鉬(或鉬合金)組成的三層構造。 本發明採取的手段3 6,係指根據手段1至g中所述 方法製作的液晶顯示裝置,係將閘極絕緣膜的沈積區域局 部性的限疋在有效畫素區域、影像信號配線的端子部區域 12 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 536655 A7 ______ B7 五、發明說明(//) 及靜電對策用保護主動式元件區域。 本發明採取的手段3 7,係指根據手段1至9中所述 方法製作的液晶顯示裝置,使從閘極絕緣膜的沈積邊界到 掃瞄線端子部末端的距離及從閘極絕緣膜的沈積邊界到靜 電對策用保護主動式元件的接合端子部末端的距離分別在 2mm以上。 本發明採取的手段3 8,係指根據手段1至6中所述 方法製作的液晶顯示裝置,是令與掃瞄線交叉的共通電極 與和影像信號配線交叉的共通電極的接續部分,位在局部 性沈積之閘極絕緣膜區域以外。 本發明採取的手段3 9,係指根據手段1至2 8中所 述方法製作的液晶顯示面板,其影像信號配線係採用由鈦 的矽化物與鋁(或鋁合金)組成的二層構造,或鉬的矽化物 與紹(或铭合金)組成的二層構造,或鉻的矽化物與鋁(或 鋁合金)組成的二層構造,或鈦的矽化物與鉬(或鉬合金) 組成的二層構造,或鉻的矽化物與鉬(或鉬合金)組成的二 層構造。 而根據前述技術手段可達成的功效,詳如以下所述: 經濟部智慧財產局員工消費合作社印製 第一圖所示者為習知的Twistnematic液晶方式用的 薄膜電晶體元件基板的剖面圖。由於在玻璃基板全面沈積 閘極絕緣膜、半導體膜及護層膜等三層膜的製造方法乃合 理的實現最少的光罩工程次數。但光罩工程的整個工程需 要5次’在此限制下即無法進一步降低成本。又如第二圖 所示,係橫電場方式液晶方式用的薄膜電晶體元件基板的 13 本紙張尺度適用中關家標準(CNS)A4規格(21G X 297公釐)" --- 經濟部智慧財產局員工消費合作社印製 五、發明說明(/>) 剖面。在此場合與第—圖 閘極絕緣膜、半導體膜疋知用在玻璃基板全面沈積 橫電場方式中,因不《頁使用:膜等二層膜的製造方法。於 4)(透明電⑴/、 第—圖所㈣4素電極(1 次it成可減少—次光罩工程,全工程可以4 姓。㈣/⑵ 時,掃晦線與共通電極將不可能連 I在SI ::像信號配線與共通電極也不可能連結。因 來成影像信號配線端子部上開了接續孔後 化成接合電極(13),月μ里 故須使用第5道光罩。施電對策用保護電晶體’ 奐S之,無論採用何種的液晶方式 ’要不降低良率且能安宗& ,疋生產,如採用習知製程,降低成 本的效果將極其有限。 而如採取本發明之手段1至9,因不需要開設端子部 接續孔,可大幅縮短的工程。且即使縮短工程,與習知者 同樣的可在基板上形成靜電對策用保護電晶體,因此不會 降低良率。 又以僅沈積最低必要面積的厚膜閘極絕緣膜,可減少 對玻璃基板產生的應力,因此pattern的變形量也變小。 因此可減少光罩間的對位偏差,因對位偏差所生的顯示不 均現象亦可大幅減少。同樣的,對向基板之彩色濾光片基 板與薄膜電晶體基板間的對合對位偏差亦可減少,因此液 晶Cel 1工程(面板組裝工程)的良率可因此大幅的提昇。 又採用本發明的手段1 〇,因容易使框膠線區域的 CellGap(面板間隙)均勻化,因此可有效降低液晶cell工 程(面板組裝工程)的不良率。 請 先 閱 讀 背 之 注 意 事 1% f 訂 # 14 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 536655 A7 --- B7 五、發明說明(丨3 ) 採用本發明手段1到9及手段1 1到1 4,可在薄膜 電晶體元件基板上形成靜電對策用保護電晶體,全工作僅 須兩道光罩工程,藉此以大幅縮短工程,而實現大幅降低 成本及提高生產效率之目的。而生產工廠的無塵室面積也 可望縮小,昂貴的清洗機、光阻塗布機、顯像裝置及曝光 裝置等裝備數量可降低至以往的一半以下,因此可大幅減 少初期的投資成本。又因已可不需要保管用的無塵倉儲( CleanStoker),故可減少大型基板上的灰塵附著,而相 對提高良率。再者,因清洗工程大量減少,純水的使用量 也減少,而使運轉成本大幅降低。採用與廉價的印刷彩色 濾、光片的組合可以實現比單純短陣型晶面板 (STN模示)更低成本的主動式矩陣型液晶面板(橫電場液晶 方式)。因此家庭的電視機也可能從影像管(CRT)轉換成主 動式矩陣型液晶面板。 如採用本發明的手段1 5,可用以製作小型的液晶面 板。 經濟部智慧財產局員工消費合作社印製 如採用本發明的手段1 6、2 1可利用四次的光罩工 程製作習用Twistnematic液晶方式的液晶面板,可降低 生產成本。 如採用本發明的手段1 7、1 8,因可高精度的控制 閘極電極與畫素電極(汲極電極)的重疊面積,故可大量減 少顯示不均現象而提高良率。 如採用本發明的手段1 9、2 〇、2 1,薄膜電晶體 元件基板上可形成靜電對策用保護電晶體,全工程只以三 15 本紙張尺度適用中國國家標準(CNS)A4規格(21G X 297公f " 536655 A7 B7 五、發明說明(# ) 人光罩工私即可完成,可降低生產成本及大幅提高生產效 率。又於此工程因護層膜並未覆蓋整個有效畫面,而並未 給予玻璃基板大的應力,因此為玻璃基板尺寸變化最小的 製私’當液晶顯示畫面超大型化時,於液晶組裝工程,彩 色濾光片基板與薄膜電晶體基板對合壓著時,可使對合壓 著對位誤差最小化。在此工程閘極電極與晝素電極(沒極 電極)的光罩對位誤差也由於不變因製程的安定性非常高 之故,顯示不均的發生率少,可實現高良率。 如抓用本發明的手段2 2至2 5,薄膜電晶體元件基 板上可形成靜電對策用保護電晶體,全工程可以三至四道 光罩工程完成。且此工程亦可在最後再形成共通電極,製 耘的自由度非常大。乃為pattern形成後的段差的落差最 小的製程,因此不容易發生配線斷線的現象,又,因液晶 組裝工程的配向膜形成後的配向處理變得非常容易,故可 使良率成為最高。 經濟部智慧財產局員工消費合作社印製 如採用本發明的手段2 6S2 8,薄膜電晶體元件基 板上可形成靜電對策用保護電晶體,全工程只須三至四道 光罩工程即可完成。於此工程中,薄膜半導體層可以薄到 5〇〇 A的程度’而因通道部分上n+層無殘留之故,乾式钱 刻時的基板全面均一性的要求標準降低,與準分子雷射的 組合,可較易變更為PolySi薄膜電晶體製程。而利用背 面曝光技術也可適用於自我整合(Sel卜Align_t)技術, 可實現超大型液晶晝面的製作。 如採取本發明的手段2 9,在超大型畫面的場合,即536655 A7 ^ ----- -B7 ______ V. Description of the Invention (/ 0) The means 3 3 adopted in the present invention refers to the liquid crystal display elements manufactured according to the methods described in means} to 6, and means 1 1 to 2 8 The scanning line is a three-layer structure composed of titanium (or titanium alloy), copper (or copper alloy) and titanium (or titanium alloy), or chromium (or chromium alloy), copper (or copper alloy), and molybdenum (or A three-layer structure composed of molybdenum alloy); the common electrode opposite to the pixel electrode is composed of a single layer structure of titanium (or titanium alloy), or a double layer composed of titanium (or titanium alloy) and molybdenum (or molybdenum alloy) Layer structure, or a double-layer structure composed of chromium (or chromium alloy) and molybdenum (or molybdenum alloy). Means 34 adopted in the present invention refer to a liquid crystal display device manufactured according to the method described in Means 1 to 28, and the image signal wiring thereof adopts a double-layer structure of titanium (or a titanium alloy) and aluminum (or an aluminum alloy). Or a double-layer structure made of titanium (or a titanium alloy) and molybdenum (or a molybdenum alloy), or a double-layer structure made of chromium (or a chromium alloy) and molybdenum (or an indium alloy). The method 3 5 adopted by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to print the present invention refers to a liquid crystal display device manufactured according to the method described in means 1 to 28. The image signal wiring is made of titanium (or titanium alloy), A three-layer structure consisting of aluminum (or aluminum alloy) and titanium (or titanium alloy), or a three-layer structure consisting of titanium (or alloy of titanium) and aluminum (or alloy of aluminum) and molybdenum (or alloy of molybdenum), or Three-layer structure consisting of titanium (or titanium alloy), aluminum (or aluminum alloy), and chromium (or chromium alloy), or consisting of titanium (or titanium alloy), molybdenum (or molybdenum alloy), and titanium (or titanium alloy) Three-layer structure, or a three-layer structure composed of titanium (or titanium alloy) and chromium (or chromium alloy) and molybdenum (or molybdenum alloy). Means 36 adopted in the present invention refer to the liquid crystal display device manufactured according to the methods described in means 1 to g, which locally limit the deposition area of the gate insulating film to the effective pixel area and the terminals of the video signal wiring Area 12 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 public love) 536655 A7 ______ B7 5. Description of the invention (//) and protection of active components for electrostatic countermeasures. Means 37 adopted in the present invention refer to the liquid crystal display device manufactured according to the method described in Means 1 to 9, such that the distance from the deposition boundary of the gate insulating film to the end of the scanning line terminal portion and the distance from the gate insulating film The distance from the deposition boundary to the end of the bonding terminal portion of the protective active element for electrostatic measures is at least 2 mm. Means 38 adopted in the present invention refers to a liquid crystal display device manufactured according to the method described in Means 1 to 6. It is a continuation part of a common electrode that intersects the scanning line and a common electrode that intersects the video signal wiring. Locally deposited gate insulating film area. Means 39 adopted by the present invention refers to a liquid crystal display panel manufactured according to the method described in means 1 to 28, and its image signal wiring adopts a two-layer structure composed of silicide of titanium and aluminum (or aluminum alloy). Or a two-layer structure composed of silicide of molybdenum and Shao (or Ming alloy), or a two-layer structure of silicide of chromium and aluminum (or aluminum alloy), or a silicide of titanium and molybdenum (or molybdenum alloy) Two-layer structure, or a two-layer structure composed of silicide of chromium and molybdenum (or molybdenum alloy). The effects that can be achieved according to the aforementioned technical means are detailed as follows: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The first picture shows a cross-sectional view of a thin-film transistor element substrate for the conventional Twistnematic liquid crystal method. Because the three-layer film manufacturing method, such as gate insulation film, semiconductor film, and protective film, is fully deposited on the glass substrate, the minimum number of photomask projects is reasonably achieved. However, the entire process of the photomask project requires 5 times. 'Within this limit, the cost cannot be further reduced. As shown in the second figure, the 13 paper sizes of the thin-film transistor element substrate for the liquid crystal mode of the transverse electric field method are applicable to the Zhongguanjia Standard (CNS) A4 specification (21G X 297 mm) " --- Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives V. Invention Description (/ >) section. In this case, the gate insulation film and semiconductor film are known to be used in the full-field deposition of a glass substrate in the transverse electric field method, because the method of manufacturing a two-layer film such as a film is not used. (4) (Transparent electrode), (see Figure 4) 4 element electrodes (1 time it can be reduced-2 times the photomask project, the whole project can be 4 surnames. At ㈣ / ⑵, the scan line and the common electrode will not be connected I is also impossible to connect the SI :: image signal wiring to the common electrode. Since the connection hole is formed in the video signal wiring terminal portion, it becomes a bonding electrode (13). Therefore, a 5th photomask must be used within a month. As a countermeasure, the protection transistor '奂 S, no matter which liquid crystal method is used', can not be reduced in yield and can be used in production, if the conventional process is used, the effect of reducing costs will be extremely limited. The means 1 to 9 of the present invention can greatly shorten the process because it is not necessary to provide a connection hole in the terminal portion. Even if the process is shortened, a protective transistor for electrostatic countermeasures can be formed on the substrate in the same way as a known person, so it will not be reduced. Yield. Also, by depositing a thick film gate insulating film with only the minimum necessary area, the stress on the glass substrate can be reduced, so the amount of pattern deformation is reduced. Therefore, the misalignment between the masks can be reduced. The display caused by the deviation is not The phenomenon can also be greatly reduced. Similarly, the misalignment and misalignment between the color filter substrate and the thin film transistor substrate of the counter substrate can also be reduced, so the yield of the liquid crystal Cel 1 process (panel assembly process) can be greatly reduced. By using the method 10 of the present invention, since the CellGap (panel gap) of the frame rubber line area is easy to be uniformized, the defect rate of the liquid crystal cell project (panel assembly process) can be effectively reduced. Please read the note on the back first Matter 1% f Order # 14 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536655 A7 --- B7 V. Description of the invention (丨 3) Use of the means 1 to 9 and means 1 of the present invention From 1 to 14, protective transistors for electrostatic countermeasures can be formed on thin-film transistor element substrates. The entire work requires only two photomask projects, thereby greatly shortening the project, and achieving a substantial reduction in costs and an increase in production efficiency. The clean room area of the production plant is also expected to be reduced, and the number of expensive cleaning machines, photoresist coaters, developing devices, and exposure devices can be reduced to less than half of the past. The initial investment cost can be greatly reduced. Since the CleanStoker for storage is no longer needed, dust adhesion on large substrates can be reduced, and the yield can be relatively improved. Furthermore, due to the large reduction in cleaning processes, pure water The use amount is also reduced, which greatly reduces the running cost. The combination with cheap printed color filters and light filters can achieve a lower cost active matrix liquid crystal panel (horizontal) than a simple short-array crystal panel (STN model). Electric field liquid crystal method). Therefore, the home television may also be converted from an image tube (CRT) to an active matrix liquid crystal panel. If the method 15 of the present invention is adopted, it can be used to make a small liquid crystal panel. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the method 16, 21 of the present invention is used, the conventional Twistnematic liquid crystal panel can be manufactured by using the four mask processes, which can reduce the production cost. If the means 17 and 18 of the present invention are adopted, the overlap area of the gate electrode and the pixel electrode (drain electrode) can be controlled with high accuracy, so that the display unevenness can be reduced greatly and the yield can be improved. If the method 19, 20, 21 of the present invention is adopted, a protective transistor for static electricity countermeasures can be formed on the thin film transistor element substrate. The entire project is only applicable to the Chinese National Standard (CNS) A4 specification (21G) on the basis of three 15 paper sizes. X 297 male f " 536655 A7 B7 V. Description of the invention (#) The mask can be completed by workers and private workers, which can reduce production costs and greatly improve production efficiency. In this project, because the protective film does not cover the entire effective screen, It does not give a large stress to the glass substrate, so it is a manufacturing system with the smallest change in the size of the glass substrate. When the liquid crystal display screen is very large, in the liquid crystal assembly process, when the color filter substrate and the thin film transistor substrate are pressed together, , Which can minimize the alignment and alignment error. In this project, the mask alignment error between the gate electrode and the day element electrode (without electrode) is also unchanged because the stability of the process is very high. Even if the average occurrence rate is small, a high yield can be achieved. For example, by using the means 22 to 25 of the present invention, a protective transistor for electrostatic countermeasures can be formed on the thin-film transistor element substrate, and the whole process can be three to four mask workers. The process can be completed. And this project can also form a common electrode at the end, and the degree of freedom of manufacturing is very large. It is the process with the smallest step difference after the pattern is formed, so it is not easy to cause the disconnection of the wiring. The alignment process after the formation of the alignment film in the assembly process becomes very easy, so that the yield can be maximized. If printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the method 2 6S 2 8 of the present invention can be used on the thin film transistor element substrate. To form a protective transistor for electrostatic countermeasures, the entire project can be completed in only three to four photomask projects. In this project, the thin-film semiconductor layer can be as thin as 500A ', and there is no residual n + layer on the channel part. Therefore, the requirements for the overall uniformity of the substrate during dry money engraving are reduced, and the combination with excimer laser can be easily changed to the PolySi thin film transistor process. The back exposure technology can also be applied to self-integration (Selbu Align_t ) Technology can realize the production of ultra-large liquid crystal daytime. For example, if the method 2 of the present invention is adopted, in the case of ultra-large screens, that is,
536655536655
使因基板尺寸變化而局部的產生對位偏差,因汲極電極及 閘極電極所形成的容量沒有變化,故顯示畫面上不會發生 不均勻現象。 如採取本發明的手段3 2至3 5,可大幅降低掃瞄線 的阻抗’且共通電極的阻抗亦可大幅降低。又,由於書素 内部的液晶驅動電極及與液晶驅動電極成對向的晝素共通 電極的電極膜厚可以變薄,液晶組裝工程的配向處理變得 非常容易。且由於可將配向處理密度及均一性提得非常高 ’故可得到信賴性及再現性良好而無不均勻現象之畫質。 如採取本發明的手段3 4、3 5及3 9,可防止閘極 絕緣膜的沈積區域邊界部分之膜剝落。特別是鈦及高融點 金屬的矽化物化合物與玻璃基板及電漿化學氣相沈積膜( 矽氧化膜,矽氮化膜)的接著力非常強,不易產生膜剝落 現象。於本發明特別是該沈積區域邊界部分的電極 Pattern形成後的膜剝落仍是最大的問題,此可利用限定 金屬種類獲得解決。影像信號配線採用鋁或鋁合金亦不會 產生膜剝落但是無法與n+層直接接合,故鋁與層之間 需要高融點金屬或高融點金屬矽化物化合物層。 經濟部智慧財產局員工消費合作社印製 如採取本發明的手段3 6,因閘極絕緣膜的沈積區域 擴大至影像信號配線端子或靜電對策用保護主動式元件的 區域,影像信號配線端子部與閘極絕緣膜的沈積區域邊界 的交叉部消失’故電極剝落的不良現象可大量減少,因此 可大幅提高良率。 如採取本發明的手段3 7,可充分的保證玻璃基板尺 17 本紙張尺庋週用T國國家標準(CNS)A4iFr210 X 297公釐)--~ 536655 五、發明說明(从) 經濟部智慧財產局員工消費合作社印製 寸加工精度與閘極絕緣膜的局部性沈積位置之精度。由於 P-CVD裝置的閘極絕緣膜沈積溫度約為3〇(rc,考慮裝置 的治具變形及熱膨脹係數之差,此值乃重要的數值。^於 此值時,掃瞄線端子部全面上沈積閘極絕緣膜,與TAB的 有效接合面積變小等之故,大量出現接觸不良現象及畫像 的橫線條不均勻。如採用手段3 7,將不會發生接觸不良 及橫線條不均勻等現象。 為使貴審查委員進一步瞭解前述目的及本發明之技 術特徵,茲附以圖式詳細說明如后: (一)圖式部分: 第一圖:係習知的縱電場方式薄膜半導體基板的單位畫素 的剖面圖。 係習知的橫電場方式薄膜半導體基板的單位畫素 的剖面圖。 係本發明的橫電場方式薄膜半導體基板的單位晝 素的剖面圖。 係本發明的橫電場方式薄膜半導體基板的單位晝 素的剖面圖。 係本發明的橫電場方式薄膜半導體基板的單位晝 素的剖面圖。 第六圖:係本發明的橫電場方式薄膜半導體基板的單位晝 素的剖面圖。 第七圖:係本發明的縱電場方式薄膜半導體基板的單位晝 素的剖面圖。 第二圖 第三圖 第四圖 第五圖 18 536655 A7 五、發明說明(/ 經濟部智慧財產局員工消費合作社印製 第八圖:係本發明的橫電場方式 素的剖面圖。 第九圖:係'本發明的橫電場方式薄膜半導體基板的單位晝 素的剖面圖。 第十圖:係本發明的縱電場方式 素的剖面圖。 第十一圖:係本發明的橫電場方式 晝素的剖面圖。 第十二圖··係本發明的橫電場方式 晝素的剖面圖。 第十二圖·係本發明的橫雷i县He — I 方式薄膜半導體基板的單位 畫素的剖面圖。 弟十四圖·係本發明的橫雷 去Ά方式薄膜半導體基板的單位 旦素的剖面圖。 第十五圖1本發㈣縱電場方式薄料㈣基板的單 畫素的剖面圖。 第十六圖:發明的橫電場方式薄膜半導體基板的單位 畫素的剖面圖。 第十七圖:^翻的橫電場方式薄料導體基板的單位 畺素的剖面圖。 第十八圖:^發明㈣電場方式薄料導體基 晝素的剖面圖。 第十九圖:^發㈣橫電場方式薄膜半導體基板的單位 旦素的剖面圖。 薄膜半導體基板的單位畫 溥膜半導體基板的單位晝 薄膜半導體基板的單位 薄膜半導體基板的單位 位 536655As a result of the misalignment locally caused by the substrate size change, there is no change in the capacity formed by the drain electrode and the gate electrode, so that unevenness does not occur on the display screen. By adopting the measures 32 to 35 of the present invention, the impedance of the scanning line can be greatly reduced, and the impedance of the common electrode can also be greatly reduced. In addition, since the thickness of the electrode film of the liquid crystal driving electrode and the daylight common electrode opposed to the liquid crystal driving electrode in the book can be reduced, the alignment processing of the liquid crystal assembly process becomes very easy. Moreover, since the alignment processing density and uniformity can be improved very high, an image quality with good reliability and reproducibility without unevenness can be obtained. By adopting the means 3, 4, 5, and 39 of the present invention, it is possible to prevent the film from peeling off at the boundary portion of the deposition region of the gate insulating film. In particular, the adhesion force of the silicide compound of titanium and high melting point metal to the glass substrate and plasma chemical vapor deposition film (silicon oxide film, silicon nitride film) is very strong, and it is not easy to cause film peeling. In the present invention, especially the peeling of the film after the electrode pattern is formed at the boundary portion of the deposition area is still the biggest problem, which can be solved by limiting the type of metal. The use of aluminum or aluminum alloy for image signal wiring will not cause film peeling but cannot be directly bonded to the n + layer. Therefore, a high melting point metal or a high melting point metal silicide compound layer is required between aluminum and the layer. If the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the method 36 of the present invention, the deposition area of the gate insulating film is enlarged to the area of the video signal wiring terminal or the active component for electrostatic countermeasures. The video signal wiring terminal and the The cross section of the boundary of the deposition region of the gate insulating film disappears. Therefore, the problem of electrode peeling can be greatly reduced, and the yield can be greatly improved. If the method 3 of the present invention is adopted, the glass substrate ruler 17 can be fully guaranteed. The national paper standard (CNS) A4iFr210 X 297 mm is used for weekly use.-~ 536655 V. Description of the invention (from) Wisdom of the Ministry of Economic Affairs The processing accuracy of the printing bureau of the property bureau employee consumer cooperative and the accuracy of the local deposition location of the gate insulating film. Since the gate insulating film deposition temperature of the P-CVD device is about 30 ° C, this value is an important value in consideration of the device's jig deformation and the thermal expansion coefficient. ^ At this value, the scanning line terminal section is comprehensive The gate insulation film is deposited thereon, and the effective joint area with the TAB becomes small, etc., a large number of poor contact phenomenon and uneven horizontal lines of the image will appear. If the means 37 is adopted, poor contact and uneven horizontal lines will not occur. In order to make your reviewers better understand the foregoing objectives and the technical characteristics of the present invention, detailed drawings are attached as follows: (1) Schematic part: The first figure: the conventional vertical electric field method thin film semiconductor substrate A cross-sectional view of a unit pixel. A cross-sectional view of a unit pixel of a conventional transverse electric field type thin film semiconductor substrate. A cross-sectional view of a unit pixel of a transverse electric field type thin-film semiconductor substrate of the present invention. A cross-sectional view of a unit semiconductor element of a thin film semiconductor substrate. A cross-sectional view of a unit semiconductor element of a thin-film semiconductor substrate of a transverse electric field method of the present invention. A cross-sectional view of a unit day element of a field-type thin-film semiconductor substrate. A seventh view: A cross-sectional view of a unit day-element of a longitudinal electric field-type thin-film semiconductor substrate of the present invention. Second view Third view Fourth view Fifth view Fifth view 18 536655 A7 V. Description of the invention (/ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 8: A cross-sectional view of the transverse electric field method element of the present invention. Figure 9: The unit day of the transverse electric field method thin film semiconductor substrate of the present invention Sectional view of the element. Figure 10: A cross-sectional view of the vertical electric field method element of the present invention. Figure 11: A cross-sectional view of the horizontal electric field method element of the present invention. A cross-sectional view of an electric field system day element. The twelfth image is a cross-sectional view of a unit pixel of a He-I-type thin-film semiconductor substrate in the Henglei county of the present invention. A cross-sectional view of a unit thin film of a thin film semiconductor substrate. Fifteenth FIG. 1 A cross-sectional view of a single pixel of a thin material substrate of a longitudinal electric field method of the present invention. FIG. Sectional view of pixels. Figure 17: Sectional view of the unit element of the thin-field conductor substrate of the transverse electric field method. Figure 18: Sectional view of the basic element of the thin-film conductor substrate of the invention of the electric field method. Nineteenth figure: A cross-sectional view of a unit denier of a thin-film semiconductor substrate with a transverse electric field method. A unit drawing of a thin-film semiconductor substrate. A unit of a thin-film semiconductor substrate. A unit of a thin-film semiconductor substrate. A unit of a thin-film semiconductor substrate.
五、 發明說明(/) 第二十圖:係本發明的橫電場方式薄膜半導體基板的單位 畫素的剖面圖。 第二十-圖:係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 第二十二圖:係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 係本發明的橫電場方式薄膜半導體基板的單 位晝素的剖面圖。 係本發明的縱電場方式薄膜半導體基板的單 位晝素的剖面圖。 係本發明的透光量調整光罩的剖面圖。 係本發明的透光量調整光罩的剖面圖。 係本發明的透光量調整光罩的剖面圖。 係本發明的透光量調整光罩的剖面圖。 係用本發明的透光量調整光罩的曝光,顯影 處理後的正光阻的剖面圖。 係用本發明的透光量調整光罩的薄膜電晶體 元件的製程流程。 經濟部智慧財產局員工消費合作社印製 弟一·十三圖 弟—十四圖 第二十五圖 第二十六圖 第二十七圖 第二十八圖 第二十九圖 第三十圖 第三十一圖 第三十二圖 弟二卞二圖 第三十四圖 第三十五圖 第三十六圖 係本發明的薄膜電晶體元件的平面圖。 係本發明的薄膜電晶體元件的平面圖。 係本發明的薄膜電晶體元件的平面圖。 係本發明的薄膜電晶體元件的平面圖。 係本务明的掃瞄電極與共通電極的平面圖。 係本發明的掃瞄電極與共通電極的剖面 20 五 、發明說明(// 第三十七圖 第三十八圖 第三十九圖 第四十圖 第四十一圖 第四十二圖 第四十三圖 第四十四圖 第四十五圖 第四十六圖 第四十七圖 第四十八圖 第四十九圖 第五十圖 第五十一圖 第五十二圖 =本《明的掃⑱電極與共通電極的剖面圖。 糸本I明的掃瞒電極與共通電極的剖面圖。 2本發明的影像信號配線與沒極電極的平面 圖。 係本發明的影像信號配線的剖面圖。 係本發明的影像信號配線的剖面圖。 係本么曰月的影像信號配線的咅,J面圖。 係本發明的薄膜半導體基板的平面圖。 係本發明的薄膜半導體基板的平面圖。 係本發明的薄膜半導體基板的平面圖。 係本發明的框膠線的配置平面圖。 係本發明的框膠線的配置平面圖。 係本發明所利用的靜電對策用保護回路圖。 係本發明所湘的靜電對策用保護回路圖。 係本發明的橫電場方式薄膜半導體元件的平 面圖。 係本發明的橫電場方式薄膜半導體元件的平 面圖。 係本發明的靜電對策用保護電晶體元件的平 面圖。 第五十三圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第五十四圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 21 W6655 A7 B7 五、發明說明( 第五十五圖:係本發明的靜電對策用保護電晶體元件的平 面圖 第十,、圖係、本發明的橫電場方式薄膜半導體元件的平 面圖。 第五十七圖:係本發明的橫電場方式薄膜半導體元件的平 面圖。 第五十八圖:係本發明的靜電對策用保護電晶體it件的平 面圖。 第五十九圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 的靜電對策用保護電晶體元件的平 弟六十圖··係本發明 面圖 第六十-圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第/、十一圖·係本發明的縱電場方式薄膜半導體元件的平 面圖。 第/、十二圖·係本發明的縱電場方式薄膜半導體元件的平 面圖。 第六十四圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第六十五圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第六十六圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 22 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公复 536655 五、發明說明(w ) 第六十七圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第六十八圖:係本發明的橫電場方式薄膜半導體元件的平 面圖。 第六十九圖W系本發明的橫電場方式薄膜半導體元件的平 面圖。 第七十圖係本發明的靜電對策用保護電晶體元件的平 面圖。 第十圖係本發明的靜電對策用保護電晶體元件的平 面圖。 第七十二圖··係本發明的靜電對策用保護電晶體元件的平 面圖。 第七十三圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第七十四圖:係本發明的縱電場方式薄膜半導體元件的平 面圖。 經濟部智慧財產局員工消費合作社印製 第七十五圖:係本發明的縱電場方式薄膜半導體元件的平 面圖。 第七十六圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第七十七圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第七十八圖·係本發明的靜電對策用保護電晶體元件的平 面圖。 23 W6655 A7 B7 、發明說明(以) 弟七十九圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 "十圖·係本發明的橫電場方式薄膜半導體元件的平 面圖。 第八十1 :係本發明的橫電場方式薄膜半導體元件的平 面圖。 第八十二圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 第十一圖·係本發明的靜電對策用保護電晶體元件的平 面圖。 第十四圖·係本發明的靜電對策用保護電晶體元件的平 面圖。 第十五圖·係本發明的靜電對策用保護電晶體元件的平 面圖。 第八十/、圖·係本發明的橫電場方式薄膜半導體元件的平 面圖。 第八十七圖:係本發明的橫電場方式薄膜半導體元件的平 面圖。 第八十八圖··係本發明的靜電對策用保護電晶體元件的平 面圖。 第八十九圖··係本發明的靜電對策用保護電晶體元件的平 面圖。 第九十圖:係本發明的靜電對策用保護電晶體元件的平 面圖。 ------I-----«裝 (請先閱讀背面之注意事項再填寫本頁) ----訂--------- # 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 24 536655 A7V. Description of the invention (/) Figure 20: A cross-sectional view of a unit pixel of a thin-film semiconductor substrate of the transverse electric field method of the present invention. 20th figure: A cross-sectional view of a unit pixel of a transverse electric field type thin film semiconductor substrate of the present invention. Fig. 22 is a cross-sectional view of a unit pixel of a transverse electric field type thin film semiconductor substrate of the present invention. This is a cross-sectional view of a unit day element of a thin-film semiconductor substrate of the transverse electric field method of the present invention. It is a cross-sectional view of a unit element of a longitudinal electric field type thin film semiconductor substrate of the present invention. This is a cross-sectional view of the light transmission amount adjustment mask of the present invention. This is a cross-sectional view of the light transmission amount adjustment mask of the present invention. This is a cross-sectional view of the light transmission amount adjustment mask of the present invention. This is a cross-sectional view of the light transmission amount adjustment mask of the present invention. This is a cross-sectional view of the positive photoresist after the exposure and development processing of the photomask using the light transmission amount of the present invention. The manufacturing process of the thin film transistor element using the light transmission amount adjustment mask of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 13-Figure 14-Figure 25-Figure 26-Figure 27-Figure 27-Figure 29-Figure 29-Figure 30 Figure 31 is a plan view of Figure 32, Figure 22, Figure 34, Figure 35, Figure 36 and Figure 36 are thin film transistor elements of the present invention. It is a plan view of a thin film transistor element of the present invention. It is a plan view of a thin film transistor element of the present invention. It is a plan view of a thin film transistor element of the present invention. This is a plan view of the scanning electrode and common electrode. It is a cross section of the scanning electrode and the common electrode of the present invention. 20 5. Description of the invention (// FIG. 37, FIG. 38, FIG. 39, FIG. 40, FIG. 41, FIG. 41, FIG. 42 Forty-three figure forty-fourth figure forty-fifth figure forty-fifth figure forty-sixth figure forty-seventh figure forty-eighth figure forty-ninth figure forty-ninth figure forty-fifth figure fifty-first figure fifty-second figure = this "Cross-sectional view of a bright sweep electrode and a common electrode. A cross-sectional view of a clear sweep electrode and a common electrode. 2 A plan view of the video signal wiring and the non-polar electrode of the present invention. It is a video signal wiring of the present invention. Sectional view. Sectional view of the image signal wiring of the present invention. Sectional view of the image signal wiring of the present month. Plane view of the thin film semiconductor substrate of the present invention. Sectional view of the thin film semiconductor substrate of the present invention. It is a plan view of the thin film semiconductor substrate of the present invention. It is a plan view of the layout of the frame rubber wire of the present invention. It is a plan view of the layout of the frame rubber wire of the present invention. It is a protection circuit diagram for the electrostatic countermeasures used by the present invention. For static electricity countermeasures Circuit diagram of the protection circuit. Plan view of the thin-film semiconductor element of the transverse electric field type of the present invention. Plan view of the thin-film semiconductor element of the transverse electric field type of the present invention. Plan view of the protective transistor element for electrostatic countermeasures of the present invention. It is a plan view of the protective transistor element for electrostatic countermeasures of the present invention. Figure 54: It is a plan view of the protective transistor element for electrostatic countermeasures of the present invention. 21 W6655 A7 B7 V. Description of the invention The tenth plan view of the protective transistor element for electrostatic countermeasures of the present invention is a plan view of a transverse electric field type thin film semiconductor element of the present invention. The fifty-seventh figure: is a plan view of a transverse electric field type thin film semiconductor element of the present invention. Fig. 58 is a plan view of a protective transistor element for an electrostatic countermeasure of the present invention. Fig. 59 is a plan view of a protective transistor element for an electrostatic countermeasure of the present invention. Figure 60 of the younger brother ... This is the surface view of the present invention. The figure 60 is a protection transistor for electrostatic countermeasures of the present invention. Element plan view. Figures 11 and 11 are plan views of the thin-film semiconductor element of the longitudinal electric field type of the present invention. Figures 12 and 12 are plan views of the thin-film semiconductor element of the longitudinal electric field type of the present invention. Figure 64: Fig. 65 is a plan view of the protective transistor element for the electrostatic countermeasures of the present invention. Fig. 65 is a plan view of the protective transistor element for the electrostatic countermeasures of the present invention. Fig. 66 is a protective transistor for the electrostatic countermeasures of the present invention. The plan view of the element. 22 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public reply 536655) 5. Description of the invention (w) Figure 67: This is a plan view of the protective transistor element for electrostatic countermeasures of the present invention. Fig. 68 is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. Fig. 69 is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. The seventieth figure is a plan view of a protective transistor element for countermeasures against static electricity of the present invention. The tenth figure is a plan view of a protective transistor element for countermeasures against static electricity of the present invention. Fig. 72 is a plan view of a protective transistor element for countermeasures against static electricity of the present invention. Figure 73 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Figure 74 is a plan view of a longitudinal electric field type thin film semiconductor device according to the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 75: This is a plan view of a longitudinal electric field type thin film semiconductor device of the present invention. Figure 76 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Fig. 77 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Fig. 78 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. 23 W6655 A7 B7, description of the invention (to) Younger figure 79: This is a plan view of the protective transistor element for electrostatic countermeasures of the present invention. " Ten diagrams " is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. Eighty-first: It is a plan view of a transverse electric field type thin film semiconductor device of the present invention. Fig. 82 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Fig. 11 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Fig. 14 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Fig. 15 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Eighteenth /. Fig. · Is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. Fig. 87 is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. The eighty-eighth figure is a plan view of a protective transistor element for electrostatic countermeasures of the present invention. Fig. 89 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. Fig. 90 is a plan view of a protective transistor element for countermeasures against static electricity according to the present invention. ------ I ----- «Installation (please read the precautions on the back before filling out this page) ---- Order --------- # Employee Cooperatives of Intellectual Property Bureau Printed 24 536655 A7
五、發明說明(4 ) 第九十一圖··係本發明的靜電對策用保護電晶體元件的平 面圖。 第九十二圖:係本發明的閘極絕緣膜局部堆積區域的平面 圖。 第九十二圖:係本發明的閘極絕緣膜局部堆積區域的平面 圖。 第九十四圖:係本發明的透光量調整光罩的平面圖。 第九十五圖:係本發明的透光量調整光罩的平面圖。 第九十六圖:係本發明的橫電場方式薄膜半導體基板的平 面圖。 第九十七圖··係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 第九十八圖:係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 第九十九圖:係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 第一 0 0圖:係本發明的橫電場方式薄膜半導體元件的平 面圖。 經濟部智慧財產局員工消費合作社印f 第一 0 —圖:係本發明的橫電場方式薄膜半導體元件的平 面圖。 第一 0 —圖··係本發明的橫電場方式薄膜半導體基板的單 位晝素的剖面圖。 第一 〇二圖··係本發明的橫電場方式薄膜半導體基板的單 位晝素的剖面圖。 25 A7V. Description of the Invention (4) Figure 91 is a plan view of the protective transistor element for electrostatic countermeasures of the present invention. Fig. 92 is a plan view of a partially deposited region of the gate insulating film of the present invention. Fig. 92 is a plan view of a partially deposited region of the gate insulating film of the present invention. Fig. 94 is a plan view of a light transmission amount adjusting mask of the present invention. Fig. 95 is a plan view of a light transmission amount adjusting mask of the present invention. Fig. 96 is a plan view of a transverse electric field type thin film semiconductor substrate of the present invention. Fig. 97 is a cross-sectional view of a unit pixel of a transverse electric field type thin film semiconductor substrate of the present invention. Fig. 98 is a cross-sectional view of a unit pixel of a transverse electric field type thin film semiconductor substrate of the present invention. Fig. 99 is a cross-sectional view of a unit pixel of a transverse electric field type thin film semiconductor substrate of the present invention. Fig. 100 is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. F 0-Figure: This is a plan view of the thin-film semiconductor device of the transverse electric field method of the present invention. The first 0-Fig. Is a cross-sectional view of a unit element of a transverse electric field type thin film semiconductor substrate of the present invention. Fig. 102 is a cross-sectional view of a unit element of a transverse electric field type thin film semiconductor substrate of the present invention. 25 A7
五、發明說明(j ) 經 濟 部 智 慧 財 產 局 員 工 合 作 社 印 製 第~ 0四圖:係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 第~ 0五圖:係本發明的橫電場方式薄膜半導體基板的單 位畫素的剖面圖。 第一 0六圖:係本發明的橫電場方式薄臈半導體元件的平 面圖。 第—0七圖:係本發明的橫電場方式薄膜半導體元件的平 面圖。 (二)圖號部分: (1 ) ···玻璃基板 (2 ) ···掃瞄線(閘極電極) (3 ) .··掃瞄線端子部 (4 ) · · ·閘極絕緣膜 (5 )…薄膜半導體層(Non-dope(無摻雜)層) (6 ) ···摻雜磷的η +半導體層 (7 ) ···影像信號配線 (8 )…汲極電極 (9 )…影像信號配線端子部 (1 0)…晝素電極接續孔 (1 1 )…掃瞄線端子部接續孔 (1 2)…影像信號配線接續孔 (1 3 )…掃瞄線端子部驅動ic接合電極(透明電極) (1 4)…畫素電極(透明電極) (1 5 )…影像信號配線端子部驅動π接人雷技, σ电極(透明 26 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 536655 A7 五、發明說明(<) 電極) 護層膜 k電場方式液晶驅動電極(晝素電極) 橫電場方式共通電極 掃瞄線端子部驅動1(;接合電極(金屬電極) 掃瞄線下層絕緣膜V. Description of the invention (j) Printed by the Intellectual Property Office of the Ministry of Economic Affairs and the Agency for Cooperatives. Figures ~ 0 4: This is a cross-sectional view of a unit pixel of a horizontal electric field type thin film semiconductor substrate of the present invention. Fig. 0 ~ 5: A cross-sectional view of a unit pixel of a lateral electric field type thin film semiconductor substrate of the present invention. Fig. 106 is a plan view of a thin-field semiconductor device using a transverse electric field method according to the present invention. Fig. 0-7 is a plan view of a transverse electric field type thin film semiconductor device according to the present invention. (2) Part of drawing number: (1) ··· Glass substrate (2) ··· Scan line (gate electrode) (3). ·· Scan line terminal (4) ··· Gate insulating film (5) ... Thin-film semiconductor layer (Non-dope (non-doped) layer) (6) ··· Doped η + semiconductor layer (7) ··· Video signal wiring (8) ... Drain electrode (9 ) ... Video signal wiring terminal section (1 0) ... Day element electrode connection hole (1 1) ... Scan line terminal connection hole (1 2) ... Video signal wiring connection hole (1 3) ... Scan line terminal driver ic bonding electrode (transparent electrode) (1 4) ... Pixel electrode (transparent electrode) (1 5) ... Video signal wiring terminal part drives π-connected lightning technology, σ electrode (transparent 26) This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 536655 A7 V. Description of the invention (<) Electrode) Protective film k electric field type liquid crystal drive electrode (day element electrode) Transverse electric field type common electrode scan line terminal driver 1 ; Bonding electrode (metal electrode) insulating film under the scanning line
Etchingstopper 絕緣膜 光罩用石英玻璃基板 半透光罩區域 半透光膜區域 光罩金屬(Cr或Mo) 衫像h號配線光罩完全遮蔽區域 汲極電極光罩完全遮蔽區域 電晶體通道部半透光區域 晶體通道部半透光膜 光阻U V曝光完全遮蔽區域的顯影後的膜厚 光阻U V曝光半透光區域的顯影後的膜厚 光阻 經濟部智慧財產局員工消費合作社印製 (16). (17) . (18) . (19) . (20) . (21). (22). (23) . (24) . (25) . (26) . (27) . (28) . (29) . (30) . (31) . (32) . (33) . (34) . (35) . (36) . (37) . (38) ., 第1層掃猫線(铭或铭合金) 第2層掃礙線(上蓋(帽)電極) 第1層共通電極(鋁或鋁合金) 第2層共通電極(晝素共通電極) •第2層下部掃瞄線 •第2層上部掃瞄線 ‘紙張尺度適用中國國家標準(CNS)A4規格(210 X : 27 五、發明說明(4 ) ((二)··.第2層下部共通電極(畫素共通電極) ...第2層上部共通電極(畫素共通電極) 丄)···下層掃瞄線 (4 ? ;·••銅或銅合金掃瞄線 (4 3 ) ···上蓋(帽)閘極電極 (4 4 ) ···鋼或銅合金共通電極 (4 5 ) ···下層共通電極 4 6 )···上盍(帽)共通電極(晝素共通電極) (4 7 )···掃瞄線與共通電極的切斷位置 (4 8) · · ·影像配線的切斷位置 (4 9 ) ···下層影像信號配線 (5 0 ) ···低抗阻影像信號配線 (5 1 ) ···上蓋(帽)影像信號配線 (5 2 ) ."Etchingstopper 影像信號配線 (5 3 )…閘極絕緣膜局部沈積區域 (5 4 ) ···護層膜局部沈積區域 (5 5 )…靜電氣對策用保護主動式元件 (5 6)…有效晝素區域周邊共通電極 (5 7 )...液晶Cell框膠線 (5 8 )…薄膜電晶體通道部钱刻區域 (5 9 )…有效畫素區域周邊半導體層 A…閘極絕緣膜沈積境界到掃瞄線端子部末端的距 B…護層膜沈積境界到掃瞄線端子部末端的距離 C…閘極絕緣膜沈積境界到靜電氣對策用保護主動式元件 28 訂 經 濟 部 智 慧 財 產 局 ‘離 消 費 合 作 社 印 製 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 536655 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 in A7 、發明說明(j?) 的接合端子部末端的距離 (6 0 ) ···共通電極端子部 —一如第二圖、第五十圖至第五十五圖所示,係本發明第 :貫施例的剖面圖及平面圖。主要係於一玻璃基板⑴ =面依序形成掃猫線(2)(閘極電極)後,局部的沈積 絕緣臈(4)、非晶料導體膜(5)及n+非晶石夕膜 6),又沈積後的掃瞄線端子部(3)將金屬電極露出 ’而為了同時形成影像信號配線(7)、液晶驅動電極( 1 7 及用以接合掃瞄線端子部(3 )的金屬電極(工9 )’係以缝(Sputtering)方式沈積金屬膜。用以如第 三十圖及手段1 1、1 3所記載的方法,僅以—次的光罩 工私,形成薄膜電晶體元件(5 )的通道部,且除去通道 部的多餘的金屬膜及n+層。此製程所使用的光罩係如第二 十七圖及第二十八圖所示,其透光量三階段以上變化。該 光罩的電晶體元件通道部的剖面圖係如第二十五及第二十 $圖所示,利用此光罩進行曝光後的正光阻剖面構造係如 第二十九圖所示。薄膜半導體所使用的曝光裝置的解析度 最高為2〜3//m程度,因此製作如第二十五圖,第二十= 圖所示的光罩構造時,使用解像力1/1〇到1/5程度的成 形(Pattern)以調整平均的透光量。以線寬〇2〜^5# 程度,線間空隙0.5〜;程度在光罩上形成半透光區域 (23)。如為第二十六圖及第二十八圖所示形式的光罩 時,可利用矽氮化膜作成半透光區域膜(24),主要係 .«裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁)Etchingstopper Quartz glass substrate for insulating film mask Semi-transparent mask area Semi-transparent film area mask Metal (Cr or Mo) Shirt like h-number wiring mask Completely shielded area Drain electrode mask Completely shielded area Transistor channel part half Semi-transparent film photoresist UV exposure in the crystal channel portion of the transparent area completely shields the developed film thickness of the photoresist in the semi-transparent area. Printed by the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 16). (17). (18). (19). (20). (21). (22). (23). (24). (25). (26). (27). (28) (29). (30). (31). (32). (33). (34). (35). (36). (37). (38)., The first layer of cat line (Ming Or ming alloy) The second layer scan line (top cover (cap) electrode) The first layer common electrode (aluminum or aluminum alloy) The second layer common electrode (daylight common electrode) • The second layer lower scanning line • the second Scanning line of the upper layer 'paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X: 27 V. Description of the invention (4) ((II) ...) Common electrode of the lower layer of the second layer (pixel common electrode) .. .Common electrode on the second layer (pixel common electrode) ) 丄) ··· Lower scan line (4?; ··· Copper or copper alloy scan line (4 3) ···················································· Common to steel or copper alloys Electrode (4 5) ... Common electrode of the lower layer 4 6) ... Common electrode of the upper (cap) (common electrode of the day) (4 7) ... The cut-off position of the scanning line and the common electrode (4 8 ) ··· Cut position of video wiring (4 9) ··· Lower video signal wiring (5 0) ··· Low impedance video signal wiring (5 1) ··· Upper cover (cap) video signal wiring (5 2). &Quot; Etchingstopper image signal wiring (5 3) ... local deposition area of gate insulation film (5 4) ... local deposition area of cover film (5 5) ... protective active element for static electricity countermeasures (5 6 ) ... Common electrodes around the effective pixel area (5 7) ... Liquid crystal Cell frame adhesive wire (5 8) ... Thin film carved area (5 9) of the thin film transistor channel section ... Semiconductor layer A around the effective pixel area ... Gate The distance from the insulation film deposition boundary to the end of the scanning line terminal B ... The distance from the cover film deposition boundary to the end of the scanning line terminal C ... The gate insulation film deposition boundary to the static electricity countermeasures Active element 28 Order Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed from a paper of a consumer co-operative society Applicable to China National Standard (CNS) A4 (210 x 297 mm) 536655 Printed by the Consumer Intellectual Property Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs in A7, Invention Explanation (j?) The distance of the end of the joint terminal part (60) ··· Common electrode terminal part—as shown in the second, fifty, and fifty-fifth figures, it is the first embodiment of the present invention: Examples of cross-sectional and plan views. Mainly on a glass substrate ⑴ = after the cat line (2) (gate electrode) is sequentially formed on the surface, the local insulation 臈 (4), amorphous conductor film (5), and n + amorphous stone film 6 are deposited locally. ), And the deposited scanning line terminal portion (3) exposes the metal electrode, and in order to form the image signal wiring (7), the liquid crystal driving electrode (17, and the metal used to join the scanning line terminal portion (3) at the same time) The electrode (work 9) 'is a method of depositing a metal film by the method of slitting. Using the method described in FIG. 30 and the methods 11 and 13 to form a thin-film transistor using only one photomask. The channel part of the element (5), and the excess metal film and n + layer are removed from the channel part. The photomask used in this process is shown in Figure 27 and Figure 28, and its light transmission amount is three stages The above changes. The cross-sectional view of the transistor element channel portion of the photomask is shown in Figures 25 and 20, and the positive photoresistance cross-section structure after exposure using this photomask is shown in Figure 29. The resolution of the exposure device used for thin-film semiconductors is about 2 ~ 3 // m, so it is produced as the twenty-fifth Figure, twentieth = In the photomask structure shown in the figure, a pattern with a resolution of about 1/10 to 1/5 is used to adjust the average light transmission. With a line width of 〇2 ~ ^ 5 #, The gap between the lines is 0.5 ~; a semi-transparent area (23) is formed on the photomask. For the photomasks shown in Figures 26 and 28, a silicon nitride film can be used to make a semi-transparent Light area film (24), mainly. «Installation -------- Order --------- (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 536655 A7 -------B7___ 五、發明說明) 以改變化矽與氮的成分比率,自由調整紫外線光(uv)的穿 透量。如第二十九圖所示,顯示未曝光部分的正光阻膜厚 (3 0)為ι·2〜2. 0//m,而已曝光的半透光區域的正光 阻骐厚(3 1 )為0.05〜〇.2_左右,其主要係於n+層 的金屬層以濕式餘刻加工,留下必要部位的金屬層,接 著可以稀釋的氟硝酸採濕式餘刻除去n+層及無離子注入之 半導體層,也可以乾式蝕刻除去n+層及無離子注入之半導 體層,接著作為薄膜電晶體元件通道部的半透光區域膜( 2 4 )所殘留薄薄的正光阻可以電漿Ashing處理除去, 該通道部的金屬層及n+層以之前相同的濕式蝕刻及乾式蝕 刻除去。最後,將護層膜作局部性的部分式沈積,以完成 主動式元件基板。於全工程中僅利用二次的光罩工程。 又如第六圖所示,係本發明第二實施例的剖面圖,直 係如第-實施例中最後將護層膜(1 6)沈積在基板 )的整個表面I,開設掃瞒線端子部的接續孔製造方法, 在整個方法中只須利用三次光罩工程。 如第四圖所示’係本發明第三實施例的剖面構造,在 第-實施例時,掃瞒線(2 )及共通電極(工8) 同-金屬材料以-次的光罩工程同時形成;在本實施例中 ’在H始先形成共通電極後,即局部性的沈積掃瞒線下 層絕緣膜(20),其光罩工程於全工程中共三次,來自 共通電極(18)與掃I線(12)的圖形(Pattern) 不良所造成的短路可大量減少,故良率亦可大幅的提高。 如第五圖所示,係本發明第四實施例的剖面構造, (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 536655 A7 ------- B7___ V. Description of the invention) To change the composition ratio of silicon and nitrogen, freely adjust the penetration of ultraviolet light (uv). As shown in the twenty-ninth figure, the positive photoresist film thickness (3 0) of the unexposed portion is ι · 2 ~ 2. 0 // m, and the positive photoresist thickness of the exposed semi-transmissive area is thick (3 1) It is about 0.05 ~ 0.2_. It is mainly based on the wet processing of the metal layer of the n + layer, leaving the necessary metal layer, and then the diluted fluoric nitric acid can be used to remove the n + layer and no ions. The implanted semiconductor layer can also be dry-etched to remove the n + layer and the semiconductor layer without ion implantation. The thin positive photoresist remaining in the semi-transparent region film (2 4) of the channel portion of the thin film transistor element can be plasma Ashed. The metal layer and the n + layer of the channel portion are removed by the same wet etching and dry etching as before. Finally, the protective film is partially deposited locally to complete the active element substrate. In the whole project, only the secondary mask project is used. As shown in the sixth figure, it is a cross-sectional view of the second embodiment of the present invention. As shown in the first embodiment, the cover film (16) is finally deposited on the entire surface I of the substrate, and a concealed wire terminal is opened. In the method of manufacturing the connection hole of the external part, only three photomask processes are required in the entire method. As shown in the fourth figure, 'It is the cross-sectional structure of the third embodiment of the present invention. In the first embodiment, the concealment line (2) and the common electrode (work 8) are the same as the mask process of the metal material at the same time. Formation; in this embodiment, after the common electrode is first formed at H, that is, the lower layer insulating film (20) is locally deposited, the photomask project is performed three times in the whole project, from the common electrode (18) and the scan The short circuit caused by the bad pattern of the I line (12) can be greatly reduced, so the yield can be greatly improved. As shown in the fifth figure, it is a cross-sectional structure of the fourth embodiment of the present invention, (please read the precautions on the back before filling this page)
ϋ n ϋ I ^-r°J «1_ι ϋ ·ϋ .^1 I # 30ϋ n ϋ I ^ -r ° J «1_ι ϋ · ϋ. ^ 1 I # 30
五、發明說明(1) 第三實施例相同,其掃晦線( 同時形成,一關私春# _ /、通電極(1 8 )不 成共通電極(:L 8 )。w I私的最後再开乂 此,來自-通雷i/'Λ 於全工程中共三次。藉 ”皁*望义所""成短路可大量減少,因此可大幅的提 摆 口 /、通電極的材質可自由選 擇之故,使製程的自由度變大。 ^七:所示,係本發明第五實施例的剖面構造。由 四員知例所不者均為橫電場方式的液晶顯示模式 ^而本實施例則適用於縱電場方式的液晶顯示模式(tn方 式、垂直配向方式、強锋雪 广〜七 5$透笔方式、反強誘電方式)。其於 形成影像信號配線(7)及汲極電極(8),並沈積護層 膜(16),該汲極電極(8)上的護層膜(16)在開 "又接’孔(1 Q )後即予除去,最後再形成透明的畫素電 極(14)。光罩工程於全工程中共四次。 如第五十六至六十一圖所示,係本發明第六實施例的 平面圖,其剖面圖則與第三圖及第六圖相同。與第一至第 五實施例相異之處,在於不使用第三十圖所示製程,為了 同柃形成影像信號配線(7)、液晶驅動電極(丄7)及 掃瞄線端子部接合金屬(i 9 ),其在金屬膜沈積、成形 (Pattern)後,再除去薄膜電晶體元件的通道部區域上殘 留的金屬膜及n+層。與其相反的,本實施例中,係在沈積 金屬膜後,除去薄膜電晶體元件通道部區域的金屬膜及n+ 層,之後再成形(Patterning)影像信號配線(7 )、液晶 31 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------·!裝— (請先閱讀背面之注意事項再填寫本頁) . 經濟部智慧財產局員工消費合作社印制衣 536655 五、發明說明㈠Ο) 驅動電極(17)及掃晦線端子部接合金屬(19)。 —如第八圖、第六十八至七十三圖所示,係本發明第七 貫施例的剖面圖與平面圖。主要是在掃猫線(2)成 ’將閘極絕緣膜(4)、非晶⑦半導體膜(5)與η+非晶 石(膜(6 )如第九十二、九十三圖所示般,作局部性的部 ^沈積。沈積後的掃瞒線端子部(3 )露出金屬電極。接 著為了同時形成影像信號配線(7)及液晶驅動電極q 7 ),用濺鍍(Sputtering)方式沈積金屬膜。金屬膜係 以濕式蝕刻或乾式蝕刻成形(Patterning)加工,無金屬膜 部分的Π+層也同樣的以濕式蝕刻或乾式蝕刻除去,之後於 基板(1)上全面沈積護層膜(16),為了分離薄膜電 晶體元件的通道部、影像信號配線(7 )及液晶驅動電極 (1 7 ),將除去多餘區域的護層膜(丄6 )及非晶矽半 導體膜(5)。前述實施例採用的光罩工程於全工程中共 三次。 經濟部智慧財產局員工消費合作社印製 第九圖係本發明第八實施例的剖面圖,主要係將間極 絕緣膜(4 )如第九十二、九十三圖所示般作局部性的部 分沈積後’於基板(1 )上全面沈積非晶;5夕半導體膜(5 )與n+非晶矽膜(6 ),接著形成影像信號配線(7 )及 液晶驅動電極(1 7 )後’於基板(1 )全面沈積護層膜 (16),之後為了分離薄膜電晶體元件的通道部、影像 信號配線(7 )及液晶驅動電極(1 7 ),將除去多餘區 域的護層膜(1 6 )及非晶矽半導體膜(5 )。此時,覆 盍掃瞒線端子部(3 )電極之護層膜(1 6 )及非晶;^半 32 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 五、發明說明($/) 導體膜(5)亦予同時除去,而護層m (16)非全面沈 積,僅局部性的部分沈積亦可。 々一如第十圖所不,係本發明第九實施例的剖面圖,與 第三實施例相同開始先形成共通電極(工8 )後,局、 部性的,積掃晦線下層絕緣膜(2〇),之後的製程步驟 七^例完全相同,其於全卫程中使用的光罩工程共 4次’藉此,纟自共通電極(丄8 )與掃瞄線⑵的: 形(Pattern)不良的狀況將大量減少,故可大幅提高良率 如第十二圖所示,係本發明第十實施例的剖面圖,兔 第四實施例相同,最後才形成共通電極(18), _、 f於:本實施例中之護層膜(1 6 )未被覆蓋於有效畫$ 區域全面’故露出非晶梦層的加卫剖面,因此露出的 =層剖面有以Ashing等處理氧化而使之成為絕緣膜的= 一如第十圖、第七十四至七十九圖所示,係、本發 -實施例的剖面圖及平面圖,本實施例係適用於 式的液晶顯示方式(TN #式、垂直配向方式、強: 及反強誘電方式)。其首先形成掃瞄線(2 ),其後如f 九十二、九十三圖所示般,以局部性的部分沈積方 第 積形成閘極絕緣膜(4)、非晶矽半導體膜(5) x ,沈 晶矽膜(6 ),接著全面性的沈積金屬膜,及+非 (Patterning)影像信號配線(γ )與汲極電極(8 )、形 除去已無金屬膜區域的η+非晶矽膜(6 )後,於基板,又 536655 經濟部智慧財產局員工消費合作社印制衣 A7 B7 五、發明說明(j〆) )全面上沈積護層膜(16),接著為了分離薄膜電晶體 元件的通道部、影像信號配線(7)及汲極電極(8), 除去多餘區域的護層膜(1 6 )及非晶矽半導體膜(5 ) ,此時並同時除去汲極電極(8 )上多餘的護層膜(工6 )及掃瞄線端子部(3 )電極上多餘的護層膜(i 6 )及 影像信號配線端子部(9 )電極上的多餘護層膜(i 6 ) ,最後再形成-透明的畫素電極(14)。而前述方法在 全工程中採用的光罩工程共為四次。如第八實施例所示, 於基板(1 )全面沈積非晶石夕半導體膜(5 )及n+非晶石夕 膜(6 )的方法亦可能。 如第十三圖、第六十四至六十七圖、第九十七圖、第 -0 0至-0-圖所示,乃本發明第十二實施例的剖面圖 與平面圖。其於基板(工)上形成掃瞒線(2)後,如第 九十二及九十三圖所示般,以局部性的部分沈積方式沈積 形成該閘極絕緣膜(4)、非晶石夕半導體膜及_ 日②石夕膜,接著於基板(1)上全面沈積金屬膜,成 形影像h號配線(7)及液晶驅動電極(17),再除去 無金屬部分的n+層及非晶矽層後,於基板⑴上全面沈 積透明導電膜或鈦系的金屬膜(13),接著為了電氣性 的^離影像信號配線(7)及液晶驅動電極(1了),除 去薄膜電晶體元件通道部分的金屬層及n+層非晶石夕層,最 後=局部性的沈積護層膜(16)。其中如第九十七圖、 第厂0 0及-〇-圖所示,乃在形成影像信號配線(u 及極電極後’於基板(U上全面沈積透明導電膜 -------------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 34 536655 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明())) 夸 ^的金屬膜(1 3 )或高融點金屬的矽化物化合物後,成 形影像信號配線(7 )及液晶驅動電極(1 7 )之後,再 除去通道部分多餘的金屬層及n+層之後局部沈積的護層膜 (16)。 如第十四圖所示,係本發明第十三實施例的剖面圖, ^沈積護層膜(1 6 )為止的步驟與第十二實施例完全相 同’於本實施例中’在基板(1 )上全面沈積護層膜(1 6 )後’在掃瞒線端子部(3 )及影像信號配線端子部形 成接續孔(11),並除去端子部上沈積的多餘護層膜 16)。 如第九十八圖所示,係本發明第十四實施例的剖面圖 。與第四實施例相同,係以不同時方式分別形成掃瞎線( 2 )與共通電極(;[8 ),一開始先形成掃猫線(2 )後 ’製程的最後再形成共通電極(18)。其在全工程中採 用的光罩工程共四次。 如第九十九圖所#,係本發明第十五實施例的剖面圖 、。與第三實施例相同,係以不同時形成掃瞄線(2 )與共 通電極(18),一開始先形成共通電極(丄8)後,局 部性的沈積掃晦線下層絕緣貞(2〇) 述方法於全二 程中共使用四次光罩工程。 〃如^十五圖、第六十二至六十七圖所示,係本發明的 第十六實施例的剖面圖與平面圖,其於形成掃晦線( 後,係如第九十二及第大+ 一同故一 弟九十二圖所不般,以局部性的部分 沈積方式形成閘極絕緣膜(4)、非晶石夕半導體 -------------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 35 536655 A7 五、發明說明 n+非Βθ_膜(6 ) ’接著在基板(1 )上全面沈積金 膜,以形成影像信號配飧r ^ n w人 (7)及沒極電極,隨後在基板 i面沈積透明導電膜,再形成影像信號配線 晝素電極(14),接著除去薄膜電晶體的通道 /、夕=金屬層及n+層’最後局部性的沈積護層膜(1 本λ〜例相於縱電場方式的液晶顯示方式(τ 式、二直配向方式、強誘電液晶方式、反強誘電液晶方式 )别逑於全工程中計採用三次光罩工程。 如第十六圖、第一 〇六 0七圖及第八十二至八十 經濟部智慧財產局員工消費合作社印製 k 五圖係本發明第十七實施例的剖面圖與平面圖。 其於形成掃猫線(2)後,係如第九十二及第九十三 圖斤丁般以局部性的部分沈積方式形成閘極絕緣膜(4 ^非晶石夕半導體膜(5) “非晶賴(6),接著成 形非晶石夕膜形成電晶體的通道部分,此後於基板(丄)上 :面沈積金屬膜,形成影像信號配線(7)及液晶驅動電 β (17)除去電阳體的通道部分的η+層後,最後局部 性的沈積護層膜(16)。在第十六圖的場合,第―〇六 、-0七圖所示的液晶驅動電極(17),其下部不存在 非晶砍層。 又第一〇二圖及第八十、八十一圖所示液晶驅動電極 ^ 1 7 )㈣下部雖存在非晶石夕㉟,仍可以完全相同的製程 製作。其全工程中共使用三次光罩工程。 如第十七圖、第一〇五圖所示,係本發明第十八實施 例的剖面圖。直到沈積護層m (工6 )為止,其製程步驟V. Description of the invention (1) The third embodiment is the same, and its scan line (formed at the same time, a pass private spring # _ /, the common electrode (1 8) is not a common electrode (: L 8). To open this, from -Tong Lei i / 'Λ in the whole project three times. By "SO * Wang Yisuo" short circuit can be greatly reduced, so the material of the pendulum opening and the electrode can be freely lifted. The reason for choice is to increase the degree of freedom of the manufacturing process. ^ Seven: Shown is the cross-sectional structure of the fifth embodiment of the present invention. All the examples shown by the four members are liquid crystal display modes of the transverse electric field method ^ and this implementation For example, it is applicable to the liquid crystal display mode of the vertical electric field method (tn method, vertical alignment method, Qiangfeng Xueguang ~ 75 $ pen-through method, anti-strong electric induction method). It is used to form the image signal wiring (7) and the drain electrode (8), and a protective film (16) is deposited. The protective film (16) on the drain electrode (8) is removed after opening " and then connected to a hole (1 Q), and finally a transparent film is formed. Pixel electrode (14). The photomask project has been performed four times in the whole project. As shown in Figures 56 to 61, it is the present invention. The plan view of the sixth embodiment is the same as the third and sixth views. The difference from the first to fifth embodiments is that the process shown in the thirty-first embodiment is not used, and the image signal is formed for the same purpose. After the wiring (7), the liquid crystal driving electrode (丄 7), and the scan line terminal portion are bonded to the metal (i 9), after the metal film is deposited and formed, the remaining portion of the channel portion of the thin film transistor is removed. Metal film and n + layer. In contrast, in this embodiment, after the metal film is deposited, the metal film and the n + layer in the channel region of the thin film transistor element are removed, and then the (Patterning) image signal wiring (7), Liquid crystal 31 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- !! Packing-(Please read the precautions on the back before filling this page ). Printed clothing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 536655 V. Description of the invention ㈠Ο) The driving electrode (17) and the metal wire (19) on the terminal of the scan line.-As shown in Figure 8 The three figures are sectional views of a seventh embodiment of the present invention and The top view is mainly formed by turning the cat wire (2) into the gate insulating film (4), the amorphous semiconductor film (5), and the η + amorphous stone (film (6) such as the ninety-second and ninety As shown in the three figures, local deposition is performed. After the deposition, the terminal portion (3) of the hidden wire is exposed to the metal electrode. Then, in order to form the image signal wiring (7) and the liquid crystal driving electrode (q7) at the same time, sputtering is used. (Sputtering) method to deposit a metal film. The metal film is processed by wet etching or dry etching (Patterning), and the Π + layer without the metal film portion is also removed by wet etching or dry etching, and then on the substrate (1) A cover film (16) is fully deposited on the top, in order to separate the channel portion of the thin film transistor element, the image signal wiring (7) and the liquid crystal drive electrode (1 7), the cover film (丄 6) and the amorphous portion of the unnecessary area will be removed. Silicon semiconductor film (5). The photomask project used in the previous embodiment was used three times in the whole project. The ninth picture printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is a cross-sectional view of the eighth embodiment of the present invention, which mainly uses the interlayer insulation film (4) as shown in Figures 92 and 93 as local After partial deposition, the amorphous layer is fully deposited on the substrate (1); the semiconductor film (5) and the n + amorphous silicon film (6) are formed, and then the image signal wiring (7) and the liquid crystal driving electrode (1 7) are formed. 'The protective film (16) is fully deposited on the substrate (1). In order to separate the channel portion of the thin-film transistor element, the image signal wiring (7) and the liquid crystal drive electrode (1 7), the protective film of the unnecessary area will be removed ( 16) and an amorphous silicon semiconductor film (5). At this time, cover the cover film (16) and amorphous of the electrode of the concealed wire terminal (3); ^ half 32 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5. Description of the invention ($ /) The conductive film (5) is also removed at the same time, and the protective layer m (16) is not completely deposited, and only a partial partial deposition is also possible. (1) As shown in the tenth figure, it is a cross-sectional view of the ninth embodiment of the present invention. After the common electrode is first formed (the same as the third embodiment), the local and partial insulation film is formed. (20), the subsequent process steps are exactly the same, and the photomask project used in the whole health process is 4 times. 'Through this, the common electrode (丄 8) and the scanning line ⑵: shape ( The bad conditions will be greatly reduced, so the yield can be greatly improved. As shown in Figure 12, it is a cross-sectional view of the tenth embodiment of the present invention. The fourth embodiment of the rabbit is the same, and a common electrode (18) is finally formed. _, F in: The protective film (16) in this embodiment is not covered in the effective drawing area, so the Jiawei section of the amorphous dream layer is exposed, so the exposed = layer section is treated with Ashing and other oxidation And make it an insulating film = as shown in the tenth figure, the seventy-fourth to seventy-nineth figures, the cross-sectional view and the plan view of the present embodiment-this embodiment is applicable to the liquid crystal display mode (TN # type, vertical alignment method, strong: and anti-strong electric induction method). It first forms a scan line (2), and then, as shown in Figures 92 and 93, the gate insulating film (4), the amorphous silicon semiconductor film (4), and the amorphous silicon semiconductor film ( 5) x, Shen Jing silicon film (6), followed by a comprehensive deposition of metal film, + + (Patterning) image signal wiring (γ) and drain electrode (8), η + to remove the area without metal film After the amorphous silicon film (6) was printed on the substrate, 536655 printed the clothing A7 B7 of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (j〆)) A protective film (16) was deposited on the entire surface, followed by a separation The channel part of the transistor element, the image signal wiring (7), and the drain electrode (8), the protective film (16) and the amorphous silicon semiconductor film (5) of the unnecessary area are removed. At this time, the drain electrode is also removed. (8) Excessive protective film (i 6) on the electrode of the scanning line terminal (3) and unnecessary protective film (i 6) on the electrode of the video signal wiring terminal (9) i 6), and finally formed a transparent pixel electrode (14). However, the mask method used in the whole method is four times. As shown in the eighth embodiment, a method for depositing an amorphous stone semiconductor film (5) and an n + amorphous stone film (6) on the substrate (1) is also possible. As shown in the thirteenth figure, the sixty-fourth to sixty-seventh figures, the ninety-seventh figure, and the -0 0 to -0- figures, they are sectional and plan views of the twelfth embodiment of the present invention. After forming a cover line (2) on the substrate (work), as shown in Figures 92 and 93, the gate insulating film (4), amorphous Shi Xi semiconductor film and _ day ② Shi Xi film, then fully deposit a metal film on the substrate (1), shape the image h wiring (7) and the liquid crystal drive electrode (17), and then remove the n + layer and non-metal part After crystallizing the silicon layer, a transparent conductive film or a titanium-based metal film (13) is completely deposited on the substrate 接着, and then the thin film transistor is removed for the purpose of electrically separating the image signal wiring (7) and the liquid crystal driving electrode (1). The metal layer of the element channel part and the n + layer of amorphous stone layer, and finally = a locally deposited protective film (16). Among them, as shown in the ninety-seventh figure, the first factory 0 0 and -0-, the transparent conductive film is fully deposited on the substrate (U after the image signal wiring (u and the electrode) is formed ------- ------ Equipment -------- Order --------- (Please read the notes on the back before filling out this page) 34 536655 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention ())) After the metal film (1 3) or the silicide compound of high melting point metal is formed, the image signal wiring (7) and the liquid crystal driving electrode (1 7) are formed, and then the channel is removed. Partially redundant metal layer and n + layer are locally deposited after the protective film (16). As shown in FIG. 14, it is a cross-sectional view of the thirteenth embodiment of the present invention. The steps up to the deposition of the protective film (16) are exactly the same as those of the twelfth embodiment. 1) After fully depositing the protective film (16) on the top surface, a connection hole (11) is formed in the sweeping wire terminal portion (3) and the video signal wiring terminal portion, and the redundant protective film 16 deposited on the terminal portion is removed. As shown in Fig. 98, it is a sectional view of a fourteenth embodiment of the present invention. As in the fourth embodiment, the illiterate line (2) and the common electrode (; [8) are formed separately in different ways. At first, the common cat electrode (2) is formed first, and then the common electrode (18) is formed at the end of the process. ). It has used a total of four mask projects in the whole project. As shown in Figure 99, it is a sectional view of the fifteenth embodiment of the present invention. Similar to the third embodiment, the scanning line (2) and the common electrode (18) are not formed at the same time. After the common electrode (丄 8) is first formed, the underlying insulating layer (20) is locally deposited. The method described above uses a total of four photomask projects during the second pass. As shown in Figure 15 and Figures 62 to 67, it is a cross-sectional view and a plan view of a sixteenth embodiment of the present invention. The first one is the same as the one shown in Figure 92. The gate insulation film is formed by a partial partial deposition method (4), amorphous silicon semiconductor ------------- installation -------- Order --------- (Please read the notes on the back before filling out this page) 35 536655 A7 V. Description of the invention n + non-Βθ_ film (6) 'Next on the substrate (1) Fully deposit a gold film on top to form the image signal distribution 飧 r ^ nw (7) and the electrode without electrode, and then deposit a transparent conductive film on the i-side of the substrate to form the image signal wiring day element electrode (14), and then Remove the thin film transistor's channel /, evening = metal layer and n + layer 'and finally deposit the protective layer film (1 x λ ~ example liquid crystal display mode which is similar to the vertical electric field mode (τ mode, two direct alignment mode, strong induced electricity) Liquid crystal method, anti-power induced liquid crystal method) Don't use the three masks in the whole project, such as the sixteenth figure, one hundred and sixty-seven figure and eighty-second to eighty Printed by the Consumers' Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs, the five pictures are cross-sectional and plan views of the seventeenth embodiment of the present invention. After forming the cat line (2), they are shown in the ninety-second and ninety-third drawings. The gate insulation film was formed by a partial partial deposition method (4 ^ amorphous semiconductor film (5) "amorphous (6)", followed by forming the amorphous channel to form a channel portion of the transistor, and thereafter On the substrate (丄): a metal film is deposited on the surface to form the image signal wiring (7) and the liquid crystal driving electric β (17). After removing the η + layer of the channel portion of the anode, the local protective film (16 ). In the case of the sixteenth figure, the liquid crystal driving electrode (17) shown in FIGS. -06 and -07 does not have an amorphous layer in the lower part. There are also the 102nd figure and the 80th and 8th. The liquid crystal driving electrode shown in Fig. 11 ^ 17) Although there is amorphous stone in the lower part, it can still be made in exactly the same process. There are three photomask projects in its entire project. As shown in Fig. 17 and 105 The figure shows a cross-sectional view of the eighteenth embodiment of the present invention. Until the protective layer m (process 6) is deposited, Which process steps
x 297公釐) -------------Λ Μ--------^--------- (請先閱讀背面之注音Ρ事項再填寫本頁) # 536655 發明說明) 與第十七實施例完全相同,於本實施例中,在基板(丄) 上全面沈積護層膜(1 6 )後,係在掃猫線端子部(3 ) 及影像信號配線端子部(9 )上形成接續孔(工工)後, t除去端子部上所沈積多餘的護層臈(16)。而前述製 程步驟於全工程共使用四次光罩工程。 如第十人圖及第三圖所示t係本發明第十九實施 =面圖。與第三實施例相同,係不同時形成掃猫線( %與共通電極(18),—開始先形成共通電極(18 =,即局部性的沈積掃晦線下層絕緣膜(20),其餘 的衣程與第十八實施例相同。 、 罩工程。在第十八圖的場合中,;:ΓΓ 次光 部不存在非晶石夕層,第電極下 17)的下部存在非晶… 電極( 示構造仍可以完全相同的製程製作。二圖所 如第十九圖及第一0四圖所示, 例的剖面圖。與第四實施例相同1十實施 極(1 8 )係不同時形成,其一開始 2 I、共通電 後,於製程步驟的最後再形成共通‘極二=線(2) 程中共使用四次光罩工程。而在 8),其全工 動電極(1 7)的下部不存在非圖的場合,液晶驅 合,液晶驅動電極(17)的第—〇四圖的場 九圖與第-0四圖所示構造仍可夕層;但第十 如第二十圖及第八十六至九十同的製程製作。 一十一實施例的剖面圖與平面圖。 不,係本發明第 b氏張尺度 鮮㈣x 297 mm) ------------- Λ Μ -------- ^ --------- (Please read the note on the reverse side before filling in this Page) # 536655 Description of the invention) Exactly the same as the seventeenth embodiment. In this embodiment, after the protective film (16) is fully deposited on the substrate (丄), it is attached to the cat wire terminal portion (3) and After forming a connection hole (worker) in the video signal wiring terminal portion (9), t remove the excess protective layer (16) deposited on the terminal portion. The aforementioned process steps used a total of four mask processes throughout the project. As shown in the tenth figure and the third figure, t is a nineteenth embodiment of the present invention. It is the same as the third embodiment, except that the cat line (% and the common electrode (18) are not formed at the same time, the common electrode (18 = is formed first, that is, the underlying insulating film (20) is locally deposited, and the rest The dressing process is the same as in the eighteenth embodiment. In the case of the eighteenth figure, there is no amorphous stone layer in the ΓΓ sub-light part, and there is amorphous in the lower part of the electrode ... The electrode ( The structure shown can still be made in exactly the same process. The second figure is a cross-sectional view of the example shown in Figure 19 and Figure 104. The same as the fourth embodiment, the ten implementation pole (18) is not formed at the same time. At the beginning, after 2 I and common power-on, a common 'pole two = line (2) is formed at the end of the process step. A total of four photomask processes are used in the process. And in 8), its full-motion electrode (1 7) Where there is no non-graph in the lower part, the liquid crystal is driven, and the structure shown in the ninth figure and the fourth figure of the -0th figure of the liquid crystal driving electrode (17) can still be a layer; but the tenth is like the twentieth Figures and the eighty-sixth to ninety-same processes. Sectional and plan views of the eleventh embodiment. Zhang's first b-scale fresh (iv)
請 先 閱 讀 背 & 之 注 意 事 項 再_ 填擊 ί裳 頁I 訂 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 536655 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(4) 當掃瞄線(2 )形成後,於形成掃瞄線(2 )後,係 如第九十二及第九十三圖所示般,以局部性的部分沈積方 式形成閘極絕緣膜(4 )、非晶矽半導體膜(5 )及蝕刻 停止膜(Etchingstopper) ( 2 1 ),沈積後的掃瞄線端子 部(3)露出其金屬電極,接著如第八十六、八十七圖的 平面圖所不掃瞄線(2 )(閘極電極)的内側部分僅在為形 成電晶體通道部之區域留下蝕刻停止膜(Etchingst〇pper) (21),在其他的區域,除了有效晝素區域周邊半導體 層(5 9 )外,其他的钱刻停止膜(EtchingSt〇pper)膜全 部除去,接著為了得到歐姆接觸,再局部性的沈積n+非晶 矽層或n+微晶質矽層。另僅有效晝素區域及靜電對策用保 口蒦電日日體區域實施於IonShowerDoping或 Ion Imp lan tat ion(離子注入)也可得到歐姆接觸;之後為 了形成影像“號配線(7 )及液晶驅動電極(1 7 )於基 板(1 )上全面沈積金屬膜,而在影像信號配線(7 )及 液晶驅動電極(1 7 )成形後除去多餘的n+層及非晶矽層 ,最後再局部性的沈積護層膜(16)。於本製程中,最 後的護層膜(1 6 )非絕對的必要,故該護層膜工程可予 省略。而前述製程於全工程中共使用三次光罩工程。 如第二十一圖所示,係本發明第二十二實施例的剖面 圖’直到沈積護層膜(1 6 )為止的製程步驟均與第二十 一實施例完全相同,於本實施例中,在基板(1 )上全面 沈積護層膜(1 6 )後,在掃瞄線端子部(3 )與影像信 號配線端子部(9 )上形成接續孔(1 1 ),而將端子部 38 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 0Please read the notes on the back & before you fill out the page of I. Order I printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 536655 A7 B7 printed by the Consumer ’s Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs After the scanning line (2) is formed, after forming the scanning line (2), the gate insulating film (4) is formed in a partial partial deposition manner as shown in Figures 92 and 93. , An amorphous silicon semiconductor film (5) and an etch stopper (2 1), the deposited scanning line terminal portion (3) exposes its metal electrode, and then the plan views as shown in Figures 86 and 87 The inner part of the scanning line (2) (gate electrode) leaves an etching stopper (Etchingstoopper) (21) only in the region where the transistor channel portion is formed. In other regions, except for the effective daylight region Except for the peripheral semiconductor layer (59), all other Etching Stop films are removed, and then in order to obtain an ohmic contact, an n + amorphous silicon layer or an n + microcrystalline silicon layer is locally deposited. In addition, only the effective daylight region and the static protection countermeasures of the electric solar heliosphere region are implemented in IonShowerDoping or Ion Imp lan tat ion (ion implantation), and ohmic contact can also be obtained. The electrode (1 7) fully deposits a metal film on the substrate (1), and after the image signal wiring (7) and the liquid crystal drive electrode (1 7) are formed, the excess n + layer and the amorphous silicon layer are removed, and finally the localized Deposit the protective film (16). In this process, the final protective film (16) is not absolutely necessary, so the protective film project can be omitted. The aforementioned process used a total of three photomask projects in the whole process. As shown in the twenty-first figure, it is a cross-sectional view of the twenty-second embodiment of the present invention. The process steps until the protective film (16) is deposited are exactly the same as the twenty-first embodiment. In this embodiment, After the protective film (16) is fully deposited on the substrate (1), a connection hole (1 1) is formed in the scanning line terminal portion (3) and the video signal wiring terminal portion (9), and the terminal portion is formed. 38 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the back of the precautions to fill out this page) 0
1111111 I I I I I — II #- 536655 五、發明說明(y) 上沈積多餘的護層膜(1 6)险土 ^ ϋ」除去。其於全工程中共使用 四次光罩工程。 π Τ /、1之用 如第二十二圖所示,係本發 — 1¾ . _ _ ^ 第一十二貫施例的剖面 圖,與弟三貫施例3相同,掃瞄魂 0 ^ , ▼田線(2 )及共通電極(i 8 )係不同時形成,jl传弁带忐 八你无形成共通電極(1 8 )後,再 局部性的沈積掃瞄線下層絕緣膜Γ 锋L — 啄胰Q 2 〇),其餘的製程與 弟二Η 貫施例相同,全工鞋Φ ±L社m 柱宁共使用四次光罩工程。 如第二=三圖所示,係本發明第二十四實施例的剖面 圖。與第四貫施例相同,掃瞄線(2 )及共通電極“ 8 )係不同時形成,其先形成掃瞒線(2 )後在製程的最後 形成共通電極(18)。全工程中計使用四次光罩工程。 如第二十四圖所示,係本發明第二十五實施例的剖面 圖。本實施例適用於縱電場方式的液晶顯示方式(tn方式 垂直配向方式、強誘電液晶方式及反強誘電液晶方式) 。其在形成影像信號配線(7 )及汲極電極(8 )後,於 基板(1 )上全面沈積透明導體膜,形成透明畫素電極( 14)。之後局部性的沈積護層膜。光罩工程於全工程共 4次。 如第二十一至三十四圖所示,係本發明的第二十六實 施例的平面圖。 對於顯示一晝素,薄膜電晶體的閘極電極(2 )被形 成為二道且互相平行,薄膜電晶體的通道(Channel)區域 也被形成為^一道且互相平行(重疊於前述閘極電極(2 ) 上的斜線部分),該汲極電極(8 )則被集中為一條,而 39 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) 請 先 閱 讀 背 面 意 事 項 填響 ί裝 頁 I w I I I I I I 訂 經濟部智慧財產局員工消費合作社印製 536655 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 B7 五、發明說明()/) 連接到液晶驅動電極(圖中未示)。而前述方法可適用於 第三圖、第八圖、第十三圖、第十六圖及第二十圖所示形 式的薄膜電晶體元件。依此構造即使發生閘極電極與汲極 電極的對位偏移(MissAlignment),該汲極電極的容量幾 乎不會產生變化。 如第二十五至三十圖所示,係本發明第廿七實施例的 剖面圖與平面圖。其中第二十五圖所示者,係利用金屬材 料(2 5 )製造光罩半透光區域(2 3 )的實施例,其適 用於製作電晶體通道區域的光罩實施例,如任何可均勻控 制通道區域uv光線的透光量之形狀(Pattern)均可。又第 二十六圖所示,係在光罩用石英玻璃基板(2 2 )上沈積 可將UV光均勻的僅吸收必要量之半透光膜(2 4 )的光 罩剖面圖。作為半透光膜(2 4 )的材質,以電漿CVD裝 置所能沈積的氮化膜為佳,藉以改變Ml、I、NH3的混合 比,而可自由且均勻的控制UV光的吸收量,即使長時間 的照射UV,只要該半透光膜(2 4 )對ϋν的吸收量不變 即可。又如第二十八圖所示,係υν吸收膜適用於電晶體 的通道區域時的光罩的實施例,其係於用以分別製作影像 信號配線及汲極電極的光罩遮蔽區域間設以製作電晶體通 道部的半透光膜(29)。再如第二十九圖所示,係利用 第一十五、二十六圖所示光罩構造作正光阻曝光顯像時的 正光阻剖面圖,其顯示光罩完全遮蔽及半透光狀態下的正 光阻膜厚(31) (32),經調整半透光量,可自由的 控制半曝光區域及無曝光區域的正光阻膜厚。如第三十九 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- # 536655 A7 五、發明說明(▽) 圖所示,係利用本發明的光罩製程以形成薄膜電晶體元件 時的製程流程。 如第二十五至三十八圖所示,其為本發明第二十八實 施例的剖面圖與平面圖。首先如第三十五圖所示,為了盡 可能的降低掃目苗線的阻抗,乃採用銘系列或鋼系列的材: ,如第-層的掃料(3 3 )及共通電極(3 5 )可採用 鋁或銘合金材料製造,藉此,共通電極之中與液晶驅動電 極成對向的畫素電極(3 6)即使抗阻高也沒問題。又考 慮到配向處理,畫素共通電極(3 6 )及液晶驅動電極的 膜厚盡可能薄較佳。而在使用紹系列材料的場合,為防止 鋁的H^lrock而使用金屬帽,又在使用銅系列的場合, 為了提高與玻璃基板的接著力,下層金屬採用鈦(Ti)系列 或鈕(Ta)系列、鉻系的金屬或高融點金屬的矽化物化合物 。又為了防止氧化,必定要使用金屬帽(34)。鋁系及 銅系的金屬帽係採用高融點金屬系列或高融點金屬的矽化 合物。由第二十六至三十八圖所示的剖面構造可知,與液 晶驅動電極成對向的晝素共通電極(3 6 )比掃瞒線(3 經濟部智慧財產局員工消費合作社印製 3 )之膜厚為薄時,配向處理時的配向密度高,液晶分子 的配向力麦強。又晝素共通電極(36)的膜厚變厚時, 則配向布的尖端運動就無法呈與旋轉方向成平行的直線狀 運動’使液晶分子的配向方向變亂,液晶分子配向性的安 定性變低。 如第二十九圖至四十二圖係本發明第二十九實施例的 剖面圖與平面圖。其中第三十九圖係影像信號配線(7 ) 41 本紙張尺匕適用中國國豕標準(CNS)A4規格(21G X 297公釐 536655 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(+。) 及及極電極(8 )的平面圖,其中沒極電極的剖面圖係如 第四十至四十一圖所示。當影像信號配線橫越過閘極絕緣 膜、非晶矽半導體膜、護層膜的沈積區域邊界時,因下層 膜的熱膨脹係數差異及接著力的差異,於沈積區域邊界發 生影像信號配線的斷線(4 8 )或膜剝落等不良現象。如 本發明,下層影像信號配線(4 9 )採用鈦系列的金屬、 鉻系列的金屬或咼融點金屬的石夕化物化合物,可使前述的 斷線、膜剝落現象大量減少。 如第四十三至四十五圖所示,係本發明第三十實施例 的平面圖。其護層膜(5 4 )的沈積區域比閘極絕緣膜( 5 3 )的沈積區域寬,靜電對策用的保護主動式元件(5 5)被形成在有效晝素的兩邊以上,共通電極(5 6)與 影像k號配線(7 )的接合區域及共通電極(5 6 )與掃 瞄線(2 )的接合區域是存在於閘極絕緣膜(5 3 )的沈 積區域外,而靜電對策用的保護主動式元件(5 5)與前 述接合區域則被護層膜(5 4)所完全覆蓋。 如第四十三圖、第四十五圖所示,當閘極絕緣膜(5 3 )被沈積到影像信號配線的端子部(9 )之下時,影像 信號配線(7)的斷線機會將大幅減少。 從掃瞄線的端子部(3 )末端到閘極絕緣膜(5 3 ) 的沈積邊界的距離(B)及從掃瞄線的端子部(3 )末端到 護層膜(5 4 )的沈積邊界的距離(A)各自需要2ram以上 。同樣的’閘極絕緣膜(5 3 )的沈積邊界到靜電對策用 的保護主動式元件(5 5 )接合端子部末端的距離(C)亦 42 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 0 裝---- # 五、發明說明(4丨) =2咖以上。當前述距離低於2随以下時,閉極絕緣膜 易產提高,容 如第四十六、四十七圖所示,係本發明告 =7。貼合於二片基板的框勝線(”7被局:: 閉極絕緣膜(5 3)的周圍邊境上或閉極絕緣膜( 内。)的沈積區域外’且位在護層膜(5 4)沈積區域以 十四圖及第九十五圖所示,係本發明第三十二 貫面圖。其中第九十四圖係形成掃晦線用的光罩 應旎配線與掃瞄線的交又位置配置有半透光 。又第九十五圖所示光罩,則係用 元件的通道區域,其係於液晶驅動電極及透明書== 交又位置配置有半透光膜(24)。利用此光罩的 曝:二光膜(2 4)設置部分的正光阻媒厚變^ =刻時,使超一成為可能。藉此心 又利用第二十五圖所示的光罩來取代半透光膜 用目^ =果’而共通電極與影像信號配線的交又部亦可適 圖,“與掃晦線又三十三實施例的平面 信號配線(7 )交又的共通電二:與”與影像 位於作局部性沈積的間極絕_ ( 5 j 部分係 536655 A71111111 I I I I I — II #-536655 V. Description of the invention (y) Excessive protective film (1 6) is deposited on the dangerous soil ^ ϋ "and removed. It used a total of four mask projects throughout the project. The use of π Τ /, 1 is shown in the twenty-second figure, which is the present — 1¾. _ _ ^ The cross-sectional view of the twelfth embodiment is the same as the third embodiment of the third embodiment, scanning the soul 0 ^ , ▼ The field line (2) and the common electrode (i 8) are not formed at the same time. After the jl transmission belt has not formed the common electrode (1 8), the underlying insulating film of the scanning line is locally deposited. — Peck pancreas Q 2 〇), the rest of the manufacturing process is the same as that of the second embodiment, full-scale shoes Φ ± L company m Zhu Ning used a total of four mask projects. As shown in the second = three figures, it is a sectional view of the twenty-fourth embodiment of the present invention. As in the fourth embodiment, the scanning line (2) and the common electrode "8" are not formed at the same time. The scan line (2) is formed first, and then the common electrode (18) is formed at the end of the manufacturing process. The photomask process is used four times. As shown in FIG. 24, it is a cross-sectional view of the twenty-fifth embodiment of the present invention. This embodiment is suitable for a liquid crystal display mode of a vertical electric field mode (tn mode, vertical alignment mode, strong induction). Liquid crystal method and anti-strongly induced liquid crystal method). After forming the image signal wiring (7) and the drain electrode (8), a transparent conductor film is fully deposited on the substrate (1) to form a transparent pixel electrode (14). Partially deposited protective film. The photomask project was performed 4 times in the whole project. As shown in Figures 21 to 34, it is a plan view of the twenty-sixth embodiment of the present invention. The gate electrode (2) of the thin-film transistor is formed in two channels and parallel to each other, and the channel region of the thin-film transistor is also formed in one channel and parallel to each other (overlapping the diagonal lines on the foregoing gate electrode (2)) Part), the drain electrode (8) is One is in the middle, and 39 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) Please read the notice on the back and fill in the page I w IIIIII Order printed by the employee ’s consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () /) Connected to the liquid crystal drive electrode (not shown). The aforementioned method can be applied to the third, eighth, tenth Thin-film transistor elements in the form shown in Figures 3, 16, and 20. According to this structure, even if a misalignment between the gate electrode and the drain electrode occurs, the capacity of the drain electrode is almost the same. Changes will occur. As shown in Figures 25 to 30, it is a cross-sectional view and a plan view of the twenty-seventh embodiment of the present invention. The one shown in Figure 25 is a metal material (2 5) to produce light An embodiment of a mask for a semi-transparent region (2 3), which is suitable for making a photomask embodiment of a transistor channel region, such as any shape that can uniformly control the amount of light transmitted by the UV light in the channel region (Patter n) Both. As shown in Figure 26, a photomask is deposited on the quartz glass substrate (2 2) for the photomask, which can uniformly absorb UV light and only absorbs a necessary amount of a translucent film (2 4). Sectional view. As the material of the semi-transmissive film (2 4), a nitride film that can be deposited by a plasma CVD device is preferred. By changing the mixing ratio of Ml, I, and NH3, the UV light can be freely and uniformly controlled. Even if UV is irradiated for a long time, the absorption amount of 透光 ν by the translucent film (2 4) is not changed. As shown in FIG. 28, the υν absorption film is suitable for the transistor. The embodiment of the photomask in the channel area is a semi-transparent film (29) provided between the photomask shielding areas for making the image signal wiring and the drain electrode, respectively, to form a transistor channel portion. As shown in Figure 29, the photoresist cross-sectional view of the positive photoresist during the development of positive photoresist is developed using the photomask structure shown in Figures 15 and 26, which shows that the photomask is completely shielded and translucent The positive photoresist film thickness (31) (32) below, after adjusting the semi-transmittance amount, the positive photoresist film thickness in the semi-exposed area and the non-exposed area can be freely controlled. For example, the thirty-ninth paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page). -------- Order --- ------ # 536655 A7 V. Description of the invention (▽) As shown in the figure, it is the process flow when the photoresist process of the present invention is used to form a thin film transistor element. As shown in the twenty-fifth to thirty-eighth drawings, it is a sectional view and a plan view of the twenty-eighth embodiment of the present invention. First, as shown in Figure 35, in order to reduce the impedance of the sweeping seedling line as much as possible, the materials of the Ming series or steel series are used: such as the first layer of the sweeping material (3 3) and the common electrode (3 5 ) Can be made of aluminum or alloy material, so that the pixel electrode (36) facing the liquid crystal drive electrode among the common electrodes has no problem even if the resistance is high. Considering the alignment process, the film thickness of the pixel common electrode (36) and the liquid crystal driving electrode is preferably as thin as possible. In the case of Shao series materials, a metal cap is used to prevent H ^ lrock of aluminum, and in the case of copper series, in order to improve the adhesion with the glass substrate, a titanium (Ti) series or a button (Ta ) Series, silicide compounds of chromium-based metals or high melting point metals. To prevent oxidation, a metal cap (34) must be used. Aluminum and copper metal caps use high melting point metal series or high melting point metal silicon compounds. From the cross-sectional structure shown in Figures 26 to 38, it can be seen that the common day electrode (3 6) is opposite to the liquid crystal drive electrode (3 6) than the concealed line (3 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 When the film thickness is thin, the alignment density during alignment processing is high, and the alignment force of the liquid crystal molecules is stronger. When the film thickness of the common electrode (36) becomes thicker, the tip of the alignment cloth cannot move in a linear motion parallel to the rotation direction. 'The alignment direction of the liquid crystal molecules is disturbed, and the alignment stability of the liquid crystal molecules is changed. low. Figures 29 to 42 are sectional and plan views of the twenty-ninth embodiment of the present invention. Among them, the thirty-ninth picture is the image signal wiring (7) 41 This paper ruler applies the Chinese National Standard (CNS) A4 specification (21G X 297 mm 536655 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation (+.) And the plan view of the electrode (8), in which the sectional view of the non-electrode is shown in Figures 40 to 41. When the image signal wiring crosses the gate insulating film, amorphous silicon semiconductor At the boundary of the deposition area of the film and the cover film, due to the difference in the thermal expansion coefficient of the underlying film and the difference in the adhesion force, bad phenomena such as disconnection of the image signal wiring (4 8) or film peeling occur at the boundary of the deposition area. According to the present invention, The lower-layer video signal wiring (49) uses a titanium series metal, a chromium series metal, or a petrified compound of a melting point metal, which can greatly reduce the aforementioned disconnection and film peeling. For example, forty-third to forty Figure 5 is a plan view of the thirtieth embodiment of the present invention. The deposition area of the protective film (54) is wider than the deposition area of the gate insulating film (53). 5 5) was Formed on both sides of the effective day element, the joint area of the common electrode (56) and the image k-number wiring (7) and the joint area of the common electrode (56) and the scanning line (2) exist in the gate insulating film (5 3) outside the deposition area, and the protective active component (5 5) for electrostatic countermeasures and the aforementioned bonding area are completely covered by the protective film (54). As shown in the figure, when the gate insulating film (53) is deposited under the terminal portion (9) of the image signal wiring, the chance of disconnection of the image signal wiring (7) will be greatly reduced. From the terminal portion of the scanning line (3) The distance (B) from the end to the deposition boundary of the gate insulating film (53) and the distance (A) from the end of the scanning line terminal portion (3) to the deposition boundary of the cover film (54) Requires more than 2ram. The distance from the deposition boundary of the same 'gate insulation film (5 3) to the end of the protective terminal (5 5) for the terminal of the static electricity countermeasure (C) is also 42. This paper size applies Chinese national standards ( CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling this page) 0 Pack ---- # 五 、 Explanation of the invention (4 丨) = more than 2 coffee. When the aforementioned distance is less than 2 and less than, the yield of the closed-electrode insulating film is increased, as shown in Figures 46 and 47. = 7. The frame winch ("7 is rounded: attached to the two substrates: on the surrounding border of the closed-electrode insulating film (5 3) or outside the deposition area of the closed-electrode insulating film (inside.)" And is located in the guard. The fourteenth and ninety-fifth drawings of the deposition area of the layer film (54) are the thirty-second plan view of the present invention. The ninety-fourth chart is a photomask for forming a mask line and should be wired. A semi-transparent position is arranged at the intersection with the scanning line. The mask shown in Figure 95 is the channel area of the element, which is connected to the liquid crystal drive electrode and the transparent book. Light transmitting film (24). Using the exposure of this photomask: when the thickness of the positive photoresist in the part where the two light films (2 4) are set is changed to ^ =, it makes super one possible. With this in mind, the photomask shown in Figure 25 is used instead of the semi-transparent film. The intersection of the common electrode and the image signal wiring can also be adapted. The plane signal wiring (7) of the thirteenth embodiment is alternately connected in common. Two: "and" and the image are located at the pole for local deposition. (5 j part is 536655 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明(牛>) 如依本發明運用在主動式元件基板的全工程,光罩工 程的次數可大幅減少至2至3次,藉此可減少無塵室的面 積,且曝光裝置、洗淨裝置、光阻相關裝置及無塵保管倉 庫的數目可大幅的減少,又可大幅減少初期投資金額及大 幅降低工場的營運成本,且因可縮短工程,品質管理容易 ,可易於提升良率。再因生產效率可大幅提高之故,液晶 顯示面板的價格可降低。 又令沈積最大膜厚的閘極絕緣膜作局部性的沈積,可 使玻璃基板上所發生的應力均勻化,因此玻璃基板切割後 亦不易產生異常的尺寸變化,彩色濾光片基板與薄膜電晶 體基板的對合壓著對位誤差也可減少。再者,採用本發明 的電晶體構造、靜電氣對策用保護電晶體,即使在光罩間 發生對位誤差也不會發生顯示不均勻,故可製造對靜電氣 強的液晶面板。用本發明的共通電極構造,可大幅的降低 配向不良’亦可大幅減少影像信號配線的斷線。另掃瞄配 線採用銅’可實現4 〇英吋的大畫面液晶面板。影像信號 配線的下層採用鈦系列的金屬或高融點金屬的矽化物化合 物可有效避免膜剝落,其即使予以超大型化,也不會降低良率。 44 本紙張尺度適用r關家標準(CNS)A4規格(21G x 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝 1111111. #Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (Bull >) If the present invention is applied to the entire project of the active component substrate, the number of photomask projects can be greatly reduced to 2 to 3 times. Reduce the area of the clean room, and the number of exposure devices, cleaning devices, photoresist related devices, and dust-free storage warehouses can be greatly reduced, and the initial investment amount and the operating cost of the workshop can be greatly reduced. Engineering, easy quality management, easy to improve yield. Since the production efficiency can be greatly improved, the price of the liquid crystal display panel can be reduced. In addition, the gate insulating film with the maximum film thickness is locally deposited, which can uniformize the stress occurring on the glass substrate. Therefore, it is not easy to produce abnormal dimensional changes after the glass substrate is cut. The alignment and alignment error of the crystal substrate can also be reduced. Furthermore, with the transistor structure of the present invention and the protective transistor for countermeasures against static electricity, even if an alignment error occurs between the photomasks, display unevenness does not occur, so that a liquid crystal panel that is strong against static electricity can be manufactured. With the common electrode structure of the present invention, it is possible to greatly reduce misalignment 'and also to significantly reduce the disconnection of video signal wiring. In addition, the scanning wiring uses copper 'to realize a 40-inch large-screen LCD panel. The lower layer of the video signal wiring uses a titanium-based metal or a high-melting-point metal silicide compound to effectively prevent the film from peeling off, and even if it is oversized, it will not reduce the yield. 44 This paper size is compatible with CNS A4 (21G x 297 mm) (Please read the precautions on the back before filling this page). 1111111. #
Claims (1)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP28319498A JP4264675B2 (en) | 1998-08-17 | 1998-08-17 | Liquid crystal display device and manufacturing method thereof |
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TW536655B true TW536655B (en) | 2003-06-11 |
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TW88113987A TW536655B (en) | 1998-08-17 | 1999-08-13 | Liquid crystal display device |
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TW (1) | TW536655B (en) |
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US6255130B1 (en) * | 1998-11-19 | 2001-07-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and a method for manufacturing the same |
US6287899B1 (en) * | 1998-12-31 | 2001-09-11 | Samsung Electronics Co., Ltd. | Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same |
JP2001005038A (en) * | 1999-04-26 | 2001-01-12 | Samsung Electronics Co Ltd | Thin film transistor substrate for liquid crystal display device and its production |
US6380559B1 (en) | 1999-06-03 | 2002-04-30 | Samsung Electronics Co., Ltd. | Thin film transistor array substrate for a liquid crystal display |
JP2001339072A (en) * | 2000-03-15 | 2001-12-07 | Advanced Display Inc | Liquid crystal display device |
JP4393662B2 (en) | 2000-03-17 | 2010-01-06 | 株式会社半導体エネルギー研究所 | Method for manufacturing liquid crystal display device |
JP2001311965A (en) | 2000-04-28 | 2001-11-09 | Nec Corp | Active matrix substrate and manufacturing method therefor |
JP2002026333A (en) * | 2000-07-11 | 2002-01-25 | Nec Corp | Method of manufacturing active matrix board |
JP4582877B2 (en) * | 2000-08-09 | 2010-11-17 | 三菱電機株式会社 | Manufacturing method of TFT array |
US7223643B2 (en) * | 2000-08-11 | 2007-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
JP4565799B2 (en) | 2002-07-01 | 2010-10-20 | 大林精工株式会社 | Horizontal electric field type liquid crystal display device, manufacturing method thereof, scanning exposure apparatus, and mixed scanning exposure apparatus |
TWI278696B (en) | 2002-09-10 | 2007-04-11 | Obayashiseikou Co Ltd | Active matrix type vertically aligned mode liquid crystal display and driving method thereof |
TW584908B (en) * | 2003-04-15 | 2004-04-21 | Hannstar Display Corp | Method of manufacturing IPS-LCD by using 4-mask process |
KR100980020B1 (en) * | 2003-08-28 | 2010-09-03 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method thereof |
TWI382264B (en) | 2004-07-27 | 2013-01-11 | Samsung Display Co Ltd | Thin film transistor array panel and display device including the same |
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JP2006133785A (en) * | 2004-11-08 | 2006-05-25 | Lg Micron Ltd | Half tone mask, method for fabricating the same, and flat panel display manufactured by the same |
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CN100449384C (en) * | 2005-08-03 | 2009-01-07 | 友达光电股份有限公司 | Method for producing liquid crystal display base board |
JP5100997B2 (en) * | 2005-10-18 | 2012-12-19 | 三菱電機株式会社 | Method for manufacturing thin film transistor substrate |
JP2007178649A (en) * | 2005-12-27 | 2007-07-12 | Dainippon Printing Co Ltd | Gray-scale mask |
JP2007310334A (en) | 2006-05-19 | 2007-11-29 | Mikuni Denshi Kk | Manufacturing method of liquid crystal display device using half-tone exposure method |
JP5673718B2 (en) * | 2006-07-21 | 2015-02-18 | 大日本印刷株式会社 | Gradation mask |
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US9645457B2 (en) | 2006-11-22 | 2017-05-09 | Mitsubishi Electric Corporation | Array substrate, display device, and method for manufacturing the array substrate |
JP5266645B2 (en) * | 2007-01-31 | 2013-08-21 | 三菱電機株式会社 | Thin film transistor and display device using the thin film transistor |
CN101382728B (en) * | 2007-09-07 | 2010-07-28 | 北京京东方光电科技有限公司 | Gray level mask plate structure |
CN101387825B (en) * | 2007-09-10 | 2011-04-06 | 北京京东方光电科技有限公司 | Compensation gray level mask plate structure |
JP4898749B2 (en) * | 2008-08-04 | 2012-03-21 | 大林精工株式会社 | Scanning exposure apparatus and horizontal electric field type liquid crystal display device |
KR20110056542A (en) | 2008-09-12 | 2011-05-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device |
KR101803264B1 (en) | 2008-09-19 | 2017-12-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
KR101273972B1 (en) * | 2008-10-03 | 2013-06-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
JP2010049288A (en) * | 2009-12-02 | 2010-03-04 | Semiconductor Energy Lab Co Ltd | Liquid crystal display |
CN102655175B (en) * | 2012-04-06 | 2014-07-02 | 京东方科技集团股份有限公司 | TFT (thin film transistor), array base plate, display device and mask plate for preparing TFT |
JP5668745B2 (en) * | 2012-11-30 | 2015-02-12 | 大日本印刷株式会社 | Gradation mask |
CN104155842A (en) * | 2014-07-18 | 2014-11-19 | 京东方科技集团股份有限公司 | Mask plate |
TWI629622B (en) * | 2017-04-17 | 2018-07-11 | 承洺股份有限公司 | Attached optical film applied technology of display device |
-
1998
- 1998-08-17 JP JP28319498A patent/JP4264675B2/en not_active Expired - Fee Related
-
1999
- 1999-08-13 TW TW88113987A patent/TW536655B/en not_active IP Right Cessation
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JP4264675B2 (en) | 2009-05-20 |
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