KR19990003792A - Liquid crystal display device and manufacturing method of liquid crystal display device - Google Patents

Abstract

The present invention relates to a structure of a pad formed at an end portion of each wiring in an active substrate used in a liquid crystal display device. When forming the gate pad portion or the source pad portion in the active substrate, the pad is connected to each wiring and has a rectangular border shape, and a pad connection terminal electrically connected to the pad and filling a center portion of the pad having the rectangular border shape. It was. Thereby, the pad connection terminal forming the center portion of the pad portion where the pin of the inspection equipment is contacted during the A / P (Auto Probe) process, which is a kind of quality inspection step, is completed. Even if scratched, torn or broken, the pads with a square rim are not damaged because they do not contact the pins. Therefore, it is possible to minimize the failure due to disconnection in the pad portion that can occur during the automatic inspection.

Description

The manufacturing method and structure of the liquid crystal display device

The present invention relates to an active matrix substrate (or an active substrate) used in a liquid crystal display. More specifically, by improving the structure of the gate pad and the source pad formed at the ends of the gate wiring and the source wiring, the probe pin of the process equipment during the auto-probe process, which is one of the quality inspection processes. The present invention relates to a method and a structure of an active substrate that overcomes defects such as disconnection or poor contact caused by scratching, tearing, or puncture of a pad.

Among the screen display devices that display image information on the screen, CRT displays (or Cathode Ray Tubes (CRTs)), which have been widely used so far, have been replaced with thin-film flat panel displays that can be easily used anywhere. In particular, the liquid crystal display device is the product which is most active development research because the display resolution is superior to other flat-panel devices and the response speed is faster than that of the CRT when implementing a moving picture. Moreover, active substrates using active elements such as thin film transistors as switching elements have been widely applied to liquid crystal displays and the like.

The structure of a general active substrate using a thin film transistor as a switching element is shown in FIG. Referring to this figure, the structure of an active substrate used in a general liquid crystal display device is as follows. The plurality of gate wirings 13 are formed in parallel in the horizontal direction on the transparent insulating substrate 1 formed of a material such as glass, and the plurality of source wirings 23 are formed in parallel in the vertical direction. Gate pads 15 and source pads 25 for applying external signals to the respective gate wirings 13 and the source wirings 23 are formed at the ends of the respective wirings. The thin film transistor which is a switching element is formed in the intersection part of each wiring. The thin film transistor includes a gate electrode 11, a gate insulating film (not shown), a semiconductor layer 33, a source electrode 21, and a drain electrode 31. The gate electrode 11 of the thin film transistor branches from the gate wiring 13, and the source electrode 21 branches from the source wiring 23. The drain electrode 31 of the thin film transistor is electrically connected to the pixel electrode 41 formed in a region surrounded by each of the gate wiring 13 and the source wiring 23.

And the manufacturing process of this active substrate is shown in FIG. 2 which is the cross section cut by the cutting line II-II in FIG. First, referring to these drawings, a method of manufacturing a general active panel is as follows.

A metal such as aluminum (Al) or an aluminum alloy (Al-alloy) is deposited on the transparent insulating substrate 1 by sputtering, and then patterned by photo-lithography to form a low resistance gate wiring. 13a, the low resistance gate pad 15a is formed. The low resistance gate wiring 13a extends in the row direction of the designed pixel. The plurality of low resistance gate wirings 13a are arranged in the column direction. The low resistance gate pad 15a is formed at the end of the low resistance gate wiring 13a (FIG. 2A).

Then, metals such as chromium (Cr), molybdenum (Mo), tantalum (Th), and antimony (Sb) are deposited and patterned to form the gate electrode 11, the gate wiring 13, and the gate pad 15. . The gate wiring 13 covers the low resistance gate wiring L3a. The gate electrode 11 is branched from the gate wiring 13 and formed at one corner of the designed pixel. The gate pad 15 is formed to cover the low resistance gate pad 15a (FIGS. 1 and 2B).

A material such as silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) is deposited over the entire surface of the substrate by a plasma chemical vapor deposition (CVD) method to form a gate insulating film 17 (FIG. 2C).

Amorphous silicon and n + amorphous silicon are sequentially deposited on the gate insulating layer 17 by plasma CVD and then patterned by photolithography to form the semiconductor layer 33 and the impurity semiconductor layer 35. The semiconductor layer 33 serves as a channel layer of the thin film transistor. In addition, the impurity semiconductor layer 35 allows ohmic contact between the source (21 in FIG. 1) -drain electrode (31 in FIG. 1) and the semiconductor layer 33 formed later (FIG. 2D).

A metal such as chromium or a chromium-based alloy is deposited by sputtering, and then patterned by photolithography to form the source electrode 21, the drain electrode 31, the source wiring 23, and the source pad 25. In this case, dry etching using the source electrode 21 and the drain electrode 31 as a mask is a portion exposed between the source electrode 21 and the drain electrode 31 of the impurity semiconductor layer 35. Remove using the law. The source electrode 21 overlaps one side of the gate electrode 11 with the impurity semiconductor layer 35 therebetween. The drain electrode 31 is formed to face the source electrode 21 and overlaps the other side of the gate electrode 11 with the impurity semiconductor layer 35 therebetween. The source wiring 23 extends in the column direction of the designed pixel. The plurality of source wirings 23 are arranged in the row direction. The source pad 25 is formed at the end of the source wiring 23 (FIG. 2E).

A material such as silicon nitride is deposited by plasma CVD to form a protective insulating film 37. The protective insulating layer 37 is patterned by photolithography to form the drain contact hole 71, the gate contact hole 59, and the source contact hole 69. The drain contact hole 71 exposes a portion of the drain electrode 31. The gate contact hole 59 and the source contact hole 69 expose a portion of the gate pad 15 and the source pad 25, respectively. (FIG. 2F).

A transparent conductive film such as ITO is deposited on the protective insulating layer 37 and then patterned to form the pixel electrode 41, the gate pad connection terminal 57, and the source pad connection terminal 67. The pixel electrode 41 is electrically connected to the drain electrode 31 through the drain contact hole 71. The gate pad connection terminal 57 and the source pad connection terminal 67 are connected to the gate pad 15 and the source pad 25 through the gate contact hole 59 and the source contact hole 69, respectively (Fig. 2G). ).

Looking at the cross-sectional structure of the general active substrate manufactured in this manner in detail is made as follows. The minser and thin film transistor units are described as follows. A gate electrode 11 made of a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or antimony (Sb) is formed on the transparent insulating substrate 1. The entire insulating film 17 including the gate electrode 11 is covered with a gate insulating film 17 made of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), or the like. A semiconductor layer 33 made of a material such as amorphous silicon (a-Si) is formed on the gate barrier layer 17. On the semiconductor layer 33, an impurity semiconductor layer 35 made of a material such as n + amorphous silicon to which an impurity material such as phosphorus (P) is added is formed on both sides. On the impurity semiconductor layer 35, a source electrode 21 and a drain electrode 31 made of a metal such as chromium or molybdenum are respectively formed to correspond to the impurity semiconductor layer 35 separated in both. A protective insulating film 37 is formed over the entire surface of the substrate including the source electrode 21 and the drain electrode 31. The drain electrode 31 is electrically connected to the pixel electrode 41 made of a transparent conductive material such as indium-tin-oxide (ITO) by a contact hole.

Next, the gate pad portion will be described below. A low resistance gate pad 15a formed of a metal including aluminum is formed on the substrate 1. The gate pad 15 containing chromium, molybdenum, tantalum, antimony, or the like is formed thereon. If necessary, the low resistance gate pad 15a may not be formed below the gate pad 15. The gate insulating layer 17 and the protective insulating layer 37 covering the gate pad 15 expose a part of the gate pad 15 and cover the entire other substrate. A gate pad connection terminal 59 made of ITO, which forms a pixel electrode, is formed on the gate pad 15 that is not covered with the gate insulating layer 17 and the protective insulating layer 37.

Finally, the source pad portion is as follows. A gate insulating film 17 made of silicon nitride is formed on the transparent insulating substrate 1. A source pad 25 made of metal containing chromium is formed on the gate insulating film 17. The protective insulating film 37 exposes a part of the source pad 25 and covers the entire other gate insulating film 17. A source pad connection terminal 69 made of ITO, which forms the pixel electrode 41, is formed on the exposed source pad 25 without being covered by the protective insulating layer 37.

The active substrate completed in this manner is inspected in an A / P (auto probe) process. In the automatic inspection process, each pad is connected to the pin of the inspection equipment and voltage is applied to determine whether there is an abnormality in each wiring. In the above-described automatic inspection process, a failure of disconnecting the pad as well as the pad connection terminal made of ITO may occur due to the pressure of the pin of the inspection equipment. In addition, in the case of TAB repair, defects such as scratching or tearing of the pad may occur.

In fact, after the automatic inspection process, a low resistance gate pad was formed of aluminum about 2000 kV thick, a gate pad was formed of molybdenum about 1000 kV thereon, and a gate pad connection terminal was formed on ITO about 500 kV thick thereafter. Open circuit defects occurred in 20 cases of 392 inspections, and the defective rate was about 5%. On the other hand, in the experiment with the aluminum-free structure, the disconnection defect in the gate pad hardly occurred after the automatic inspection. This is because aluminum is a weak metal, and when the test pin contacts it, it cannot withstand the pressure and is scratched or torn off.

Since failure of the normally completed active substrate in the inspection process does not mean performing the defect inspection process, it is important to form a high-strength pad that can withstand the pressure of the inspection pin in the inspection process.

1 is a plan view of a general active substrate according to the prior art.

FIG. 2 is a cross-sectional view illustrating a process of manufacturing a conventional active substrate with a cut line II-II in FIG. 1.

3 is a plan view of an active substrate according to the present invention.

4 is a cross-sectional view illustrating a manufacturing process of an active substrate according to a first embodiment of the present invention, which is a view taken along cut line IV-IV of FIG. 3.

FIG. 5 is a cross-sectional view showing a manufacturing process of an active substrate according to a second embodiment of the present invention, which is taken along the cut line IV-IV of FIG. 3.

6 is a plan view of an active substrate according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of an active substrate according to a third embodiment of the present invention, which is a view taken along the line VII-VII of FIG. 6.

* Explanation of symbols for main parts of the drawings

1,101 substrate 11,111 gate electrode

13,113: gate wiring 15,115: gate pad

13a, 113a: low resistance gate wiring 15a, 115a: low resistance gate pad

17,117: gate insulating film 21,121: source electrode

23,123: source wiring 25,125: source pad

31,131: drain electrode 33,133: semiconductor layer

35,135 impurity semiconductor layer 37,137 protective film

41,141: pixel electrode 57,157: gate pad connection terminal

59,159: Gate contact hole 67,167: Source pad connection terminal

69,169: source contact hole 71,171: drain contact hole

145: etching prevention member

An object of the present invention is to overcome the disconnection defect that may occur in the pad portion in manufacturing an active substrate of the liquid crystal display device. In particular, it is an object of the present invention to prevent the pad from being torn by the pins of the inspection equipment in the step of inspecting the finished active substrate. Still another object of the present invention is to have a structure in which disconnection does not occur even if the pad is damaged by the pins of the inspection equipment.

In order to solve this object, in the present invention, the pad portion of the active substrate used in the liquid crystal display device is formed in the following structure. At the end of the wiring, a pad having a rectangular shape, ie, a rectangular rim, with a blank center and an edge only, was formed of the first conductive material. In addition, a pad connection terminal electrically connected to the pad was formed by filling a center portion of the pad pattern with the second conductive material. That is, in a typical liquid crystal display device, a pad portion is formed by contacting a pad having a rectangular shape made of a single metal and a pad connection terminal thereon, whereas in the present invention, a pad having a rectangular border shape and an empty center of the pad are formed. The pads are filled with pad connection terminals connected to the pads. In order to understand the present invention in detail, it will be described in more detail through the following various embodiments.

Example 1

The pad manufacturing method according to the present embodiment will be described with reference to Fig. 3 showing a plan view of an active substrate according to the present invention and Fig. 4 showing a sectional view taken along the cut lines IV-IV of Fig. 3.

A metal such as aluminum (Al) or an aluminum alloy (Al-alloy) is deposited on the substrate 101 by sputtering, and then patterned by photolithography to form a low resistance gate wiring 113a. The low resistance gate wiring 113a extends in the row direction of the designed pixel. A plurality of low resistance gate wirings 113a are arranged in the column direction (Fig. 4A).

Then, a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or antimony (Sb) is deposited by sputtering, and then patterned by photolithography to form a gate electrode 111, a gate wiring 113, and the like. The gate pad 115 is formed. The gate wiring 113 is formed to cover the low resistance gate wiring 113a. The gate electrode 111 branches from the gate line 113 and is formed at one corner of the designed pixel. In addition, the gate pad 115 has a rectangular rim shape in which a part of the gown is empty, and only an edge is formed, and is formed at an end of the gate wiring 113 (FIG. 4B),

A gate insulating film 117 is formed by depositing a material such as silicon nitride or silicon oxide over the entire surface of the substrate 101 on which the gate electrode 111 and the like are formed by plasma CVD (FIG. 4C).

Subsequently, amorphous silicon and n + amorphous silicon are sequentially deposited by using a plasma CVD method and then patterned to form a semiconductor layer 133 and an impurity semiconductor layer 135. The semiconductor layer 133 forms a channel layer of the thin film transistor, and the impurity semiconductor layer 135 allows the source electrode and the drain electrode formed later to make ohmic contact with the semiconductor layer 133 (FIG. 4D).

A metal such as chromium or a chromium-based alloy is deposited by sputtering, and then patterned to form a source electrode 121, a drain electrode 131, a source wiring 123, and a source pad 125. The source wiring 125 extends in the column direction of the designed pixel. The plurality of source wirings 125 are arranged in the row direction. The source electrode 121 branches from the source wiring 123 and overlaps one side of the gate electrode 111 with the impurity semiconductor layer 135 interposed therebetween. The drain electrode 131 is formed to face the source electrode 121 and overlaps the other side of the gate electrode 111 with the impurity semiconductor layer 135 interposed therebetween. The source pad 125 is formed on the gate insulating layer 117 in the shape of a rectangular border having only an edge portion at the center of the designed source pad pattern. The impurity semiconductor layer 135 exposed between the source electrode 121 and the drain electrode 131 is removed using a dry etching method using the source electrode 121 and the drain electrode 131 as a mask (FIG. 4E). ).

A material such as silicon nitride is deposited by plasma CVD to form a protective insulating film 137. The protective insulating layer 137 is patterned to form the drain contact hole 171 on the drain electrode 131, and the source contact hole 169 is formed in the source pad 125. The gate pad portion is etched to the gate insulating film 117 covering the gate pad portion to form the gate contact hole 159. The drain contact hole 171 exposes a part of the drain electrode 131, the gate contact hole 159 exposes the gate pad 115, and the source contact hole 169 exposes the source pad 125. In particular, when the source contact hole 169 is formed, the shape of the exposed source pad 125 is continuously viewed with a mask to remove the gate insulating film 117 exposed at the center portion of the source pad 125. In general, since the gate insulating layer 117 and the protective insulating layer 137 are similar materials including SiO ₂ or SiN _x , the gate insulating layer 117 and the protective insulating layer 137 may be etched with the same etching material (FIG. 4F).

A transparent conductive material such as ITO is deposited and then patterned to form the pixel electrode 141, the gate pad connection terminal 157, and the source pad connection terminal 167. The pixel electrode 141 is electrically connected to the drain electrode 131 through the drain contact hole 171. The gate pad connection terminal 157 is connected to the gate pad 115 through the gate contact hole 159 and fills the center portion of the empty gate pad pattern. The source pad connection terminal 167 is connected to the source pad 125 through the source contact hole 169 and fills the center portion of the empty source pad shape (FIG. 4G).

The gate pad portion formed in this manner has the following structure. On the glass substrate 101, a gate pad 115 having a rectangular edge shape formed only at an edge portion of a metal such as chromium, molybdenum, tantalum, or antimony that forms the gate wiring 113 is formed. A gate insulating layer 117 is formed on the substrate 101 including the gate pad 115, and a protective insulating layer 137 is formed on the gate insulating layer 117. Gate contact holes 159 are formed in the gate insulating layer 117 and the protective insulating layer 137 to expose a portion of the gate pad 115. The gate pad connection terminal 157 which fills the center portion of the empty gate pad 115 while electrically connected to the gate pad 115 through the gate contact hole 159 with the ITO forming the pixel electrode 141 is formed. Formed.

On the other hand, the source pad portion has the following structure. A gate insulating film 117 is formed on the substrate 101. The source pad 125 is formed of a metal such as chromium or a chromium alloy forming the source wiring 123 on the gate insulating layer 117. As in the case of the gate pad 115, the source pad 125 also has a rectangular edge shape having only an edge portion of the source pad pattern. In addition, the gate insulating layer 117 is also removed from the exposed middle portion of the source pad (125). A protective insulating layer 137 is formed on the source pad 125. A source contact hole 169 exposing a portion of the source pad 125 is formed in the protective insulating layer 137. A source pad connection terminal 167 is formed through the ITO forming the pixel electrode 141 and is electrically connected to the source pad 125 to fill a center portion of the source pad pattern.

In this embodiment, aluminum is not included in the gate pad 115. This increased the strength of the gate pad 115. In addition, the shape of the gate pad 115 and the source pad 125 in the shape of a window frame, so that only the pad connection terminal made of ITO is formed at the part where the pin of the inspection equipment touches. As a result, even if the pad connection terminal was damaged by the pins of the inspection equipment, the pads did not fail.

Example 2

In Example 1, the gate pad was formed to form a single metal layer. However, if necessary, a low resistance gate pad may be formed when the low resistance gate wiring is formed, and a gate pad covering the low resistance gate pad may be formed when the gate wiring is formed thereon. For the sake of understanding, the present invention will be described with reference to FIG. 5, which shows a manufacturing process with a view taken along the cut line IV-IV of FIG. 3, which is a plan view of the active substrate according to the present invention.

In this case, the manufacturing method of an active substrate is as follows. A metal such as aluminum (Al) or an aluminum alloy (Al-alloy) is deposited on the substrate 101 by sputtering, and then patterned by photolithography to form the low resistance gate wiring 113a and the low resistance gate pad 115a. Form. The low resistance gate wiring extends in the row direction of the designed pixel. The plurality of low resistance gate lines 113a are arranged in the column direction. The low resistance gate pad 115a is positioned at the end of the low resistance gate wiring 113a, and is formed in a rectangular border shape in which a center portion of the pad pattern is empty and only an edge portion is formed (FIG. 5A).

Then, a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or antimony (Sb) is deposited by sputtering, and then patterned by photolithography to form a gate electrode 111, a gate wiring 113, and the like. The gate pad 115 is formed. The gate wiring 113 is formed to cover the low resistance gate wiring 113a. The gate electrode 111 branches from the gate line 113 and is formed at one corner of the designed pixel. In addition, the gate pad 115 covers the low resistance gate pad 115a and has a rectangular edge shape in which a portion of the gown is empty and only an edge portion is formed (FIG. 5B).

The subsequent active substrate manufacturing process proceeds in the same manner as in Example 1. The gate insulating film 117 is formed of a material such as silicon nitride or silicon oxide over the entire surface of the substrate 101 on which the gate electrode 111 and the like are formed (FIG. 5C).

Subsequently, amorphous silicon and n + amorphous silicon are sequentially deposited and then patterned to form a semiconductor layer 133 and an impurity semiconductor layer 135 (FIG. 5D).

The source electrode 121, the drain electrode 131, the source wiring 123, and the source pad 125 are formed of a metal such as chromium or a chromium-based alloy (FIG. 5E).

The protective insulating film 137 is formed of a material such as silicon nitride. The protective insulating layer 137 is patterned to form the drain contact hole 171 on the drain electrode 131, and the source contact hole 169 is formed in the source pad 125. The gate pad portion is etched to the gate insulating film 117 covering the gate pad portion to form the gate contact hole 159. The drain contact hole 171 exposes a portion of the drain electrode 131, the gate contact hole 159 exposes the gate pad 115, and the source contact hole 169 exposes the source pad 125. In particular, when the source contact hole 169 is formed, the shape of the exposed source pad 125 is continuously viewed with a mask to remove the gate insulating film 117 exposed at the center portion of the source pad 125 (FIG. 5F). ).

A transparent conductive material such as ITO is deposited and then patterned to form the pixel electrode 141, the gate pad connection terminal 157, and the source pad connection terminal 167 (FIG. 5G).

As a result, the structure of the thin film transistor portion and the structure of the source pad portion are the same as in the case of Example 1 (compare Fig. 3G with Fig. 5G). The gate pad portion has a structure in which the low resistance gate pad 115a and the gate pad 115 are stacked in the first embodiment. The gate pad connecting terminal 157 is connected to the gate pad 115 through the gate contact hole 15g and fills the center portion of the empty gate pad pattern (FIG. 5G).

In this embodiment, the low resistance gate pad is made of aluminum having low resistance. However, the test pin does not directly contact the gate pad in the automatic inspection process because the pad has an empty shape in the center and has a rectangular edge shape having only an edge. However, only high-strength ITO is used, and only the gate pad connecting terminal filling the center portion of the gate pad comes into contact with the test pin. Therefore, a defect that is scratched or torn in the gate pad portion by the pressure of the pin does not occur.

Example 3

In general, in a pattern process such as a protective insulating film formed after forming the gate pad, an etchant penetrates into the gate insulating film and the gate pad, thereby causing damage to the gate pad. In order to solve the above etching problem of the pad, an active substrate having a pad etch preventing member formed on an outer circumference of the pad shape is presented in Korean Patent Application No. 97-12327. When the etching of the pad occurs in the gate pad forming a portion except for the center portion of the pad pattern of the present invention, the gate pad in the form of a window frame may be more easily etched and broken because of its narrow width. In order to prevent this, the present embodiment provides an active substrate having a structure in which an etch preventing member is formed at an outer circumference of the gate pad.

6 is a plan view of an active substrate according to the present embodiment. 7 is a cross-sectional view taken along the line VIII-XI of FIG. 6, showing the manufacturing process of the active substrate according to the present embodiment. With reference to these drawings, the manufacturing method of the pad which concerns on a present Example is demonstrated. In particular, in the present embodiment, in the case of Example 1, the case where the etching prevention member is further formed. In Example 2, it is obvious that the etch stop member can be further formed in a similar manner, and thus descriptions thereof will not be repeated.

A metal such as aluminum (Al) or an aluminum alloy (Al-alloy) is deposited on the substrate 101 by sputtering, and patterned by photolithography to form a low resistance gate wiring 113a (FIG. 7A). .

Then, a metal such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or antimony (Sb) is deposited by sputtering, and then patterned by photolithography to form a gate electrode 111, a gate wiring 113, and The gate pad 115 is formed. The gate pad 115 is formed in the shape of a rectangular border having an empty center portion and only an edge portion (FIG. 7B).

A material such as silicon nitride or silicon oxide is deposited on the substrate by plasma CVD or the like over the entire surface of the substrate to form a gate insulating film 117 (FIG. 7C).

Subsequently, amorphous silicon and n + amorphous silicon are sequentially deposited using a plasma CVD method and then patterned to form a semiconductor layer 133 and an impurity semiconductor layer 135. The semiconductor layer 133 forms a channel layer of the thin film transistor, and the impurity semiconductor layer 135 allows the source electrode and the drain electrode formed later to make ohmic contact with the semiconductor layer 133 (FIG. 7D).

A metal such as chromium or a chromium alloy is deposited by sputtering and then patterned by photolithography to form a source electrode 121, a drain electrode 131, a source wiring 123, a source pad 125, and an etch preventing member 145. ). The source pad 125 is formed on the gate insulating layer 117 in the shape of a rectangular border having an empty center portion and only an edge portion. The etch preventing member 145 is formed to cover the window pad-shaped source pad 125 on the gate insulating film 117 (FIG. 7E).

A material such as silicon nitride is deposited by plasma CVD to form a protective insulating film 137. The protective insulating film 137 is patterned to form a drain contact hole 171, a gate contact hole 159, and a source contact hole 169 (FIG. 7F).

A transparent conductive material such as ITO is deposited and then patterned to form the pixel electrode 141, the gate pad connection terminal 157, and the source pad connection terminal 167. The pixel electrode 141 is electrically connected to the drain electrode 131 through the drain contact hole 171. The gate pad connection terminal 157 is connected to the gate pad 115 through the gate contact hole 159, and fills a center portion of the empty gate pad 115. The source pad connection terminal 167 is connected to the source pad 125 through the source contact hole 169 and fills the center portion of the empty source pad 125 (FIG. 7G).

In this embodiment, only the metal for forming the source wiring 113 is used as the etch preventing member 145, but when forming the semiconductor layer 133, a protective layer for preventing etch around the gate pad 115 with a semiconductor material. 145 may be formed. Alternatively, a protective layer 145 may be formed around the gate pad 115 in a structure in which a semiconductor material used to form the semiconductor layer 133 and a metal forming the source wiring 123 are stacked. have.

According to the present invention, when forming a gate pad portion or a source pad portion in an active substrate, a pad is connected to each wire and has a rectangular edge shape, and a pad connection terminal electrically connected to the pad and filling a center portion of the rectangular edge shape. It was. Thereby, the pad connection terminal forming the center portion of the pad portion where the pin of the inspection equipment is contacted during the A / P: Auto Probe process, which is a kind of quality inspection step. Even if scratched, torn or broken, the pad forming the edge portion of the pad pattern could have the effect of not being damaged by the pins. Therefore, it was possible to improve the production yield by minimizing defects due to disconnection at the pad part that could occur during the automatic inspection.

Claims (17)

Forming a gate electrode with a first conductive material, a gate wiring connected to the gate electrode, and a gate pad having a rectangular shape having an edge only at an end of the gate wiring on a substrate; Manufacturing method. The method of claim 1, further comprising: forming a gate insulating film on the substrate on which the gate wiring, the gate electrode, and the gate pad are formed, and forming a gate insulating film on the gate electrode on the gate insulating film using a semiconductor material. Forming a semiconductor layer, a source electrode overlapping one portion of the gate electrode with the semiconductor layer interposed therebetween on a substrate on which the semiconductor layer is formed, a source wiring connecting the source electrodes, and And forming a source pad having a rectangular shape having an edge only at an end portion of the source wiring. 3. The method of claim 2, further comprising: forming an insulating protective film on the source electrode, the source wiring, and the substrate on which the source pad is formed, using a second insulating material, and patterning the insulating protective film to expose a portion of the drain electrode. Forming a contact hole, a gate contact hole exposing a portion of the gate insulating film formed on the gate pad, and a source contact hole exposing a portion of the source pad, and the gate exposed through the gate contact hole; Removing a portion of the gate insulating layer covering a portion over the pad to expose a portion of the gate pad, and removing a portion of the gate pad exposed by the shape of the source contact hole and the source pad; A pixel connected to the drain electrode through the drain contact hole with a conductive material. And forming a gate pad connection terminal connected to the gate pad through the gate contact hole, and a source pad connection terminal connected to the source pad through the source contact hole. Manufacturing method. The method of claim 2, wherein in the forming of the semiconductor layer, a pad protection layer covering the gate pad is further formed on the gate insulating layer using the semiconductor material. The method of claim 3, wherein in the forming of the source electrode, a pad protective layer covering the gate pad is further formed on the gate insulating layer using the second conductive material. The method of claim 4, wherein the forming of the source electrode further comprises forming a pad protective layer covering the gate pad on the gate insulating layer with the second conductive material. The method of claim 1, wherein the first conductive material comprises a first metal layer and a second metal layer. The method of claim 7, wherein the first metal layer comprises aluminum. The method of claim 7, wherein the second metal layer comprises any one selected from the group consisting of chromium, molybdenum, tantalum, and antimony. And a gate electrode formed of a first conductive material on the substrate, a gate wiring connected to the gate electrode, and a gate pad having a rectangular shape at the end of the gate wiring. The semiconductor device of claim 10, further comprising: a gate insulating film formed of a first insulating material on the substrate on which the gate wiring, the gate electrode, and the gate pad are formed, and a semiconductor layer formed of a semiconductor material on the gate electrode on the gate insulating film. And a source electrode formed to overlap one portion of the gate electrode with the semiconductor layer interposed therebetween, a source wiring connecting the source electrodes, and a rectangular shape having only a border at the end of the source wiring. The liquid crystal display device further comprises a source pad formed. 12. The method of claim 11, wherein the source electrode, the source wiring, an insulating protective film formed with a second insulating material on the substrate on which the source pad is formed, a drain contact hole exposing a portion of the drain electrode, and a portion of the gate pad. A gate contact hole for exposing, a source contact hole for exposing a portion of the source pad, a pixel electrode connected to the drain electrode through the drain contact hole with a third conductive material on the protective insulating layer, and through the gate contact hole And a gate pad connection terminal connected to the gate pad and a source pad connection terminal connected to the source pad through the source contact hole. The liquid crystal display device of claim 12, further comprising a pad protection layer formed on the gate insulating layer to cover the gate pad with the semiconductor material. The liquid crystal display device of claim 10, further comprising a pad protective layer formed on the gate insulating layer to cover the gate pad with the second conductive material. The liquid crystal display device according to any one of claims 10 and 13, wherein the first conductive material comprises a first metal layer and a second metal layer. The liquid crystal display device of claim 15, wherein the first metal layer comprises aluminum. The liquid crystal display of claim 15, wherein the second metal layer comprises any one selected from the group consisting of chromium, molybdenum, tantalum, and antimony.