KR100497297B1 - Liquid Crystal Display Device and Fabricating Method Thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a method of manufacturing the same that can improve the yield.

A liquid crystal display device according to the present invention includes a signal pad connected to one end of a signal line formed on a substrate, a gate insulating film formed to cover the signal pad, a semiconductor layer formed on the gate insulating film, and the gate insulating film. And a pad contact hole through the semiconductor layer to expose the signal pad, a metal electrode in contact with the signal pad through the pad contact hole, and directly contacting the metal electrode on the gate insulating layer and the metal electrode. And a pad protective electrode.

Description

Liquid crystal display device and its manufacturing method {Liquid Crystal Display Device and Fabricating Method Thereof}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can improve the yield.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. In general, the pixel electrode is formed for each liquid crystal cell on the lower substrate, while the common electrode is integrally formed on the front surface of the upper substrate. Each of the pixel electrodes is connected to a thin film transistor (TFT) used as a switch element. The pixel electrode drives the liquid crystal cell along with the common electrode according to the data signal supplied through the thin film transistor.

1 and 2, the lower substrate 1 of the liquid crystal display device includes a TFT part TP positioned at an intersection of the data line 4 and the gate line 2, and a drain of the TFT part TP. The pixel electrode 22 connected to the electrode 10, the storage capacitor part SP located at an overlapping portion of the pixel electrode 22 and the gate line 2, the data line 4 and the gate line 2. And a gate pad portion GP and a data pad portion DP formed at one end of each side.

The TFT portion TP is connected to the pixel electrode 22 through the gate electrode 6 connected to the gate line 2, the source electrode 8 connected to the data line 4, and the drain contact hole 26a. A drain electrode 10 is provided. In addition, the TFT portion TP further includes semiconductor layers 14 and 16 for forming a conductive channel between the source electrode 8 and the drain electrode 10 by the gate voltage supplied to the gate electrode 6. . The TFT portion TP selectively supplies the data signal from the data line 4 to the pixel electrode 22 in response to the gate signal from the gate line 2.

The pixel electrode 22 is formed in a cell region divided by the data line 4 and the gate line 2 and is made of a transparent conductive material having high light transmittance. The pixel electrode 22 is formed on the protective layer 18 coated on the entire surface of the substrate 1, and is electrically connected to the drain electrode 10 through the drain contact hole 26a penetrating through the protective layer 18. . The pixel electrode 22 generates a potential difference from a common transparent electrode (not shown) formed on an upper substrate (not shown) by a data signal supplied through the TFT portion TP. Due to this potential difference, the liquid crystal located between the lower substrate 1 and the upper substrate (not shown) rotates due to the dielectric anisotropy. The amount of light transmitted from the light source to the upper substrate through the pixel electrode 22 is adjusted by the rotated liquid crystal.

The storage capacitor part SP plays a role of suppressing a voltage variation of the pixel electrode 22. The storage capacitor part SP is formed of the storage electrode 24 formed with the gate line 2 and the gate insulating layer 12 interposed therebetween. The storage electrode 24 is in electrical contact with the pixel electrode 22 through the storage contact hole 26b.

The gate pad part GP and the data pad part DP are positioned at one end of each of the gate line 2 and the data line 4, and are connected to a driving integrated circuit (IC). The gate pad portion GP supplies a gate signal for controlling the TFT to the gate line 2, and the data pad portion DP supplies a data signal for controlling the TFT to the data line 4.

The gate pad 32 is in electrical contact with the gate protection electrode 36 through the gate contact hole 26c, and the data pad 28 is in electrical contact with the data protection electrode 30 through the data contact hole 26d. do.

A method of manufacturing such a liquid crystal display device will be described with reference to FIGS. 3A to 3E.

Referring to FIG. 3A, a gate metal layer is deposited on the substrate 1 by a deposition method such as sputtering. The gate metal layer is made of aluminum (Al) or aluminum alloy. The gate electrode 6, the gate line 2, and the gate pad 32 are formed by patterning the gate metal layer in a photolithography process including an etching process using a first mask.

Referring to FIG. 3B, a gate insulating layer 12 is formed on the substrate 1 on which the gate electrode 6, the gate line 2, and the gate pad 32 are formed. The gate insulating layer 12 is made of silicon oxide (SiOx) or silicon nitride (SiNx), which is an inorganic insulating material. The first and second semiconductor layers are continuously deposited on the gate insulating layer 12 by chemical vapor deposition. The first semiconductor layer is formed of amorphous silicon that is not doped with impurities, and the second semiconductor layer is formed of amorphous silicon doped with N or P impurities. Subsequently, the first and second semiconductor layers are patterned by a photolithography method including a dry etching process using a second mask, thereby forming the active layer 14 and the ohmic contact layer 16.

Referring to FIG. 3C, the data metal layer is deposited on the gate insulating layer 12 on which the active layer 14 and the ohmic contact layer 16 are formed by a deposition method such as a CVD method or sputtering. The data metal layer is formed of chromium (Cr) or molybdenum (Mo). Subsequently, the data metal layer is patterned by a photolithography process including a wet etching process using a third mask to form a source electrode 8, a drain electrode 10, a storage electrode 24, and a data pad 28. . Next, the ohmic contact layer 16 exposed between the source electrode 8 and the drain electrode 10 is removed by a dry etching process to separate the source electrode 8 and the drain electrode 10. By partially removing the ohmic contact layer 16, the portion of the active layer 14 corresponding to the gate electrode 6 between the source and drain electrodes 8 and 10 becomes a channel.

Referring to FIG. 3D, an insulating material is formed on the substrate 1 on which the source electrode 8, the drain electrode 10, the storage electrode 24, and the data pad 28 are formed. As the insulating material, inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiOx), or organic insulating materials such as acryl-based organic compounds, benzocyclobutene (BCB) and perfluorocyclobutane (PFCB) are used. Subsequently, the insulating material is patterned by a photolithography process including an etching process using a fourth mask to protect the protective layer 18, the drain contact hole 26a, the storage contact hole 26b, the gate contact hole 26c, and the like. The data contact hole 26d is formed.

Referring to FIG. 3E, the transparent metal layer is formed on the passivation layer 18 by a deposition method such as sputtering. The transparent metal layer may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin oxide (ITZO). ) And so on. Subsequently, the transparent metal layer is patterned by a photolithography process including an etching process using a fifth mask to form the pixel electrode 22, the gate protection electrode 36, and the data protection electrode 30. The pixel electrode 22 is connected to the drain electrode 10 through the drain contact hole 26a passing through the passivation layer 18, and the storage electrode 24 through the storage contact hole 26b passing through the passivation layer 18. Connected with. The gate protection electrode 36 is connected to the gate pad 32 through the gate contact hole 26c penetrating through the gate insulating film 12 and the protection film 18. The data protection electrode 30 is connected to the data pad 28 through the data contact hole 26d penetrating the protective film 18.

In the conventional liquid crystal display device, an aluminum (Al) series having good conductivity is used as a material of the gate metal layer. In particular, aluminum has problems such as hillock and diffusion, and mainly uses aluminum alloys such as aluminum-nedium (AlNd). The aluminum-based metal has a large contact resistance with the transparent metal layer used as the pixel electrode 22, the gate protection electrode 36, and the data protection electrode 30. Accordingly, the gate metal layer is formed of a double metal layer structure such as Mo / AlNd, Mo / Al, Cr / AlNd, etc. using molybdenum (Mo) and chromium (Cr) having good contact resistance with the transparent metal layer. However, when the gate metal layer is formed in a double metal layer structure, the etching process is performed in two steps, thereby increasing the process defect rate and manufacturing cost.

In addition, at least five to six mask processes are required to form the lower substrate of the conventional liquid crystal display. Consumption and processing time of the raw materials used in each of the mask process has been a problem to reduce the yield with a high manufacturing cost in manufacturing the lower substrate of the liquid crystal display device has been proposed a four mask process to solve this problem.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same that can improve the yield.

In order to achieve the above object, a liquid crystal display device according to the present invention is a signal pad connected to one end of a signal line formed on a substrate, a gate insulating film formed to cover the signal pad, and formed on the gate insulating film A pad contact hole for exposing the signal pad through the semiconductor layer, the gate insulating film and the semiconductor layer, a metal electrode in contact with the signal pad through the pad contact hole, and a direct contact with the metal electrode and in contact with the gate insulating film. And a pad protection electrode formed on the metal electrode.

The metal electrode is formed of one of molybdenum (Mo), chromium (Cr), tantalum (Ta), tungsten (W).

The signal line is a gate line, and the signal pad is formed of aluminum (Al) or an aluminum alloy.

The liquid crystal display device may include a data pad part formed at one end of a data line perpendicular to the gate line.

The data pad part includes a second metal electrode formed on the substrate, a data contact hole through the gate insulating layer and the semiconductor layer to expose the second metal electrode, and a data pad connected to the second metal electrode through the data contact hole. And a data protection electrode formed to cover the data pad.

The data pad part may include a data pad formed in the same pattern as the semiconductor layer and a data protection electrode formed to cover the data pad.

The data pad part includes a second metal electrode formed on the substrate, a data pad formed in the same pattern as the semiconductor layer, and a data protection electrode formed to cover the data pad.

And a transparent conductive pattern formed to cover the data line along the data line.

The thin film transistor formed at the intersection of the data line and the gate line has the same pattern as the gate electrode connected to the gate line, the active layer formed on the gate insulating layer, the ohmic contact layer formed on the active layer, and the ohmic contact layer. And a pixel electrode connected to the source and drain electrodes to be formed.

The storage capacitor part formed at an overlapping portion of the pixel electrode and the gate line includes a semiconductor layer formed in an area corresponding to the gate line, and a storage electrode connected to the pixel electrode and formed in the same pattern as the semiconductor layer. do.

In order to achieve the above object, a method of manufacturing a liquid crystal display device according to the present invention comprises the steps of forming a gate pad with a first mask on a substrate, a gate insulating material and a semiconductor material to cover the gate pad on the substrate After deposition, simultaneously patterning the gate insulating material and the semiconductor material with a second mask to form a gate contact hole through the gate insulating film and the semiconductor material to expose the gate pad, and on the substrate on which the gate contact hole is formed. Depositing a data metal on the substrate and simultaneously patterning the data metal and the semiconductor material with a third mask to form a metal electrode connected to the semiconductor layer and the gate pad, and directly contacting the metal electrode and the metal electrode. Forming a gate protection electrode on the gate insulating layer using a fourth mask.

The method of manufacturing the liquid crystal display device may include forming a gate electrode on a substrate with a first mask, simultaneously patterning the semiconductor material and data metal with a third mask to form a semiconductor layer and a data metal pattern; Forming a pixel electrode on the gate insulating layer using a four mask, and forming a channel, a source, and a drain electrode by patterning the data metal pattern using the pixel electrode as a mask.

The manufacturing method of the liquid crystal display device may include forming a gate line on a substrate with a first mask, and forming a semiconductor layer and a storage electrode by patterning a semiconductor material and a data metal with a third mask. do.

The forming of the data pad part on one side of the data line orthogonal to the gate line may include forming a second metal electrode on the substrate with a first mask, and a data contact hole exposing the second metal electrode with the second mask. And forming a data pad connected to the second metal electrode through the data contact hole with the third mask, and forming a data protection electrode to cover the data pad with the fourth mask. It is done.

Forming a data pad part on one side of the data line orthogonal to the gate line may include forming a semiconductor layer and a data pad of the same pattern by patterning a semiconductor material and a data metal with a third mask, and covering the data pad. And forming a data protection electrode with four masks.

The forming of the data pad portion on one side of the data line orthogonal to the gate line may include forming a second metal electrode on the substrate with a first mask, patterning the semiconductor material and the data metal with a third mask, Forming a semiconductor layer and a data pad, and forming a data protection electrode with a fourth mask to cover the data pad.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the accompanying examples.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 through 12D.

4 is a plan view illustrating a lower substrate of the liquid crystal display according to the first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating a lower substrate of the liquid crystal display illustrated in FIG. 4.

4 and 5, the lower substrate 51 of the liquid crystal display according to the first embodiment of the present invention is a TFT portion TP positioned at an intersection of the data line 54 and the gate line 52. A pixel electrode 72 connected to the drain electrode 60 of the TFT portion TP, a storage capacitor portion SP positioned at an overlapping portion of the pixel electrode 72 and the gate line 52, and data; A gate pad portion GP and a data pad portion DP formed at one end of the line 54 and the gate line 52 are provided.

The TFT portion TP includes a gate electrode 56 connected to the gate line 52, a source electrode 58 connected to the data line 54, and a drain electrode 60 connected to the pixel electrode 72. . In addition, the TFT portion TP further includes semiconductor layers 64 and 66 for forming a conductive channel between the source electrode 58 and the drain electrode 60 by the gate voltage supplied to the gate electrode 56. . The TFT portion TP selectively supplies the data signal from the data line 54 to the pixel electrode 72 in response to the gate signal from the gate line 52.

In order to prevent a defect from disconnection of the data line 54 supplying the data signal, a transparent electrode pattern 88 is formed along the data line 54. The transparent electrode pattern 88 is formed at the same time as the pixel electrode 72, and the transparent electrode pattern 88 enables redundancy when the data line 54 is disconnected, thereby preventing defects in the data line 54. Can be.

The pixel electrode 72 is formed in a cell region divided by the data line 54 and the gate line 52 and is made of a transparent conductive material having high light transmittance. The pixel electrode 72 is formed on the gate insulating film 62, the source and drain electrodes 58 and 60, and is electrically connected to the drain electrode 60. The pixel electrode 72 generates a potential difference from a common transparent electrode (not shown) formed on an upper substrate (not shown) by a data signal supplied through the TFT portion TP. Due to this potential difference, the liquid crystal located between the lower substrate 51 and the upper substrate (not shown) rotates due to the dielectric anisotropy. The amount of light transmitted from the light source to the upper substrate through the pixel electrode 72 is adjusted by the rotated liquid crystal.

The storage capacitor part SP serves to suppress voltage fluctuation of the pixel electrode 72. The storage capacitor part SP is formed of the storage electrode 74 formed with the gate line 52 and the gate insulating layer 62 interposed therebetween. The active layer 64 and the ohmic contact layer 66 having the same pattern as the storage electrode 74 are formed below the storage electrode 74, and the pixel electrically contacting the storage electrode 74 is formed on the storage electrode 74. An electrode 72 is formed.

The gate pad part GP and the data pad part DP are formed at one end of each of the gate line 52 and the data line 54, and are connected to a driving IC. The gate pad part GP supplies a gate signal for controlling the TFT to the gate line 52, and the data pad part DP supplies a data signal for controlling the TFT to the data line 54.

The gate pad 82 of the gate pad part GP is electrically connected to the gate pad upper electrode 84 through the gate contact hole 68a penetrating through the gate insulating layer 62, the active layer 64, and the ohmic contact layer 66. In addition to being in contact with each other, the gate protection electrode 86 is also electrically contacted. The gate pad upper electrode 84 is formed of the same metal as the source and drain electrodes 58 and 60 to be in contact with the gate pad 82 having a low resistance to compensate for signal delay caused by the gate pad 82. Accordingly, the gate pad 82 formed in at least a two-layer structure can be formed in a single layer using aluminum (Al) or an aluminum alloy.

The data pad 78 of the data pad part DP is electrically connected to the data pad lower electrode 76 through the data contact hole 68b passing through the gate insulating layer 62, the active layer 64, and the ohmic contact layer 66. In addition to being in contact with each other, it is also in electrical contact with the data protection electrode (80).

The TFT portion TP of the lower substrate of the liquid crystal display according to the first exemplary embodiment of the present invention is protected by using an alignment layer (not shown) formed to cover the gate insulating layer 62 and the pixel electrode 72. Done.

6A through 6D are cross-sectional views illustrating a method of manufacturing a lower substrate of the liquid crystal display shown in FIG. 5.

Referring to FIG. 6A, a gate metal layer is deposited on the substrate 51 by a deposition method such as sputtering. As the gate metal layer, aluminum (Al), aluminum-nedium (AlNd), or the like is used in a single layer structure. Subsequently, a first mask (not shown) is aligned on the substrate 51, and the gate metal layer is patterned by the photolithography process for the exposure, development, and etching processes. Accordingly, the gate electrode 56, the gate line 52, the gate pad 82, and the data pad lower electrode 76 are formed on the substrate 51.

Referring to FIG. 6B, a gate insulating layer 62 is formed on the substrate 51 on which the gate electrode 56, the gate line 52, the gate pad 82, and the data pad lower electrode 76 are formed. As the gate insulating layer 62, silicon oxide (SiOx) or silicon nitride (SiNx), which is an inorganic insulating material, is used. The first and second semiconductor layers 65a and 65b are continuously deposited on the gate insulating layer 62 by a chemical vapor deposition method. The first semiconductor layer 65a is formed of amorphous silicon that is not doped with impurities, and the second semiconductor layer 65b is formed of amorphous silicon that is doped with N-type or P-type impurities. Subsequently, a second mask (not shown) is aligned on the first and second semiconductor layers 65a and 65b, and the gate insulating film 62, the first and the second photolithography and etching processes including an exposure and development process are performed. The second semiconductor layers 65a and 65b are patterned. As a result, a gate contact hole 68a for exposing a part of the surface of the gate pad 82 is formed on the substrate 51, and a data contact hole 68b for exposing a part of the surface of the data pad lower electrode 76 is formed. do.

Referring to FIG. 6C, the data metal layer is entirely deposited on the substrate 51 by the CVD method or the sputtering method so as to cover the second semiconductor layer 68b. As the data metal layer, a metal such as molybdenum (Mo), titanium (Ti), tungsten (W) or tantalum (Ta), or a molybdenum alloy (Mo alloy) such as MoW, MoTa or MoNb is selected. A third mask (not shown) is aligned on the data metal layer, and the data metal layer and the first and second semiconductor layers 65a and 65b are simultaneously patterned by a photolithography process and a wet etching process including an exposure and development process. Accordingly, the active layer 64, the ohmic contact layer 66, the data metal pattern 59, the storage electrode 74, the gate pad upper electrode 84, and the data pad 78 are formed on the substrate 51.

Referring to FIG. 6D, the transparent conductive material covers the active layer 64, the ohmic contact layer 66, the data metal pattern 59, the storage electrode 74, the gate pad upper electrode 84, and the data pad 78. This front surface is deposited. The transparent conductive material may be selected from indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (IZO). A fourth mask (not shown) is arranged on the substrate 51 on which the transparent conductive material layer is deposited, and patterned by an exposure and development process followed by an etching process to thereby form the pixel electrode 72, the gate protection electrode 86, and data. The protective electrode 80 is formed. Thereafter, a part of the data metal pattern 59 is removed by using the pixel electrode 72 as a mask to form separate source and drain electrodes 58 and 60 with a predetermined interval therebetween. The ohmic contact layer 66 exposed between the separated source electrode 58 and the drain electrode 60 is removed by a dry etching process. By partially removing the ohmic contact layer 66, the portion of the active layer 64 corresponding to the gate electrode 56 between the source and drain electrodes 58 and 60 becomes a channel.

In the manufacturing process of the liquid crystal display device according to the first embodiment of the present invention, a first mask for patterning the gate electrode 56, the gate line 52, the data pad lower electrode 76, and the gate pad 82 is provided. A second mask for patterning the gate contact hole 68a and the data contact hole 68b, the data line 52, the upper gate pad electrode 84, the data pad 78, the active layer 64 and the ohmic contact layer Source and drain electrodes 58 and 60 of the third mask and TFT for patterning 66, transparent electrode pattern 88, pixel electrode 72, gate protection electrode 86 and data protection electrode 80 There is a need for a fourth mask for patterning.

FIG. 7 is a plan view illustrating a lower substrate of the liquid crystal display according to the second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view illustrating a lower substrate of the liquid crystal display illustrated in FIG. 7.

7 and 8, the lower substrate of the liquid crystal display according to the second exemplary embodiment of the present invention has a data pad portion 78 compared to the lower substrate of the liquid crystal display shown in FIGS. 4 and 5. And the same components except for the data protection electrode 80.

The data pad part DP of the liquid crystal display according to the second exemplary embodiment of the present invention includes a data pad 78 having the same pattern as the semiconductor layers 64 and 66 and a data protection electrode formed on the data pad 78. 80 is provided. Accordingly, the number of pattern formations can be relatively reduced, thereby lowering the defective rate.

The gate pad 82 of the gate pad part GP is electrically connected to the gate pad upper electrode 84 through the gate contact hole 68a penetrating through the gate insulating layer 62, the active layer 64, and the ohmic contact layer 66. The gate pad upper electrode 84 is in electrical contact with the gate protection electrode 86. The gate pad upper electrode 84 is made of the same metal as the source and drain electrodes 58 and 60 to compensate for signal delay caused by the gate pad 82 having a low resistance. Accordingly, the gate pad 82 formed in at least a two-layer structure can be formed in a single layer using aluminum (Al), aluminum alloy (AlNd), or the like.

The transparent electrode pattern 88 is formed on the data line 54 along the data line 54. The transparent electrode pattern 88 allows the data signal to be supplied to the pixel electrode 72 along the transparent electrode pattern 88 when the data line 54 is disconnected. That is, the transparent electrode pattern 88 allows redundancy to prevent defects in the data line 54.

9A to 9D illustrate a method of manufacturing a lower substrate of the liquid crystal display shown in FIG. 8.

First, the gate metal layer is deposited on the substrate 51 by a deposition method such as sputtering, and then patterned by using a first mask, so that the gate electrode 56, the gate line 62 and The gate pad 82 is formed. Then, the gate insulating film 62 is formed by depositing an insulating material on the substrate 51 so as to cover them. After sequentially depositing the first and second semiconductor layers 65a and 65b on the gate insulating layer 62, the gate insulating layer 62 and the first and second semiconductor layers 65a and 65b are formed using a second mask. By patterning, the gate contact hole 68a is formed as shown in FIG. 9B. Thereafter, the data metal layer is deposited to cover the second semiconductor layer 65b, and then the data metal layer and the first and second semiconductor layers 65a and 65b are simultaneously patterned using a third mask, as shown in FIG. 9C. The active layer 64, the ohmic contact layer 66, the data metal pattern 59, the storage electrode 74, the gate pad upper electrode 84, and the data pad 78 are formed. A transparent conductive material is deposited on the substrate 51 to cover them, and then patterned using a fourth mask, so that the pixel electrode 72, the gate protection electrode 86, and the data protection electrode 80 are shown in FIG. 9D. ) Is formed. Thereafter, a part of the data metal pattern 59 is removed by using the pixel electrode 72 as a mask to form separate source and drain electrodes 58 and 60 with a predetermined interval therebetween. The ohmic contact layer 66 exposed between the separated source electrode 58 and the drain electrode 60 is removed by a dry etching process. By partially removing the ohmic contact layer 66, the portion of the active layer 64 corresponding to the gate electrode 56 between the source and drain electrodes 58 and 60 becomes a channel.

FIG. 10 is a plan view illustrating a lower substrate of the liquid crystal display according to the third exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view illustrating a lower substrate of the liquid crystal display illustrated in FIG. 10.

Referring to FIGS. 10 and 11, the lower substrate of the liquid crystal display according to the third exemplary embodiment of the present invention has data of the data pad part DP compared to the lower substrate of the liquid crystal display of FIGS. 4 and 5. The same components are provided except that the pad lower electrode 76, the data pad 78, and the data protection electrode 80 are formed.

By forming the data pad part DP as the data pad lower electrode 76, the data pad 78, and the data protection electrode 80, the data pad part DP maintains the same height as the gate pad part GP. . Accordingly, when the tape carrier package (hereinafter referred to as "TCP") on which the driving IC is mounted is contacted with the gate protection electrode 86 and the data protection electrode 80 by the TAB method, the pressure applied to the TCP is applied. Become the same. Since the TCP applied with the same pressure can be uniformly adhered to the gate protection electrode 86 and the data protection electrode 80, the adhesion uniformity is improved and the workability of the TAB process is improved.

12A to 12D illustrate a method of manufacturing a lower substrate of the liquid crystal display shown in FIG. 10.

First, the gate metal layer is deposited on the substrate 51 by a deposition method such as sputtering, and then patterned by using a first mask, so that the gate electrode 56, the gate line 62, The gate pad 82 and the data pad lower electrode 76 are formed. Then, the gate insulating film 62 is formed by depositing an insulating material on the substrate 51 so as to cover them. After sequentially depositing the first and second semiconductor layers 65a and 65b on the gate insulating layer 62, the gate insulating layer 62 and the first and second semiconductor layers 65a and 65b are formed using a second mask. By patterning, the gate contact hole 68a is formed as shown in FIG. 12B. Thereafter, the data metal layer is deposited to cover the second semiconductor layer 68b, and then the data metal layer and the first and second semiconductor layers 65a and 65b are simultaneously patterned using a third mask, as shown in FIG. 12C. The active layer 64, the ohmic contact layer 66, the data metal pattern 59, the storage electrode 74, the gate pad upper electrode 84, and the data pad 78 are formed. By transparently depositing a transparent conductive material on the substrate 51 so as to cover them, and then patterning it using a fourth mask, the pixel electrode 72, the gate protection electrode 86, and the data protection electrode 80 as shown in FIG. 12D. ) Is formed. Thereafter, a part of the data metal pattern 59 is removed by using the pixel electrode 72 as a mask to form separate source and drain electrodes 58 and 60 with a predetermined interval therebetween. The ohmic contact layer 66 exposed between the separated source electrode 58 and the drain electrode 60 is removed by a dry etching process. By partially removing the ohmic contact layer 66, the portion of the active layer 64 corresponding to the gate electrode 56 between the source and drain electrodes 58 and 60 becomes a channel.

In the first to third embodiments of the present invention, the storage electrode, the active layer and the ohmic contact layer under the storage electrode may be omitted.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention can form the gate pad as a single layer by forming the gate pad upper electrode as the data metal layer between the gate protection electrode and the gate pad, so that the yield is improved. In addition, redundancy is possible due to the transparent electrode pattern formed along the data line on the data line, thereby preventing line defects. In addition, the production cost can be reduced by using a total of four masks to form the liquid crystal display device, thereby improving the yield.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing a lower substrate of a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view illustrating a lower substrate of the liquid crystal display device taken along the lines "A1-A1 '", "A2-A2'", and "A3-A3 '" in FIG.

3A to 3E are cross-sectional views illustrating a method of manufacturing a lower substrate of the liquid crystal display shown in FIG. 2.

4 is a plan view illustrating a lower substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a lower substrate of the liquid crystal display device taken along the lines "B1-B1 '", "B2-B2'", and "B3-B3 '" in FIG.

6A through 6D are cross-sectional views illustrating a method of manufacturing the lower substrate for the liquid crystal display device illustrated in FIG. 5.

7 is a plan view illustrating a lower substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a lower substrate of the liquid crystal display taken along the lines "C1-C1 '", "C2-C2'", and "C3-C3 '" in FIG.

9A to 9D are cross-sectional views illustrating a method of manufacturing the lower substrate for the liquid crystal display device illustrated in FIG. 8.

10 is a plan view illustrating a lower substrate of a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a lower substrate of the liquid crystal display device taken along the lines "D1-D1 '", "D2-D2'", and "D3-D3 '" in FIG.

12A through 12D are cross-sectional views illustrating a method of manufacturing a lower substrate of the liquid crystal display shown in FIG. 11.

<Explanation of symbols for the main parts of the drawings>

1,51: substrate 2,52: gate line

4,54 data line 6,56 gate electrode

8.58: source electrode 10,60: drain electrode

12,62: gate insulating film 14,64: active layer

16,66: ohmic contact layer 18,68: protective layer

22,72 pixel electrode 24,74 storage electrode

28,78: Data pad 30, 80: Data protection electrode

32,82 gate pad 34,84 gate protection electrode

Claims (16)

A signal pad connected to one end of a signal line formed on the substrate; A gate insulating film formed to cover the signal pad; A semiconductor layer formed on the gate insulating film; A pad contact hole penetrating the gate insulating film and the semiconductor layer to expose the signal pad; A metal electrode contacting the signal pad through the pad contact hole; And a pad protective electrode in direct contact with the metal electrode and formed on the gate insulating layer and the metal electrode. The method of claim 1, The metal electrode is formed of any one of molybdenum (Mo), chromium (Cr), tantalum (Ta), tungsten (W). The method of claim 1, Wherein the signal line is a gate line, and the signal pad is formed of aluminum (Al) or an aluminum alloy. The method of claim 3, wherein And a data pad portion formed at one end of the data line orthogonal to the gate line. The method of claim 4, wherein The data pad unit A second metal electrode formed on the substrate; A data contact hole penetrating the gate insulating film and the semiconductor layer to expose the second metal electrode; A data pad connected to the second metal electrode through the data contact hole; And a data protection electrode formed to cover the data pad. The method of claim 4, wherein The data pad unit A data pad formed in the same pattern as the semiconductor layer; And a data protection electrode formed to cover the data pad. The method of claim 4, wherein The data pad unit A second metal electrode formed on the substrate; A data pad formed in the same pattern as the semiconductor layer; And a data protection electrode formed to cover the data pad. The method of claim 4, wherein And a transparent conductive pattern formed to cover the data line along the data line. The method of claim 4, wherein The thin film transistor formed at the intersection of the data line and the gate line is A gate electrode connected to the gate line; An active layer formed on the gate insulating film; An ohmic contact layer formed on the active layer; Source and drain electrodes formed in the same pattern as the ohmic contact layer; And a pixel electrode connected to the source and drain electrodes. The method of claim 9, The storage capacitor part formed on the overlapping portion of the pixel electrode and the gate line. A semiconductor layer formed in a region corresponding to the gate line; And a storage electrode connected to the pixel electrode and formed in the same pattern as the semiconductor layer. Forming a gate pad on the substrate with a first mask, Depositing a gate insulating material and a semiconductor material to cover the gate pad on the substrate, and simultaneously patterning the gate insulating material and the semiconductor material with a second mask to expose the gate pad through the gate insulating film and the semiconductor material. Forming a gate contact hole; Depositing data metal on the substrate on which the gate contact hole is formed, and simultaneously patterning the data metal and the semiconductor material with a third mask to form a metal electrode connected to the semiconductor layer and the gate pad; And forming a gate protection electrode on the metal electrode and the gate insulating layer so as to be in direct contact with the metal electrode. The method of claim 11, Forming a gate electrode on the substrate with the first mask; Simultaneously patterning the semiconductor material and the data metal with the third mask to form a semiconductor layer and a data metal pattern; Forming a pixel electrode on the gate insulating layer using the fourth mask; And patterning the data metal pattern using the pixel electrode as a mask to form a channel, a source, and a drain electrode. The method of claim 11, Forming a gate line on the substrate with the first mask; And patterning the semiconductor material and the data metal with the third mask to form a semiconductor layer and a storage electrode. The method of claim 13, Forming a data pad part on one side of the data line orthogonal to the gate line; The forming of the data pad part may include: Forming a second metal electrode on the substrate with the first mask; Forming a data contact hole exposing the second metal electrode with the second mask; Forming a data pad connected to the second metal electrode through the data contact hole with the third mask; And forming a data protection electrode to cover the data pad with the fourth mask. The method of claim 13, Forming a data pad part on one side of the data line orthogonal to the gate line; The forming of the data pad part may include: Patterning the semiconductor material and the data metal with the third mask to form a semiconductor layer and a data pad of the same pattern; Forming a data protection electrode with the fourth mask so as to cover the data pad. The method of claim 13, Forming a data pad part on one side of the data line orthogonal to the gate line; The forming of the data pad part may include: Forming a second metal electrode on the substrate with the first mask; Patterning the semiconductor material and the data metal with the third mask to form a semiconductor layer and a data pad of the same pattern; Forming a data protection electrode with the fourth mask so as to cover the data pad.