KR100646784B1 - a thin film transistor array panel for a liquid crystal display and a manufacturing method thereof - Google Patents

Abstract

A plurality of storage wirings including a plurality of storage electrode lines and the storage electrodes and a plurality of gate wirings are formed on the substrate. The gate wiring and the sustain wiring are covered with a gate insulating film, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. A common bar adjacent to the sustain electrode line and a plurality of data lines are formed on the ohmic contact layer and the gate insulating film. A protective film is formed thereon with contact holes exposing the ends of the plurality of sustain electrode lines and a part of the common bar together. A pixel electrode is formed on the passivation layer, and a common pattern for connecting the plurality of storage electrode lines and the common bar through the contact hole is also formed. Here, the common bar connected to the plurality of storage electrode lines is formed of a film containing aluminum and molybdenum and has low resistance. In addition, the plurality of storage electrode lines and the common bar may overlap each other. In this case, the storage electrode line and the common bar are connected through the first common pattern, and the storage electrode lines are connected to each other through the second common pattern to form a parallel resistor. Therefore, the resistance between the common bar and the storage electrode line can be lowered. In this way, by reducing the resistance of the common bar to reduce the signal delay applied to the sustain electrode line can reduce the screen failure.

Holding electrode wire, resistance, parallel connection, bad screen

Description

A thin film transistor array panel for a liquid crystal display and a manufacturing method

1 is a layout view schematically illustrating a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view illustrating a pixel area and a pad part of a part II in FIG. 1;

3 is a cross-sectional view taken along line III-III of FIG. 2,

4 is an enlarged layout view of a portion IV in FIG. 1;

5 is a cross-sectional view taken along the line VV of FIG. 4;

6A is a layout view of a thin film transistor substrate in a first step of manufacturing in accordance with the present invention;

FIG. 6B is a cross-sectional view taken along the VIb-VIb line in FIG. 6A;

FIG. 7A is a layout view at the first stage of fabricating a portion of the thin film transistor substrate of FIG. 4 in accordance with the present invention; FIG.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb of FIG. 7A;

FIG. 8a is a layout view in the next step of FIG. 6a;

FIG. 8B is a cross-sectional view taken along the line VIIb-VIIb of FIG. 8A;

FIG. 9A is a layout view in the next step of FIG. 7A;

FIG. 9B is a cross-sectional view taken along the line VIIb-VIIb of FIG. 9A;

FIG. 10A is a layout view in the next step of FIG. 8A;

FIG. 10B is a cross-sectional view taken along the line VIIb-VIIb of FIG. 10A;

FIG. 11A is a layout view of the next step of FIG. 9A;

FIG. 11B is a cross-sectional view taken along the line XIB-XIB in FIG. 11A;

12A is a layout view at the next step of FIG. 10A;

FIG. 12B is a cross-sectional view taken along the line IIb-VIIll of FIG. 12A,

FIG. 13A is a layout view of the next step of FIG. 11A;

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb in FIG. 13A;

FIG. 14 is an enlarged layout view of another structure of the IV part of FIG. 1;

FIG. 15 is a cross-sectional view taken along the line XV-XV in FIG. 14;

FIG. 16 is an equivalent circuit diagram of the part XVI of FIG. 14.

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display device has a structure in which a liquid crystal is injected between two substrates, and an amount of light transmission is controlled by adjusting an intensity of an electric field applied thereto.

It is common to have a thin film transistor for switching a voltage applied to an electrode on one substrate of the liquid crystal display, and the thin film transistor substrate includes a pixel electrode, a gate line, and a data line electrically connected to the thin film transistor in addition to the thin film transistor. A gate pad and a data pad are formed to receive a scan signal or an image signal from an external wiring, and to transfer the scan signal or image signal to a gate line and a data line. A color filter is formed on the other substrate, a black matrix is formed between the color filters on the color filter substrate, and a common electrode which forms an electric field together with the pixel electrode of the thin film transistor substrate is also formed.

In the lower plate of the liquid crystal display, a storage line is formed to overlap the pixel electrode to form a storage capacitor which improves the charge storage capability of the pixel. The common voltage applied to the common electrode of the upper plate is transferred to the storage line. At this time, parasitic capacitance occurs between them due to the coupling of the sustain wiring and the data line. If the delay of the common signal transmitted through the sustain wiring increases due to the parasitic capacitance, crosstalk or flicker may be severe and the degree of screen defect may be increased. It gets worse.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of reducing a screen defect by minimizing a signal delay of a sustain line.

In order to achieve this problem, the present invention connects the plurality of storage electrode lines and the common bar through a common pattern, and forms the common bar as a film including aluminum and molybdenum.

After the plurality of storage electrode lines and the common bar are overlapped, the resistance between the common bar and the storage electrode line is lowered by connecting the plurality of storage electrode lines and the common bar through a common pattern and connecting the plurality of storage electrode lines to each other to add parallel resistance to the common bar.

According to the present invention, a gate wiring including a plurality of gate lines, a gate electrode which is part of a gate line, and a gate pad connected to the gate line is formed on an insulating substrate. A sustain wiring including a plurality of sustain electrode lines and sustain electrodes connected to the sustain electrode lines is formed between the gate lines. The gate wiring and the sustain wiring are covered with a gate insulating film, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating film. A data line is formed on the ohmic contact layer and the gate insulating layer, the data line including a plurality of data lines crossing the gate line, a source electrode which is part of the data line, a drain electrode separated from the source electrode, and a data pad connected to the data line. A common bar that is formed in the same direction as the data line is formed adjacent thereto. A passivation film is formed on the data line, having a drain electrode, a gate pad, and first to third contact holes respectively exposing the data pad and a fourth contact hole exposing a part of the storage electrode line and the common bar together. On the passivation layer, a pixel electrode connected to the drain electrode through the first contact hole, an auxiliary gate pad connected to the gate pad through the second contact hole, and an auxiliary data pad connected to the data pad through the third contact hole are formed. It is. In addition, a first common pattern is formed on the protective film to connect the plurality of storage electrode lines and the common bar through the fourth contact hole.

The common bar may be made of a single film or a multilayer film including aluminum and molybdenum.

The common bar may overlap a plurality of storage electrode lines, and in this case, a fifth contact hole may be further formed on the passivation layer to expose a portion of the storage electrode lines adjacent to each other, and may connect the storage electrode lines adjacent to each other through the fifth contact hole. It may further include a second common pattern.

In the manufacturing method of the present invention, by reducing the resistance of the common bar, a signal delay occurring when a signal is transmitted to the sustain electrode line through the common bar can be reduced.

Next, a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same. do.

First, a schematic structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIG. 1.

A plurality of gate lines 20 extend in the horizontal direction on the insulating substrate 10, and a plurality of gate pads 23 are connected to ends of each gate line 20. A plurality of storage electrode lines 25 are formed between the gate lines 20, and the plurality of storage electrode lines 25 are electrically connected to each other through the common bar 65. In the vertical direction, a plurality of data lines 60 are formed that are insulated from and intersect the gate lines 20 to define the plurality of pixel regions P. A plurality of data pads 64 are connected to the ends of the data line 60. Although not shown in the drawings, a plurality of common signal pads that receive a common signal from the outside may be connected to the sustain electrode line 25 of the wiring in consideration of the delay of the common signal due to the resistance.

Next, the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 2 to 5.

2 is a layout view illustrating a pixel area and a pad part of a part II in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2. 4 is an enlarged layout view of a portion IV in FIG. 1, and FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4.

First, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta) on the insulating substrate 10 as shown in FIGS. Gate wirings and holding wirings made of metal or conductors such as these are formed. The gate wiring is connected to one end of the gate line 20 extending in the horizontal direction, the gate electrode 21 that is part of the gate line 20, and the gate line 20, and receives a scan signal from the outside to the gate line 20. And a gate pad 23 for transmitting. The storage wiring is formed in the vertical direction and is formed in parallel with the storage electrode 26 and the gate line 20 overlapping the pixel electrode 80 formed later to form the storage capacitor, and are common to the storage electrode 26. The storage electrode line 25 which transmits a signal is included.

The gate insulating film 30 such as silicon nitride is covered on the gate wirings 20, 21, 23 and the storage wirings 25, 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 on the gate electrode 21, and an amorphous silicon doped with n-type impurities is formed on the semiconductor layer 40. The ohmic contacts 51 and 52 formed on the gate electrode 21 are separated from each other.

On the ohmic contact layers 51 and 52 and the gate insulating film 30, the common bars 65 and the data lines 60, 61, 62, 64 made of metal or conductors of a single film or a multilayer film containing aluminum and molybdenum having a low specific resistance are formed. ) Is formed. The data line crosses the gate line 20 to define a pixel area, and the data line 60 extending in the vertical direction, the drain separated from the source electrode 61 and the source electrode 61 which are part of the data line 60. The electrode 62 includes a data pad 64 connected to one end of the data line 60 to receive an image signal from the outside and transmit the image signal to the data line 60. The common bar 65 is formed in the vertical direction at a predetermined distance adjacent to the storage electrode line 25.

The passivation film 70 is formed on the data wires 60, 61, 62, and 64, the common bar 65, the semiconductor layer 40, and the gate insulating film 30.

In the passivation layer 70, a contact hole 72 exposing the drain electrode 62 together with the gate insulating layer 30, a contact hole 74 exposing the data pad 64, and a contact hole 73 exposing the gate pad 23 are provided. Is formed. In the passivation film 70, a contact hole 75 which exposes an end portion of the storage electrode line 25 and a part of the common bar 65 together with the gate insulating film 30 is formed for each storage electrode line 25. .

On the passivation layer 70, a pixel electrode 80 connected to the drain electrode 62 is formed through a contact hole 72 made of a transparent conductive material such as ITO, and the pixel electrode 80 has a curved corner. It is connected in several ways. The pixel electrode 80 may be patterned in various shapes, in order to divide and align the liquid crystal molecules into multiple regions by using a fringe field to improve the viewing angle of the liquid crystal display. The pixel electrode 80 of this type may be applied to a liquid crystal display of a twisted nematic (TN) or vertically aligned (VA) method.

Here, the pixel electrode 80 overlaps with the storage electrode line 25 and the storage electrode 26 to form a storage capacitor. On the gate pad 23 and the data pad 64 are formed auxiliary gate pads 83 and auxiliary data pads 84 which are connected to them through contact holes 73 and 74, respectively, which are pads 23 and 64. ) And to protect the pads (23, 64), and is not essential. In addition, a common pattern 85 that connects the storage electrode line 25 and the common bar 65 through the contact hole 75 is formed in the same layer as the pixel electrode 80.

Herein, a transparent conductive material such as ITO is used as the material of the pixel electrode 80, but an opaque conductive material such as chromium or aluminum may be used.

Here, if the line width a of the common bar 65 is increased or the common bar 65 is formed of a metal or a conductor of a single film or a multilayer film containing aluminum and molybdenum having a low specific resistance, the resistance of the common bar 65 may be lowered. Therefore, the delay of the signal through the sustain electrode line 25 can be prevented. In addition, when the size of the contact hole 75 is increased, it is easier for the signal applied to the common bar 65 to be transmitted to the storage electrode line 25 through the common pattern 85.

A method of manufacturing the thin film transistor substrate for a liquid crystal display device will be described with reference to FIGS. 6A to 13B.

First, as shown in FIGS. 6A to 7B, the gate wiring conductor is deposited and patterned on the substrate 10 by a method such as sputtering, to form the gate wirings 20, 21, 23, the storage electrode lines 25, and the storage electrodes 26. To form.

Subsequently, as shown in FIGS. 8A to 9B, the gate insulating layer 30, the semiconductor layer 40, and the ohmic contact layer 50 are sequentially deposited by chemical vapor deposition, and then the upper two layers are patterned.

Subsequently, as shown in FIGS. 10A to 11B, the data wiring conductor layer is deposited and patterned by a method such as sputtering to form the data wirings 60, 61, 62, 64 and the common bar 65, and then the source electrode 61. ) And the ohmic contact layer exposed between the drain electrode 62 and the drain electrode 62 are separated into two parts 51 and 52.

Next, as shown in FIGS. 12A to 13B, the protective layer 70 is deposited and patterned by chemical vapor deposition to form contact holes 72, 73, 74, and 75.

Next, as shown in FIGS. 2 to 5, a transparent conductive material such as ITO is deposited and patterned to form the pixel electrode 80, the auxiliary gate pad 83, the auxiliary data pad 84, and the common pattern 85.

In the thin film transistor substrate according to the first exemplary embodiment of the present invention, a plurality of pads connected to the common electrode 65 are connected to the plurality of storage electrode lines 25 through the common bar 65, and the common signal is maintained from the outside. By transmitting to the electrode lines 25, the resistance of the sustain wirings 25 and 26 can be lowered to reduce the signal delay. However, since the common bar 65 should not overlap the gate pad 23, there is a restriction in the space formed. Therefore, there is a limit in forming the common bar 65 at a distance from the storage electrode line 25. Therefore, a structure in which the common bar 65 overlaps with the storage electrode line 25 is preferable, which will be described with reference to FIGS. 14 to 16.

FIG. 14 is an enlarged layout view of another structure of part IV in FIG. 1, FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14, and FIG. 16 is an equivalent circuit diagram of part XVI in FIG. 14. .

As shown in FIGS. 14 and 15, the storage electrode line 25 is covered with the gate insulating layer 30, and the common bar 65 is formed to partially overlap the end of the storage electrode line 25 on the gate insulating layer 30. A passivation layer 70 is formed on the gate insulating layer 30 and the common bar 65, and a contact hole 75 exposing a part of the end of the storage electrode line 25 and a part of the common bar 65 together in the passivation layer 70. ) Is formed, and a contact hole 76 which exposes the neighboring storage electrode lines 25 together is formed. A first common pattern 85 is formed on the passivation layer 70 to connect the storage electrode line 25 and the common bar 65 through the contact hole 75, and the storage electrode line adjacent to each other through the contact hole 76 ( 25) The 2nd common pattern 86 which connects with each other is formed.

In this structure, the signal entered through the common bar 65 is transmitted to the storage electrode line 25 through the first and second common patterns 85 and 86. This will be described with reference to FIG. 16.

FIG. 16 is an equivalent circuit diagram of the part XVI in FIG. 14.

Here, there is a resistance C between the common bar 65 and the first common pattern 85 and a resistance A between the first common pattern 85 and the storage electrode line 25. In addition, there is a resistor B between each of the storage electrode lines 25 connected through the second common pattern 86. In this case, since the resistor B is connected in parallel with the resistor A, the resistance between the common bar 65 and the storage electrode line 25 may be lowered, thereby reducing the delay of the signal applied to the storage electrode line 25.

Here, the manufacturing method is the same as that of the embodiment of the present invention, in which only the contact hole 76 is further formed when the contact hole 75 is formed and the second common pattern 86 is formed when the pixel electrode 80 is formed. To form more.

As described above, in the present invention, crosstalk in the horizontal direction can be reduced by reducing the resistance of the common bar to reduce the delay of the signal.

Claims (5)

Insulation board, A gate wiring including a plurality of gate lines formed on the substrate, a gate electrode which is a part of the gate lines, and a gate pad connected to each of the gate lines; A sustain wiring including a plurality of sustain electrode lines respectively formed between the gate lines and sustain electrodes connected to the sustain electrode lines, respectively; A gate insulating film covering the gate wiring and the sustain wiring; A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A plurality of data lines formed on the ohmic contact layer and the gate insulating layer and intersecting the gate lines, a source electrode which is a part of the data line, a drain electrode separated from the source electrode, and a data pad connected to the data line; Data wiring, A common bar formed adjacent to the sustain electrode line in the same direction as the data line; First to third contact holes covering the data wires, the first and third contact holes respectively exposing the drain electrode and the gate pad, the data pads, and the fourth contact holes exposing a part of the storage electrode line and the common bar, and neighboring each other. A protective film having a fifth contact hole exposing a part of the sustain electrode line, A pixel electrode formed on the passivation layer and connected to the drain electrode through the first contact hole; An auxiliary gate pad formed on the passivation layer and connected to the gate pad through the second contact hole; An auxiliary data pad formed on the passivation layer and connected to the data pad through the third contact hole; A first common pattern formed on the passivation layer and connecting the plurality of storage electrode lines and the common bar through the fourth contact hole; and And a second common pattern formed between the storage electrode lines adjacent to each other and connecting the storage electrode lines adjacent to each other through the fifth contact hole. In claim 1, The common bar is a thin film transistor substrate for a liquid crystal display device comprising a single film or a multilayer film including aluminum and molybdenum. In claim 1, The common bar is a thin film transistor substrate for a liquid crystal display device overlapping the plurality of storage electrode lines. delete delete

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