KR102448543B1 - Display device and method for inspecting pad align of the same - Google Patents

Abstract

Embodiments of the present invention relate to a display device capable of inspecting an alignment error between pads of a flexible film and pads of a non-display area, and a pad alignment inspection method thereof.
A display device according to an embodiment of the present invention includes a display panel, a source drive IC, and a flexible film. A display panel of a display device according to an embodiment of the present invention includes a plurality of panel pads connected to data lines and a plurality of panel dummy pads adjacent to the panel pads. The flexible film of the display device according to the embodiment of the present invention includes a plurality of film pads connected to the panel pads and connected to the source drive IC, and a plurality of film dummy pads adjacent to the film pads.
According to an embodiment of the present invention, the panel dummy pads may be disposed at an interval different from the interval between the panel pads, and the film dummy pads may be disposed at a different interval from the interval between the film pads. According to an embodiment of the present invention, when an alignment error of a predetermined ratio or more occurs relative to the width of the panel pads, the panel dummy pad and the film dummy pad may be connected. According to an embodiment of the present invention, it may be determined whether an alignment error of a certain ratio or more has occurred compared to the width of the panel pads by using the alignment error information output from the panel dummy pads. Accordingly, according to the embodiment of the present invention, an alignment error between the pads of the flexible film and the pads of the non-display area can be automatically checked.

Description

DISPLAY DEVICE AND METHOD FOR INSPECTING PAD ALIGN OF THE SAME

Embodiments of the present invention relate to a display device and a pad alignment inspection method thereof.

As the information society develops, demands for display devices for displaying images are increasing in various forms, and in recent years, liquid crystal displays, plasma display panels, and organic light emitting displays Various flat panel display devices such as light emitting display devices are being used.

The display device includes a display panel and a source drive IC. The display panel includes a display area for displaying an image and a non-display area for not displaying an image. The display area includes data lines, gate lines, and a plurality of pixels formed at intersections of data lines and gate lines to receive data voltages of the data lines when gate signals are supplied to the gate lines. The pixels emit light with a predetermined brightness according to the data voltages. The non-display area may include pads connected to data lines.

The source drive IC may be manufactured as a driving chip. In this case, the source drive IC may be mounted on the flexible film. The flexible film may be implemented as a chip on film (COF). Pads that can be electrically connected are formed on the flexible film, and can be electrically connected with the pads of the non-display area.

Accordingly, when there is an error in alignment between the pads of the flexible film and the pads of the non-display area, data voltages of the source drive IC are not properly supplied to the data lines of the display panel. Even if there is an error in the alignment between the pads of the flexible film and the pads in the non-display area, it is difficult to check the alignment error. Accordingly, there is a need for a method of checking whether the source drive IC properly supplies the data voltages by checking the alignment error.

SUMMARY Embodiments of the present invention provide a display device capable of inspecting an alignment error between pads of a flexible film and pads of a non-display area, and a method of inspecting the alignment of the pads thereof.

A display device according to an embodiment of the present invention includes a display panel, a source drive IC, and a flexible film. A display panel of a display device according to an embodiment of the present invention includes a plurality of panel pads connected to data lines and a plurality of panel dummy pads adjacent to the panel pads. The flexible film of the display device according to the embodiment of the present invention includes a plurality of film pads connected to the panel pads and connected to the source drive IC, and a plurality of film dummy pads adjacent to the film pads. The panel dummy pads of the display device according to the embodiment of the present invention are disposed at different intervals from the panel pads, and the film dummy pads are disposed at different intervals from the film pads.

A pad alignment inspection method according to an embodiment of the present invention includes applying an input signal to a first panel dummy pad, applying output signals to the film dummy pads, and outputting alignment error signals from the film dummy pads includes

According to an embodiment of the present invention, the panel dummy pads may be disposed at an interval different from the interval between the panel pads, and the film dummy pads may be disposed at a different interval from the interval between the film pads. According to an embodiment of the present invention, when an alignment error of a predetermined ratio or more occurs relative to the width of the panel pads, the panel dummy pad and the film dummy pad may be connected. According to an embodiment of the present invention, it may be determined whether an alignment error of a certain ratio or more has occurred compared to the width of the panel pads by using the alignment error information output from the panel dummy pads. Accordingly, according to an embodiment of the present invention, an alignment error between the pads of the flexible film and the pads of the non-display area may be checked.

1 is a perspective view illustrating a display panel, a circuit board, a source drive IC, a timing control circuit, and a flexible film of a display device according to an embodiment of the present invention;
2 is a plan view illustrating in detail a lower substrate of the display device according to the first embodiment of the present invention;
3 is a plan view illustrating in detail a flexible film of a display device according to a first embodiment of the present invention;
4 is a cross-sectional view illustrating a combination of a panel pad and a film pad of a display device according to an embodiment of the present invention;
5 is a front view illustrating an alignment relationship between panel pads, panel dummy pads, film pads, and film dummy pads of the display device according to the first embodiment of the present invention;
6 is a plan view illustrating in detail a lower substrate of a display device according to a second exemplary embodiment of the present invention;
7 is a plan view illustrating in detail a flexible film of a display device according to a second exemplary embodiment of the present invention;
8 is a front view illustrating an alignment relationship between panel pads, panel dummy pads, film pads, and film dummy pads of a display device according to a second exemplary embodiment of the present invention;
9 is a block diagram illustrating panel dummy pads, film dummy pads, and a source drive IC of a display device according to an exemplary embodiment of the present invention.
10 is a detailed block diagram illustrating a source drive IC of a display device according to an exemplary embodiment of the present invention.
11 is a flowchart of a pad alignment inspection method according to an embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than the range in which the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 , a display device according to an embodiment of the present invention includes a display panel 100 , a circuit board 200 , a source drive integrated circuit (hereinafter referred to as “IC”) 300 , and a timing control circuit ( 400 ), and a flexible film 500 . The display device may be a liquid crystal display, a plasma display panel, an organic light emitting display device, or an electrophoretic display device.

The display panel 100 includes a lower substrate 110 and an upper substrate 120 . The lower substrate 110 serves as a support substrate. The lower substrate 110 may include a display area and a non-display area, and a detailed description thereof will be described later with reference to FIG. 2 . The upper substrate 120 serves as an encapsulation substrate.

The circuit board 200 may be attached to the flexible films 40 . A plurality of circuits implemented with driving chips may be mounted on the circuit board 200 . For example, the timing control circuit 400 may be mounted on the circuit board 200 . The circuit board 200 may be a printed circuit board or a flexible printed circuit board.

The source drive IC 300 receives digital video data and a source control signal from the timing control circuit 400 . The source drive IC 300 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source drive IC 300 is manufactured as a driving chip, it may be mounted on the flexible film 500 .

The timing control circuit 400 receives digital video data and a timing signal from an external system board (not shown). The timing controller 400 generates a gate control signal for controlling the operation timing of the gate driver (not shown) and a source control signal for controlling the source driver ICs 300 based on the timing signal. The timing controller 400 supplies a gate control signal to a gate driver (not shown) and supplies a source control signal to the source drive ICs 300 .

The flexible film 500 may connect the circuit board 200 and the display panel 100 . The flexible film 500 includes wires connecting the display panel 100 and the circuit board 200 and wires connecting the display panel 100 and the source drive IC 300 . The flexible film 500 is attached on the pads using an anisotropic conducting film, whereby the pads and wires of the flexible film 500 can be connected. The flexible film 500 may mount the source drive IC 300 .

Hereinafter, a display device according to a first embodiment of the present invention will be described with reference to FIGS. 2 to 5 .

2 and 3 , the lower substrate 110 is divided into a display area DA and a non-display area NDA. The display area DA is an area in which an image is displayed using pixels, and the non-display area NDA is an area in which an image is not displayed.

Gate lines and data lines are formed in the display area DA. Pixels may be formed in cross regions of the gate lines and the data lines. Pixels can display an image.

In the non-display area NDA, panel pads P1 and panel dummy pads DP1 are formed.

The flexible film 500 includes a source drive IC 300 , film pads P2 , and film dummy pads DP2 .

The panel pads P1 are connected to data lines. The panel pads P1 receive data voltages from the source drive IC 300 and supply data voltages to the data lines. The panel pads P1 may be connected to the film pads P2 provided on the flexible film 500 .

The panel dummy pads DP1 may be adjacent to the panel pads P1 and may be disposed on one side of the panel pads P1 . The panel dummy pads DP1 are not connected to the data lines. In FIG. 2 , the panel dummy pads DP1 are adjacent to the plurality of panel pads P1 and are arranged three at a time on one side of the panel pads P1 , but the present invention is not limited thereto. A small number of panel dummy pads DP1 may be provided.

The source drive IC 300 supplies data voltages to the film pads P2 through wires formed inside the flexible film 500 . The source drive IC 300 may be mounted on the flexible film 500 in a chip on film (COF) method.

The film pads P2 receive data voltages from the source drive IC 300 through wires formed inside the flexible film 500 . The film pads P2 are connected to the panel pads P1 and supply data voltages to the panel pads P1 .

The film dummy pads DP2 may be adjacent to the film pads P2 and may be disposed on one side of the film pads P2 . The film dummy pads DP2 are connected to the source drive IC 300 through wires formed inside the flexible film 500 . However, the film dummy pads DP2 do not receive data voltages from the source drive IC 300 . In FIG. 3 , the film dummy pads DP2 are adjacent to the plurality of film pads P2 and are arranged three at a time on one side of the film pads P2 , but the present invention is not limited thereto. A small number of film dummy pads DP2 may be provided.

As shown in FIG. 4 , the panel pads P1 on the display panel 100 and the film pads P2 on the flexible film 500 are connected using an anisotropic conductive film (ACF) 600 . The anisotropic conductive film 600 includes a conductive material. In FIG. 4 , only one of the panel pads P1 and the film pads P2 is illustrated for convenience.

When the flexible film 500 is connected to the display panel 100 , the panel pads P1 and the film pads P2 are connected to each other, and preferably in each region where the flexible film 500 is connected to the panel. The number of pads P1 and the number of film pads P2 are the same. Also, preferably, the number of panel dummy pads DP1 and the number of film dummy pads DP2 are the same in each region to which the flexible film 500 is connected.

Hereinafter, based on FIG. 5 , the panel pads P1-1 to P1-n, the film pads P2-1 to P2-n, the panel dummy pads DP1-1 to DP1-3, and the film dummy An alignment relationship of the pads DP-1 to DP-3 will be described.

The n (n is a positive integer) panel pads P1-1 to P1-n are connected to the n film pads P2-1 to P2-n. Each of the panel pads P1-1 to P1-n is connected to the data lines DL1 to DLn. The width W of each of the panel pads P1-1 to P1-n is the same. Also, the distance W1 between the respective panel pads P1-1 to P1-n is the same.

The n film pads P2-1 to P2-n are connected to the n panel pads P1-1 to P1-n. Each of the film pads P2-1 to P2-n is connected to the source drive IC 300 . The width W of each of the film pads P2-1 to P2-n is the same. In addition, the distance W1 between each of the film pads P2-1 to P2-n is the same.

The panel dummy pads DP1-1 to DP1-3 are disposed adjacent to the panel pads P1-1 to P1-n. 5 exemplifies a case in which there are three panel dummy pads DP1-1 to DP1-3, but the present invention is not limited thereto, and a smaller or larger number of panel dummy pads may be provided.

The first panel dummy pad DP1-1 may be connected to the second panel dummy pad DP1-2 through the first panel line PL1. Also, the first panel dummy pad DP1-1 may be connected to the third panel dummy pad DP1-3 through the second panel line PL2.

The panel dummy pads DP1-1 to DP1-3 may be disposed at an interval different from the interval W1 between the panel pads P1-1 to P1-n. The distance between the first panel dummy pad DP1-1 and the second panel dummy pad DP1-2 is defined as the first panel pad interval PW1, the second panel dummy pad DP1-2 and the third panel dummy pad. The interval between (DP1-3) is the second panel pad interval (PW2), and the interval between the third panel dummy pad (DP1-3) and the first panel pad (P1-1) is the third panel pad interval (PW3). it can be said

The film dummy pads DP-1 to DP-3 are disposed adjacent to the film pads P2-1 to P2-n. 5 exemplifies a case in which there are three film dummy pads DP-1 to DP-3, but the present invention is not limited thereto, and a smaller or larger number of film dummy pads may be provided. The film dummy pads DP-1 to DP-3 may be connected to the source drive IC 300 through wires.

The source drive IC 300 may generate an input signal SIG_IN for checking an alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n. The source drive IC 300 does not generate a separate input signal SIG_IN, but uses a signal generated by the source drive IC 300 such as a data enable signal for supplying data voltages to the input signal SIG_IN. is available as Accordingly, an alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n may be checked without designing a separate internal circuit.

The film dummy pads DP-1 to DP-3 may be disposed at a spacing different from the spacing W1 between the film pads P2-1 to P2-n. The distance between the first film dummy pad DP-1 and the second film dummy pad DP-2 is the first film pad distance FW1, the second film dummy pad DP-2 and the third film dummy pad The interval between (DP-3) is the second film pad interval (FW2), and the interval between the third film dummy pad (DP-3) and the first film pad (P2-1) is the third film pad interval (FW3). it can be said

The first panel pad spacing PW1 may be smaller than the first film pad spacing FW1. In an alignment error of 2/3 or less of the width W of the panel pads P1-1 to P1-n, the second panel dummy pad DP1-2 and the second film dummy pad DP-2 are not connected. does not When an alignment error of 2/3 or more of the width W of the panel pads P1-1 to P1-n occurs, the second panel dummy pad DP1-2 and the second film dummy pad DP-2 can be connected. Accordingly, it may be determined whether an alignment error of 2/3 or more of the width W of the panel pads P1-1 to P1-n occurs.

The second panel pad spacing PW2 may be smaller than the second film pad spacing FW2. In an alignment error of 1/3 or less of the width W of the panel pads P1-1 to P1-n, the third panel dummy pad DP1-3 and the third film dummy pad DP-3 are not connected. does not When an alignment error of 1/3 or more of the width W of the panel pads P1-1 to P1-n occurs, the third panel dummy pad DP1-3 and the third film dummy pad DP-3 can be connected. Accordingly, it may be determined whether an alignment error of 1/3 or more of the width W of the panel pads P1-1 to P1-n occurs.

The width WL of the first panel dummy pad DP1-1 may be greater than the width W of the panel pads P1-1 to P1-n. If the width WL of the first panel dummy pad DP1-1 is 1 to 3 times the width W of the panel pads P1-1 to P1-n, even if an alignment error occurs, the first The panel dummy pad DP1-1 may always be connected to the first film dummy pad DP-1. Accordingly, even if an alignment error occurs, the input signal SIG_IN for always checking the alignment error may be applied to the first panel dummy pad DP1-1.

The width W of the second and third panel dummy pads DP1-2 and DP1-3 may be the same as the width W of the panel pads P1-1 to P1-n.

The central axis of the first film dummy pad DP-1 is disposed to coincide with the central axis of the first panel dummy pad DP1-1. Accordingly, even if an alignment error occurs, the first film dummy pad DP-1 may always be connected to the first panel dummy pad DP1-1.

The width W of the film dummy pads DP-1 to DP-3 may be the same as the width W of the film pads P2-1 to P2-n.

In the display device according to the first embodiment of the present invention, the panel dummy pads DP1-1 to DP1-3 and the film dummy pads DP-1 to DP-3 are connected to the panel pads P1-1 to P1- n) and the film pads P2-1 to P2-n. Accordingly, in the display device according to the first embodiment of the present invention, the panel dummy pads DP1-1 to DP1-3 and the film dummy pads DP-1 to DP-3 are not additionally arranged, and the panel An alignment error between the pads P1-1 to P1-n and the film pads P2-1 to P2-n may be checked.

Hereinafter, a display device according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 8 .

6 and 7 , the lower substrate 110 includes a display area DA, a non-display area NDA, panel pads P1, and panel dummy pads DP1, and the flexible film 500 ) includes the source drive IC 300 , the film pads P2 , and the film dummy pads DP2 . The description of the display area DA, the non-display area NDA, the panel pads P1, the source drive IC 300, and the film pads P2 of the display device according to the second embodiment of the present invention is as follows. Since it is the same as the display device according to the first embodiment of the present invention, a detailed description thereof will be omitted.

The panel dummy pads DP1 may be adjacent to the panel pads P1 and may be disposed on both sides of the panel pads P1 . The panel dummy pads DP1 are not connected to the data lines. In FIG. 6 , the panel dummy pads DP1 are adjacent to the plurality of panel pads P1 and three are formed on both sides of the panel pads P1 , but the present invention is not limited thereto. A small number of panel dummy pads DP1 may be provided.

The film dummy pads DP2 may be disposed adjacent to the film pads P2 on both sides of the film pads P2 . The film dummy pads DP2 do not receive data voltages from the source drive IC 300 . In FIG. 7 , the film dummy pads DP2 are adjacent to the plurality of film pads P2 and are arranged three on each side of the film pads P2 , but the present invention is not limited thereto. A small number of film dummy pads DP2 may be provided.

Hereinafter, based on FIG. 8 , panel pads P1-1 to P1-n, film pads P2-1 to P2-n, and panel dummy pads P1-1 to P1-n of a display device according to a second exemplary embodiment of the present invention DP1-1 to DP1-3) and the alignment relationship of the film dummy pads DP-1 to DP-3 will be described. The alignment relationship between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n of the display device according to the second embodiment of the present invention is Since it is the same as the display device, a detailed description thereof will be omitted.

The panel dummy pads DP1 may be adjacent to the panel pads P1 and may be symmetrically disposed on both sides of the panel pads P1 .

The first panel dummy pad DP1-1 may be connected to the second panel dummy pad DP1-2 through the first panel line PL1. Also, the first panel dummy pad DP1-1 may be connected to the third panel dummy pad DP1-3 through the second panel line PL2.

The panel dummy pads DP1-1 to DP1-3 may be disposed at an interval different from the interval W1 between the panel pads P1-1 to P1-n. The distance between the first panel dummy pad DP1-1 and the second panel dummy pad DP1-2 is defined as the first panel pad interval PW1, the second panel dummy pad DP1-2 and the third panel dummy pad. The interval between (DP1-3) is the second panel pad interval (PW2), and the interval between the third panel dummy pad (DP1-3) and the first panel pad (P1-1) is the third panel pad interval (PW3). it can be said

The film dummy pads DP2 may be adjacent to the film pads P2 and may be symmetrically disposed on both sides of the film pads P2 .

The film dummy pads DP-1 to DP-3 may be disposed at a spacing different from the spacing W1 between the film pads P2-1 to P2-n. The distance between the first film dummy pad DP-1 and the second film dummy pad DP-2 is the first film pad distance FW1, the second film dummy pad DP-2 and the third film dummy pad The interval between (DP-3) is the second film pad interval (FW2), and the interval between the third film dummy pad (DP-3) and the first film pad (P2-1) is the third film pad interval (FW3). it can be said

The first panel pad spacing PW1 may be smaller than the first film pad spacing FW1. In an alignment error of 2/3 or less of the width W of the panel pads P1-1 to P1-n, the second panel dummy pad DP1-2 and the second film dummy pad DP-2 are not connected. does not When an alignment error of 2/3 or more of the width W of the panel pads P1-1 to P1-n occurs, the second panel dummy pad DP1-2 and the second film dummy pad DP-2 can be connected. Accordingly, it may be determined whether an alignment error of 2/3 or more of the width W of the panel pads P1-1 to P1-n occurs.

The second panel pad spacing PW2 may be smaller than the second film pad spacing FW2. In an alignment error of 1/3 or less of the width W of the panel pads P1-1 to P1-n, the third panel dummy pad DP1-3 and the third film dummy pad DP-3 are not connected. does not When an alignment error of 1/3 or more of the width W of the panel pads P1-1 to P1-n occurs, the third panel dummy pad DP1-3 and the third film dummy pad DP-3 can be connected. Accordingly, it may be determined whether an alignment error of 1/3 or more of the width W of the panel pads P1-1 to P1-n occurs.

In the display device according to the second exemplary embodiment of the present invention, the panel dummy pads DP1-1 to DP1-3 and the film dummy pads DP-1 to DP-3 are symmetrically disposed on both sides. Accordingly, even if an alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n occurs in either direction, it can be detected.

Hereinafter, a signal application relationship between the source drive IC 300 , the panel dummy pads DP1-1 to DP1-3, and the film dummy pads DP-1 to DP-3 will be described with reference to FIG. 9 . do it with

The source drive IC 300 may generate an input signal SIG_IN. The source drive IC 300 may apply the input signal SIG_IN to the first film dummy pad DP-1. The first film dummy pad DP-1 may apply the input signal SIG_IN to the first panel dummy pad DP1-1. Even if an alignment error occurs, the first film dummy pad DP-1 is connected to the first panel dummy pad DP1-1. Accordingly, even if an alignment error occurs, the input signal SIG_IN may always be applied to the first panel dummy pad DP1-1.

The first panel dummy pad DP1-1 receives the input signal SIG_IN through the first and second panel lines PL1 and PL2 to the second and third panel dummy pads DP1-2 and DP1-3. can be authorized with The second panel dummy pad DP1 - 2 may generate the first output signal SIG_OUT1 by using the input signal SIG_IN. The third panel dummy pad DP1-3 may generate the second output signal SIG_OUT2 by using the input signal SIG_IN.

When an alignment error of 2/3 or more of the width W of the panel pads P1-1 to P1-n occurs, the second panel dummy pad DP1-2 and the second film dummy pad DP-2 can be connected. When the second panel dummy pad DP1 - 2 and the second film dummy pad DP - 2 are connected, the second film dummy pad DP - 2 may receive the first output signal SIG_OUT1 . The second film dummy pad DP-2 may output the first alignment error signal MA1 using the first output signal SIG_OUT1. Accordingly, it can be determined whether the alignment error is 2/3 or more of the width W of the panel pads P1-1 to P1-n.

When an alignment error of 1/3 or more of the width W of the panel pads P1-1 to P1-n occurs, the third panel dummy pad DP1-3 and the third film dummy pad DP-3 can be connected. When the third panel dummy pad DP1-3 and the third film dummy pad DP-3 are connected, the third film dummy pad DP-3 may receive the second output signal SIG_OUT2. The third film dummy pad DP-3 may output the second alignment error signal MA2 using the second output signal SIG_OUT2. Accordingly, it may be determined whether the alignment error is 1/3 or more of the width W of the panel pads P1-1 to P1-n.

The source drive IC 300 receives the first and second alignment error signals MA1 and MA2 output from the second and third film dummy pads DP-2 and DP-3.

Hereinafter, the internal structure of the source drive IC 300 of the display device according to the embodiment of the present invention will be described with reference to FIG. 10 .

The source drive IC 300 includes an alignment error information generating unit 310 , a bit converting unit 320 , a voltage generating unit 330 , and an AND gate 340 .

The alignment error information generating unit 310 receives the first and second alignment error signals MA1 and MA2 outputted from the second and third film dummy pads DP-2 and DP-3. The alignment error information generating unit 310 generates the alignment error information MA by using the first and second alignment error signals MA1 and MA2.

The bit conversion unit 320 receives the alignment error information MA generated from the alignment error information generation unit 320 . The bit converter 320 generates a register bit RB by using the alignment error information MA. The register bit RB is digital data obtained by converting the first alignment error information into an upper bit and the second alignment error information into a lower bit.

For example, the register bit RB may consist of 2 bits. When the alignment error is 1/3 or less of the width W of the panel pads P1-1 to P1-n, the value of the register bit RB may be '00'. When the alignment error is 1/3 or more and 2/3 or less of the width W of the panel pads P1-1 to P1-n, the value of the register bit RB may be '01'. When the alignment error is greater than or equal to 2/3 of the width W of the panel pads P1-1 to P1-n, the value of the register bit RB may be '11'.

The voltage generator 330 receives the register bit RB from the bit converter 320 . The voltage generator 330 generates a data enable (DE) signal, which is a signal for determining whether to supply a data voltage to the data line. The voltage generator 330 inverts the register bit RB to generate the inverted register bit RB_INV.

For example, the inversion register bit RB_INV may consist of 2 bits. When the alignment error is 1/3 or less of the width W of the panel pads P1-1 to P1-n, the value of the inversion register bit RB_INV may be '11'. When the alignment error is 1/3 or more and 2/3 or less of the width W of the panel pads P1-1 to P1-n, the value of the inversion register bit RB_INV may be '10'. When the alignment error is greater than or equal to 2/3 of the width W of the panel pads P1-1 to P1-n, the value of the inversion register bit RB_INV may be '00'.

The AND gate 340 receives an inversion register bit RB_INV and a data enable signal DE from the voltage generator 330 . The AND gate 340 outputs '1' only when all of the input signals are '1'. The AND gate 340 generates the data voltages DS only when both the inversion register bit RB_INV and the data enable signal DE are '1'.

When the alignment error is greater than or equal to 2/3 of the width W of the panel pads P1-1 to P1-n, the first and second alignment error signals MA1 and MA2 are applied. In this case, the value of the inversion register bit RB_INV may be '00'. Even when the data enable signal DE is applied, if the value of the inversion register bit RB_INV is '00', the AND gate 340 does not generate the data voltages DS. When the alignment error is equal to or greater than 2/3 of the width W of the panel pads P1-1 to P1-n, the data voltages DS may be blocked. Accordingly, when the alignment error is greater than or equal to 2/3 of the width W of the panel pads P1-1 to P1-n, the data voltages DS may be cut off to reduce power consumption. In addition, when a short circuit or a short circuit occurs due to an alignment error, the data voltages DS may be cut off to protect the circuit.

Hereinafter, a pad alignment inspection method of a display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 11 .

First, the input signal SIG_IN is applied to the first panel dummy pad DP1-1. The source drive IC 300 generates an input signal SIG_IN. The source drive IC 300 applies the generated input signal SIG_IN to the first film dummy pad DP-1. The first panel dummy pad DP1-1 is connected to the first film dummy pad DP-1 to receive the input signal SIG_IN. (S101 in FIG. 8)

Second, the output signals SIG_OUT1 and SIG_OUT_2 are applied to the film dummy pads DP-2 and DP-3. The first panel dummy pad DP1-1 may apply the input signal SIG_IN to the second and third panel dummy pads DP1-2 and DP1-3. The second panel dummy pad DP1 - 2 may generate the first output signal SIG_OUT1 by using the input signal SIG_IN. The third panel dummy pad DP1-3 may generate the second output signal SIG_OUT2 by using the input signal SIG_IN.

When the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 2/3 or more of the width W of the panel pad P1, the second panel dummy The pad DP1 - 2 may be connected to the second film dummy pad DP - 2 . The second panel dummy pad DP1 - 2 may apply the first output signal SIG_OUT1 to the second film dummy pad DP - 2 . Accordingly, it is determined whether the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 2/3 or more of the width W of the panel pad P1. can judge

When the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 1/3 or more of the width W of the panel pad P1, the third panel dummy The pad DP1-3 may be connected to the third film dummy pad DP-3. The third panel dummy pad DP1-3 may apply the second output signal SIG_OUT2 to the third film dummy pad DP-3. Accordingly, it is determined whether the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 1/3 or more of the width W of the panel pad P1. can judge (S102 in FIG. 8)

Third, the alignment error signals MA1 and MA2 are output from the film dummy pads DP-2 and DP-3. The second film dummy pad DP-2 may output the first alignment error signal MA1 using the applied first output signal SIG_OUT1. The third film dummy pad DP-3 may output the second alignment error signal MA2 using the applied second output signal SIG_OUT2. (S103 in FIG. 8)

Fourth, alignment error information MA is generated using the alignment error signals MA1 and MA2. The alignment error information generating unit 310 inside the source drive IC 300 may generate the alignment error information MA using the alignment error signals MA1 and MA2. (S104 in FIG. 8)

Fifth, the alignment error information (MA) is converted into register bit (RB) information. The bit conversion unit 320 in the source drive IC 300 may convert the alignment error information MA into the register bit RB. The register bit RB is digital data obtained by converting the first alignment error information into an upper bit and the second alignment error information into a lower bit.

For example, the register bit RB may consist of 2 bits. When the alignment error is 1/3 or less of the width W of the panel pads P1-1 to P1-n, the value of the register bit RB may be '00'. When the alignment error is 1/3 or more and 2/3 or less of the width W of the panel pads P1-1 to P1-n, the value of the register bit RB may be '01'. When the alignment error is greater than or equal to 2/3 of the width W of the panel pads P1-1 to P1-n, the value of the register bit RB may be '11'. (S105 in FIG. 8)

Sixth, when the register bit RB information is not 0, the data voltages are cut off. When the alignment error is greater than or equal to 2/3 of the width W of the panel pads P1-1 to P1-n, the first and second alignment error signals MA1 and MA2 are applied. In this case, the value of the inversion register bit RB_INV may be '00'. Even when the data enable signal DE is applied, if the value of the inversion register bit RB_INV is '00', the AND gate 340 does not generate data voltages.

When the alignment error is equal to or greater than 2/3 of the width W of the panel pads P1-1 to P1-n, the data voltages DS may be blocked. Accordingly, when the alignment error is equal to or greater than 2/3 of the width W of the panel pads P1-1 to P1-n, the data voltages may be cut off to reduce power consumption. In addition, when a short circuit or a short circuit occurs due to an alignment error, the data voltages DS may be cut off to protect the circuit. (S106 in FIG. 8)

According to an embodiment of the present invention, the panel dummy pads may be disposed at an interval different from the interval between the panel pads, and the film dummy pads may be disposed at a different interval from the interval between the film pads. According to an embodiment of the present invention, when an alignment error of a predetermined ratio or more occurs relative to the width of the panel pads, the panel dummy pad and the film dummy pad may be connected. According to an embodiment of the present invention, it may be determined whether an alignment error of a certain ratio or more has occurred compared to the width of the panel pads by using the alignment error information output from the panel dummy pads. Accordingly, according to an embodiment of the present invention, an alignment error between the pads of the flexible film and the pads of the non-display area may be checked.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: lower substrate
120: upper substrate 200: circuit board
300: source drive IC 310: alignment error information generation unit
320: bit conversion unit 330: voltage generation unit
340: AND gate 400: timing control circuit
500: flexible film 600: anisotropic conductive film
DL1 to DLn: data lines DP1-1 to DP1-3: panel dummy pads
DP-1~DP-3: Film dummy pads P1-1~P1-n: Panel pads
P2-1 to P2-n: film pads PL1, PL2: first and second panel lines

Claims (12)

A plurality of panel pads P1-1 to P1-n connected to the data lines DL1 to DLn, and a plurality of panel dummy pads DP1 adjacent to the panel pads P1-1 to P1-n -1 to DP1-3) including a display panel 100;
a source drive IC 300 for generating data voltages supplied to the data lines DL1 to DLn; and
A plurality of film pads P2-1 to P2-n connected to the panel pads P1-1 to P1-n and connected to the source drive IC 300, and the film pads P2-1 to P2-n) and a flexible film 500 including a plurality of adjacent film dummy pads DP-1 to DP-3,
The panel dummy pads DP1-1 to DP1-3 are disposed at an interval different from the interval W between the panel pads P1-1 to P1-n, and the film dummy pads DP-1 to DP-1 to DP-3) is disposed at an interval different from the interval W between the film pads P2-1 to P2-n,
The source drive IC 300 generates alignment error information MA using the alignment error signals MA1 and MA2 output from the film dummy pads DP-1 to DP-3, and the alignment A display device that converts error information MA into register bit RB information, and blocks data voltages when the register bit RB information is not 0. According to claim 1, wherein the source drive IC (300),
A display device generating an input signal SIG_IN for checking an alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n. 3. The method of claim 2,
The first panel dummy pad DP1-1 is connected to the first film dummy pad DP-1, and the first film dummy pad DP-1 serves as the first panel dummy pad DP1-1. A display device that applies an input signal (SIG_IN). The method of claim 1,
The distance PW1 between the first and second panel dummy pads DP1-1 and DP1-2 is greater than the distance FW1 between the first and second film dummy pads DP-1 and DP-2. small display. 5. The method of claim 4,
The distance PW2 between the second and third panel dummy pads DP1-2 and DP1-3 is greater than the distance FW2 between the second and third film dummy pads DP-2 and DP-3. small display. 6. The method of claim 5,
A width WL of the first panel dummy pad DP1-1 is greater than a width W of the panel pad P1. 7. The method of claim 6,
When the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 2/3 or more of the width W of the panel pad P1,
A second panel dummy pad DP1-2 and a second film dummy pad DP-2 are connected, and the second film dummy pad DP-2 sends a first alignment error signal to the source drive IC 300 . A display device that outputs (MA1). 8. The method of claim 7,
When the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 1/3 or more of the width W of the panel pad P1,
A third panel dummy pad DP1-3 and a third film dummy pad DP-3 are connected, and the third film dummy pad DP-3 sends a second alignment error signal to the source drive IC 300 . A display device that outputs (MA2). The method of claim 8, wherein the source drive IC (300),
A display device that blocks data voltages supplied to the film pads P2-1 to P2-n when the first and second alignment error signals MA1 and MA2 are applied. An alignment error between the panel pads P1-1 to P1-n connected to the data lines DL1 to DLn and the film pads P2-1 to P2-n connected to the source drive IC 300 is checked. applying the input signal SIG_IN to the first panel dummy pad DP1-1;
Film dummy pads in the panel dummy pads DP1-1 to DP1-3 according to an alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n. applying the output signals SIG_OUT1 and SIG_OUT2 to (DP-1 to DP-3);
outputting alignment error signals MA1 and MA2 from the film dummy pads DP-1 to DP-3;
generating alignment error information MA using the alignment error signals MA1 and MA2;
converting the alignment error information (MA) into register bit (RB) information; and
and blocking data voltages when the register bit (RB) information is not 0. The method of claim 10, wherein the applying the output signals (SIG_OUT1, SIG_OUT2) comprises:
When the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 2/3 or more of the width W of the panel pad P1, the first output Pad alignment check method by applying a signal (SIG_OUT1). The method of claim 10, wherein the applying the output signals (SIG_OUT1, SIG_OUT2) comprises:
When the alignment error between the panel pads P1-1 to P1-n and the film pads P2-1 to P2-n is 1/3 or more of the width W of the panel pad P1, the second output Pad alignment check method by applying a signal (SIG_OUT2).

Images