KR20040098869A - Pad structure of liquid crystal display - Google Patents

Abstract

PURPOSE: A pad structure of an LCD(Liquid Crystal Display) is provided to reduce the output aberration of a gate driver IC(Integrated Circuit), thereby obtaining a high quality of display by increasing the contact area of the wires so as to reduce the wire resistance. CONSTITUTION: The first conductive layer(43) is formed on a substrate. The second conductive layer(45) is formed over the first conductive layer. A plurality of contact holes(49) is formed to expose the first conductive layer and the second conductive layer respectively. The first and the second conductive layers are connected by third conductive layer(49) covering the contact holes used in forming a pixel electrode. The contact area of two conductive layers is in proportion to the number of the contact holes. The more the contact hole is, the wider current path of two conductive layers is. Therefore, the current path is capable broadening by increasing the number of the contact holes.

Description

Pad structure of liquid crystal display

The present invention relates to a structure of a liquid crystal display device, and more particularly, to a pad structure of a liquid crystal display device for the design of line on glass (LOG) wiring in a thin film transistor liquid crystal display device.

In the case of the active liquid crystal display device according to the prior art, a lot of efforts have been made to reduce the manufacturing cost by reducing the number of components, simplifying the circuit and the like. There is also a series of efforts, such as no FPC or no gate PCB.

In this regard, the manufacturing method of the liquid crystal display according to the related art will be described with reference to FIG. 1 as follows.

1 is a layout view of a liquid crystal display for explaining the structure of a liquid crystal display according to the prior art.

In the structure of the liquid crystal display according to the related art, as shown in FIG. 1, an active region 25 is provided in an area formed by a horizontal source PCB 11 in a horizontal direction and a gate PCB 13 in a vertical direction. A flexible printed circuit 15 is formed between the source PCB 11 and the gate PCB 13.

In addition, a source TCP (COF) 17 and a gate TCP (COF) 19 are disposed at predetermined intervals in the source PCB 11 and the gate PCB 13, respectively. An array glass 21 is formed between the PCB 13 and the active region 25, and a color filter glass 23 is provided below the active region 25.

As mentioned above, the technique without gate PCB (including no FPC) is a technique for forming respective signals in a panel for driving a gate driver IC. Since it is possible to save parts such as connectors, the manufacturing cost can be lowered.

In addition, FIG. 2 schematically illustrates a liquid crystal display device in which the FPC connection unit 15 is removed and there is no FPC. The array glass 21, the source TCP (COF) 17, and the gate TCP (COF) ( In this case, a LOG (line on glass) line 27 is formed between the 19 and 19 lines.

3 illustrates a liquid crystal display device in which a gate PCB is removed together with an FPC connection unit. In this case, the signals transmitted through the FPC connection unit drive signals for driving the gate driver IC. These gate driver IC driving signals are formed in the panel wiring LOG 27 in the panel rather than the FPC connection portion to allocate driving signal lamps.

Usually, the driving signals are gate low voltage, gate high voltage, STV, CPV, OE, GND, Vdd (driver IC driving voltage), and common voltage.

Here, the common voltage is a signal for transmitting the common voltage to the C / F substrate.

As shown in FIG. 3, the common wiring 30 is formed to transmit a common signal to the transfer formed at the lower left of the panel through the common wiring 30 formed in the panel.

In general, if the LOG wiring is formed in the array glass substrate, it is restricted in space because the LOG wiring should be formed as low as possible in the limited space.

Since the application of the case without FPC and the requirement of the LOG wiring must be made within the range of the screen quality, the most important factor for applying the case without FPC and without gate PCB is the How to use the space to meet the required resistance.

Failure to meet the required resistance can cause problems with the gate driver IC output, which can cause significant problems with the screen quality.

One way to solve this problem is to connect the gate layer and the source / drain layer in parallel, which is more advantageous in terms of resistance than forming a single layer.

However, in order to connect the gate layer and the source / drain layer in a general five-mask structure, a via hole is formed and ITO is formed by covering the exposed portions of the gate and the source / drain layer, and the resistance of the ITO is large and the size of the via hole, the ITO and the gate are formed. And when the problem of the interface characteristics between the source and drain layer occurs, there is a problem in the resistance reduction effect of LOG, which may also damage the screen quality.

FIG. 4 is a plan view taken along line IV-IV of FIG. 3 and illustrates a general structure of a LOG pad part of a liquid crystal display device according to the prior art.

As shown in Fig. 4, the tab bonding area A is formed of the gate single layer 33, and the gate and source / drain bilayers are formed from the pad lead portion (i.e., the pan out portion B). To form.

The technique of forming a double layer using this method is, of course, one of a series of efforts to reduce the LOG resistance.

However, problems may arise in the interfacial characteristics of the via hole portions depending on the interfacial characteristics between the gate and source / drain layers of the ITO metal and the conditions at the time of deposition of the ITO layer. This problem of interfacial properties becomes a factor of increasing resistance.

In addition, as shown in FIG. 5, the film quality of the gate of the via hole 35 and the conductive layer of the source / drain ITO is floated.

Therefore, the present invention has been made to solve the above problems of the prior art, the liquid crystal which can obtain a high-quality screen quality by reducing the LOG resistance to solve the problem of the driver IC output abnormality for the resistance in the gate driver IC It is an object of the present invention to provide a pad structure of a display device.

1 is a layout diagram of a general liquid crystal display device;

2 is a layout diagram of a structure of a liquid crystal display device without an FPC according to the prior art;

3 is a layout view of a structure of a liquid crystal display device to which a gate PCB according to the prior art is not applied;

4 is a plan view taken along the line IV-IV of FIG. 3, illustrating a general structure of a LOG pad portion of a liquid crystal display device according to the prior art;

5 is a photograph showing an abnormal region of a via hole interface characteristic in the structure of a liquid crystal display device according to the prior art;

6 is a layout diagram of a structure of a liquid crystal display device according to an embodiment of the present invention;

7 is a photograph showing an interfacial area of a structure of a liquid crystal display according to an embodiment of the present invention;

8A and 8B show another embodiment of the present invention, FIG. 8A is a plan view of another embodiment of the present invention, and FIG. 8B is a cross-sectional view of another embodiment of the present invention.

[Description of Drawing Reference]

41: transparent substrate 43: gate layer

45: source / drain layer 47: protective film

49: via hole 51: ITO layer

The pad structure of the liquid crystal display device according to the present invention for achieving the above object comprises a gate layer line formed on the pad portion of the transparent insulating substrate;

A source / drain layer line extending to a predetermined portion of the gate layer line;

A via hole formed in a portion of the gate / line layer where the source / drain layer line and the source / drain layer line are not formed, and exposing the source / drain layer line and the gate layer line; And

And an ITO layer line which overlaps the gate layer line and connects the source / drain layer line and the gate layer line through the via hole.

(Example)

Hereinafter, a pad structure of a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

6 is a first embodiment of a pad structure of a liquid crystal display device according to the present invention, and FIG. 7 is a photograph showing an interfacial area of the pad structure of the liquid crystal display device according to one embodiment of the present invention.

In the pad structure of the liquid crystal display according to the present invention, a plurality of via holes 49 are formed in each pad portion A in order to maximize the size and number of via holes between the gate or source / drain 45 and the ITO 51. We propose a structure that minimizes the resistance of the contacts. That is, unlike the conventional liquid crystal display device, the source / drain layer of the source / drain portion is extended to the pad portion as a whole to maximize the via hole size and to reduce the resistance of the contact portion as much as possible.

In general, the contact resistance between ITO and metal is determined by the interfacial properties of ITO as mentioned above. If the interface area between ITO and metal is maximized as much as possible, the contact area is effectively used to reduce the resistance of the contact. Negative resistance can be reduced.

When comparing the interface areas of the contact portions of FIGS. 4 and 6, when the source / drain metal layer 45 is formed to extend to the pad portion A of FIG. 6 rather than the via hole 12 formed in the pad lead portion B, the interface is formed. You can see that the area is much larger.

Here, the interfacial area means an area in contact between the gate 33 and the ITO 31, and also between the S / D 37 and the ITO 31, and refers to a part shown by a thick line in FIG. 7.

If the interface area is small, the area of the substantial contact portion is small, and therefore, the resistance is large.

Typical pad sizes are determined within 50 to 150 μm.

The size of the chip on film (COF) is limited, and if the size is too high, problems with TCP or COF schrinkage may occur, so that one part of the TCP or COF is well aligned during tap bonding. The opposite is because misalignment can occur. This is a temperature dependent variable during tap bonding.

As described above, in the case of the present invention, increasing the contact size or the number thereof can reduce the LOG resistance, so that the problem of the driver IC output abnormality for the resistance in the gate driver IC can be solved, thereby obtaining a good display quality. have.

8A and 8B show another embodiment of the present invention, FIG. 8A is a plan view of another embodiment of the present invention, and FIG. 8B is a cross-sectional view of another embodiment of the present invention.

According to another embodiment of the present invention, as shown in FIG. 8A, when the plurality of via holes 49 are formed on a predetermined area, that is, the source / drain layer 45, the interface area is further increased. You can get

More specifically, as shown in FIG. 8B, a gate layer line 43 is formed on the transparent insulating substrate 41, and a gate insulating film (not shown) is deposited thereon.

In addition, a source / drain layer line 45 is formed on the gate insulating film (not shown) in the gate layer line 43 region. Here, the source / drain layer line 45 extends to the pad region.

A plurality of via holes 49 exposing a portion of the source / drain layer line 45 and a portion of the gate layer line 43 are formed on an area of the source / drain layer line 45.

In addition, an ITO layer line 51 is formed on an upper surface of the entire structure including the plurality of via holes 49. In this case, the ITO layer line 51 covers the entire source / drain layer line 45. In addition, a protective film 47 is formed between the ITO layer line 51 and the side surface of the source / drain layer line 45.

As described above, according to the structure of the liquid crystal display device according to the present invention, as the interface area increases according to the increase in the contact size or the interface area between the gate and the source / drain layer and the ITO, the current path becomes as much as that. As it increases, the desired LOG resistance can be secured, and the output error of the gate driver IC can be reduced, so that a good screen quality can be obtained.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (4)

A gate layer line formed on the pad portion of the transparent insulating substrate; A source / drain layer line extending to a predetermined portion of the gate layer line; A via hole formed in a portion of the gate / line layer where the source / drain layer line and the source / drain layer line are not formed, and exposing the source / drain layer line and the gate layer line; And And an ITO layer line overlapping the source / drain layer line and the gate layer line through the via hole while overlapping the gate layer line. The structure of a liquid crystal display device according to claim 1, wherein a plurality of via holes are formed in the source / drain layer line. 3. The structure of claim 2, wherein the plurality of via holes comprise a pair of via holes exposing source / drain layer lines and gate layer lines thereunder, respectively. The structure of a liquid crystal display device according to claim 1, wherein the ITO layer line is used as a LOG pattern.