CN218995843U - Array substrate, display panel and display device - Google Patents

Abstract

The application is applicable to the field of display devices and provides an array substrate, a display panel and a display device. The array substrate is provided with a peripheral wiring area, and the peripheral wiring area comprises a substrate layer; a first metal layer provided with a first pad pattern; the first insulating layer is arranged on the first metal layer; the second metal layer is arranged on the first insulating layer and is provided with a second bonding pad graph and a vacant part; the second insulating layer is arranged on the second metal layer; a conductive layer provided with a third pad pattern; a first via hole corresponding to the vacant part and a second via hole corresponding to the second bonding pad pattern are arranged in the peripheral wiring area, the first via hole penetrates through the second insulating layer and the first insulating layer, the second via hole penetrates through the second insulating layer, and the cross sections of the first via hole and the second via hole are non-circular; the third pad pattern is connected to the first metal layer through the first via hole, and is connected to the second pad pattern through the second via hole. The array substrate can reduce the on-resistance between the upper layer and the lower layer and improve the display quality.

Description

Array substrate, display panel and display device

Technical Field

The present disclosure relates to the field of display devices, and more particularly, to an array substrate, a display panel, and a display device.

Background

In the manufacturing process of display devices such as liquid crystal displays (Liquid Crystal Display, LCD) and electronic papers (TFT-EPDs), after the display panel is manufactured, an integrated circuit chip (IC), a flexible circuit board (FPC), and the like are required to be bonded to the display panel for subsequent signal input or processing.

At present, since the line width of the line at the IC bonding pad (IC pad) is relatively thin, the contact conduction area of the upper and lower conductive layers is small, the on-resistance is high, and the IC driving capability is easily reduced, so that the display panel has the problem of mura and other display defects caused by insufficient driving capability.

Disclosure of Invention

In view of this, the present application provides an array substrate, a display panel and a display device, which can reduce the on-resistance between the upper layer and the lower layer and improve the display quality.

An embodiment of a first aspect of the present application proposes an array substrate, the array substrate is provided with a peripheral routing area, and the peripheral routing area includes:

a substrate layer;

the first metal layer is arranged on the substrate layer, and a first bonding pad pattern is arranged in the first metal layer;

the first insulating layer is arranged on the first metal layer;

the second metal layer is arranged on the first insulating layer, and a second bonding pad pattern and a vacant part are arranged above the first bonding pad pattern;

the second insulating layer is arranged on the second metal layer;

the conductive layer is arranged on the second insulating layer, and a third bonding pad pattern is arranged in the conductive layer;

the peripheral wiring area is internally provided with a first via hole corresponding to the vacancy part and a second via hole corresponding to the second bonding pad graph, the first via hole penetrates through the second insulating layer and the first insulating layer, the second via hole penetrates through the second insulating layer, and the cross sections of the first via hole and the second via hole are non-circular;

the third bonding pad pattern is connected with the first metal layer through the first via hole, and the third bonding pad pattern is also connected with the second bonding pad pattern through the second via hole.

In some embodiments, the first via and the second via are oval holes, rectangular holes, or diamond holes.

In some embodiments, a plurality of first pad patterns arranged at intervals are arranged in the first metal layer, a plurality of second pad patterns arranged at intervals are arranged in the second metal layer, and a plurality of third pad patterns arranged at intervals are arranged in the conductive layer;

the third pad pattern, the second pad pattern and the third pad pattern are stacked and form a bonding pad.

In some embodiments, two of the first vias and two of the second vias are provided in each of the bond pads.

In some embodiments, the second pad patterns and the empty portions are arranged in parallel above the first pad patterns, and the empty portions are arranged between every two second pad patterns.

In some embodiments, the material of the first metal layer and the second metal layer includes any one of molybdenum, aluminum and alloys thereof, gold, silver and copper.

In some embodiments, the conductive layer is made of ITO.

A second aspect of the present application proposes a display panel comprising:

the array substrate as provided in the first aspect;

the opposite substrate is arranged opposite to the array substrate;

and the display medium is arranged between the array substrate and the opposite substrate.

In some embodiments, the display medium is a liquid crystal or an electronic ink.

A third aspect of the present application provides a display device comprising a display panel as provided in the second aspect.

The array substrate that this embodiment provided is equipped with peripheral wiring district, peripheral wiring district is including the substrate layer, first metal level, first insulating layer, second metal level, second insulating layer and the conducting layer of laminating in proper order setting, be equipped with first pad figure in the first metal level, be equipped with second pad figure in the second metal level, and be equipped with the third pad figure in the conducting layer, first metal level is connected through first via hole to the third pad figure, the second pad figure is still connected through the second via hole to the third pad figure can be electrically connected in first pad figure and second pad figure. Because the cross sections of the first via hole and the second via hole are non-circular, the cross sections of the first via hole and the second via hole are increased compared with the traditional circular via hole, so that the contact area of the third pad graph and the first pad graph and the contact area of the third pad graph and the second pad graph are increased, the conduction performance of the upper layer and the lower layer is improved, and the resistance is reduced. The first pad pattern, the second pad pattern and the third pad pattern can form a binding pad for binding an IC, so that the array substrate can reduce the on-resistance between the upper layer and the lower layer, avoid the problem of poor display caused by mura and the like due to insufficient IC driving capability, and improve the display quality.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a top view of a bond pad provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a bond pad structure according to one embodiment of the present application;

FIG. 4 is a schematic diagram of the bond pad shown in FIG. 3 after fabrication of a second metal layer;

FIG. 5 is a top view of a bond pad provided in accordance with another embodiment of the present application;

fig. 6 is a schematic structural diagram of a binding pad according to another embodiment of the present application.

The meaning of the labels in the figures is:

1. a display panel;

100. an array substrate; 200. an opposite substrate;

101. a peripheral routing area; 102. binding the bonding pad;

10. a substrate layer; 20. a first metal layer; 21. a first pad pattern; 30. a first insulating layer; 40. a second metal layer; 41. a second pad pattern; 42. a hollow portion; 50. a second insulating layer; 60. a conductive layer; 61. a third pad pattern; 70. a first via; 80. and a second via.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings, i.e. embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper," "lower," "left," "right," and the like are used for convenience of description based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements in question must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be construed as limiting of the patent. The terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "a plurality of" is two or more, unless specifically defined otherwise.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, which means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

For the purpose of illustrating the technical solutions described in this application, reference is made to the following description taken in conjunction with the accompanying drawings and examples.

The array substrate is used in a display panel. Referring to fig. 1, the embodiment of the present application provides a display panel 1, which includes an array substrate 100 and an opposite substrate 200 disposed opposite to each other, wherein the opposite substrate 200 may be a Color filter substrate provided with a Color filter (Color filter), but is not limited thereto. The array substrate 100 is provided with a display area and a peripheral wiring area 101, and the peripheral wiring area 101 is arranged outside the display area. A plurality of sub-pixel units are arranged in the display area in an array mode, and a thin film transistor (Thin Film Transistor, TFT) and a pixel electrode which are electrically connected are arranged in each sub-pixel unit.

Referring to fig. 1 to 4, an embodiment of a first aspect of the present application provides an array substrate 100, where the array substrate 100 is provided with a peripheral trace area 101, and the peripheral trace area 101 includes a substrate layer 10, a first metal layer 20, a first insulating layer 30, a second metal layer 40 and a conductive layer 60 stacked in sequence.

The first metal layer 20 is arranged on the substrate layer 10, and a first pad pattern 21 is arranged in the first metal layer 20; the first insulating layer 30 is disposed on the first metal layer 20 and is used for covering the first metal layer 20; the second metal layer 40 is arranged on the first insulating layer 30, the second metal layer 40 is provided with a second pad pattern 41 and a vacant part 42 above the first pad pattern 21, and the vacant part 42 can expose the first insulating layer 30, namely a groove between two adjacent second pad patterns 41; the second insulating layer 50 is disposed on the second metal layer 40, the conductive layer 60 is disposed on the second insulating layer 50, and the third pad pattern 61 is disposed in the conductive layer 60.

The peripheral routing area 101 is provided with a first via hole 70 corresponding to the hollow part 42 and a second via hole 80 corresponding to the second pad pattern 41, the first via hole 70 penetrates through the second insulating layer 50 and the first insulating layer 30, the second via hole 80 penetrates through the second insulating layer 50, and the cross sections of the first via hole 70 and the second via hole 80 are non-circular. The third pad pattern 61 is connected to the first metal layer 20 through the first via hole 70, and the third pad pattern 61 is also connected to the second pad pattern 41 through the second via hole 80, so that the third pad pattern 61 can electrically connect the first pad pattern 21 and the second pad pattern 41.

The cross sections of the first via hole 70 and the second via hole 80 refer to cross sections of the via holes perpendicular to the thickness direction of the array substrate 100, for example, as seen from a top view of the bonding pad shown in fig. 2, the first via hole 70 and the second via hole 80 are elliptical holes, that is, the cross sections of the first via hole 70 and the second via hole 80 are elliptical. Compared to the conventional circular hole, the area of the elliptical hole is larger, so that the above-mentioned array substrate 100 can increase the contact area between the conductive layer 60 and the first metal layer 20 and the contact area between the conductive layer 60 and the second metal layer 40, thereby increasing the conduction performance of the upper and lower layers and reducing the resistance. It is understood that the first via 70 and the second via 80 may be non-circular holes with other shapes, and are not limited to elliptical shapes.

The third pad pattern 61 and the second pad pattern 41 are stacked in correspondence with the first pad pattern 21, and the third pad pattern 61 is electrically connected to both the first pad pattern 21 and the second pad pattern 41, so that the third pad pattern 61, the second pad pattern 41 and the first pad pattern 21 can form the bonding pad 102. When the bonding pad 102 is used to bond an IC, since the resistance of the bonding pad 102 is reduced, the IC driving capability is improved, and the problem of mura due to insufficient driving is improved. The third pad pattern 61 and the second pad pattern 41 are stacked in correspondence with the first pad pattern 21, and are not limited to the formation of the bonding pad 102, and the above-described structure may be used for a wiring such as an electrostatic ring that needs to be turned on up and down.

The array substrate 100 provided in this embodiment is provided with a peripheral routing area 101, where the peripheral routing area 101 includes a substrate layer 10, a first metal layer 20, a first insulating layer 30, a second metal layer 40, a second insulating layer 50 and a conductive layer 60 that are sequentially stacked, a first pad pattern 21 is disposed in the first metal layer 20, a second pad pattern 41 is disposed in the second metal layer 40, and a third pad pattern 61 is disposed in the conductive layer 60, the third pad pattern 61 is connected to the first metal layer 20 through a first via 70, and the third pad pattern 61 is further connected to the second pad pattern 41 through a second via 80, so that the third pad pattern 61 can be electrically connected to the first pad pattern 21 and the second pad pattern 41. Because the cross sections of the first via hole 70 and the second via hole 80 are non-circular, the cross sections of the first via hole 70 and the second via hole 80 are increased compared with the conventional circular via hole, so that the contact area between the third pad pattern 61 and the first pad pattern 21 and the contact area between the third pad pattern 61 and the second pad pattern 41 are increased, the conduction performance of the upper layer and the lower layer is increased, and the resistance is reduced. The first pad pattern 21, the second pad pattern 41 and the third pad pattern 61 may form a bonding pad 102 for bonding ICs, and thus, the array substrate 100 may reduce on-resistance between upper and lower layers, avoid a problem of defective display such as mura due to insufficient driving capability of ICs, and improve display quality.

Referring to fig. 2, 5 and 6, in some embodiments, the first via 70 and the second via 80 are elliptical holes, rectangular holes or diamond holes.

By changing the shapes of the first via hole 70 and the second via hole 80 to be non-circular, the cross-sectional areas of the first via hole 70 and the second via hole 80 can be increased, the conductive areas of the upper and lower layers can be increased, and the contact resistance can be reduced. It is understood that the first via 70 and the second via 80 may also be other shapes, including regular shapes and irregular shapes. The sizes of the first via hole 70 and the second via hole 80 can be designed according to the width variation of the PIN of the IC, and the larger the PIN angle is, the larger the sizes of the first via hole 70 and the second via hole 80 can be correspondingly opened.

Referring to fig. 1 to 4 again, in some embodiments, the first metal layer 20 is provided with a plurality of first pad patterns 21 arranged at intervals, the second metal layer 40 is provided with a plurality of second pad patterns 41 arranged at intervals, and the conductive layer 60 is provided with a plurality of third pad patterns 61 arranged at intervals; the third pad pattern 61, the second pad pattern 41 are disposed corresponding to the third pad pattern 61 and form a bonding pad 102.

Fig. 2 to 4 each show one bonding pad 102, and when the bonding pad 102 is used for bonding ICs, a plurality of bonding pads 102 arranged in sequence need to be provided on the array substrate 100. Therefore, in fabricating the first metal layer 20, it is necessary to pattern the first metal layer 20 to form a plurality of first pad patterns 21 arranged at intervals; similarly, the method is used for the treatment of the heart disease. The second metal layer 40, the conductive layer 60, and the like are also required to be patterned to form a plurality of second and third pad patterns 41 and 61 arranged at intervals. The third pad pattern 61 covers both the first via hole 70 and the second via hole 80.

By adopting the above technical solution, the peripheral routing area 101 of the array substrate 100 may be provided with a plurality of binding pads 102 for binding ICs.

In some embodiments, two first vias 70 and two second vias 80 are provided in each bond pad 102.

Specifically, the first via 70 is used to connect the conductive layer 60 and the first metal layer 20, and the second via 80 is used to connect the conductive layer 60 and the second metal layer 40, so at least one first via 70 and one second via 80 are required to be disposed in each bonding pad 102. Further, in some cases, the first via hole 70 or the second via hole 80 may be formed with a bad etching, or the second via hole Cheng Pianwei may be formed, which may affect the conducting function of the upper and lower layers.

By arranging two first vias 70 and two second vias 80 in each bonding pad 102, the reliability of the process can be improved, and conduction between the upper layer and the lower layer can be ensured.

In some embodiments, the second pad patterns 41 are juxtaposed with the void portions 42 above the first pad patterns 21, and the void portions 42 are provided between every two adjacent second pad patterns 41.

Specifically, after the second metal layer 40 is formed, a metal pattern including the second pad pattern 41 is formed by patterning through exposure, development, and etching. The metal at the void 42 is etched away, exposing the first insulating layer 30. Since the adjacent bonding pads 102 are all independently disposed, it is necessary to separate the second pad patterns 41 of the adjacent bonding pads 102, and the void portion 42 is provided between every two adjacent second pad patterns 41, so that electrical connection of the adjacent second pad patterns 41 can be avoided. Meanwhile, the second metal layer 40 is not disposed at the position of the empty portion 42, so that the first insulating layer 30 and the second insulating layer 50 of the empty portion 42 can be etched simultaneously by exposing, developing and etching to fabricate the first via hole 70.

In some embodiments, the material of the first metal layer 20 and the second metal layer 40 includes any one of molybdenum, aluminum and its alloys, gold, silver, and copper.

It can be understood that the display area of the array substrate 100 is provided with a thin film transistor and a pixel electrode, and optionally, the first metal layer 20 is disposed on the same layer as the gate electrode of the thin film transistor, and the second metal layer 40 is disposed on the same layer as the source electrode and the drain electrode of the thin film transistor; alternatively, the first metal layer 20 is disposed on the same layer as the source and drain electrodes of the thin film transistor, and the second metal layer 40 is disposed on the same layer as the gate electrode of the thin film transistor.

The substrate layer 10 may be made of glass, acrylic, PC, PI, PET, or other flexible materials.

In some embodiments, the conductive layer 60 is Indium Tin Oxide (ITO).

In this way, the conductive layer 60 is disposed on the same layer as the pixel electrode, which facilitates the fabrication of the bonding pad 102. In other embodiments, the conductive layer 60 may also be other conductive metal layers.

In some embodiments, the peripheral trace region 101 further includes a semiconductor layer disposed between the first insulating layer 30 and the second metal layer 40, the semiconductor layer being disposed in common with the semiconductor layer in the thin film transistor.

In the process of manufacturing, the substrate layer 10 is provided first, the first metal layer 20 is manufactured on the surface of the substrate layer 10, and the conductive circuit is formed by developing and etching, and the conductive circuit includes the first pad pattern 21. Next, a first insulating layer 30 is formed on the surface of the first metal layer 20, and the first insulating layer 30 may be made of silicon nitride, but is not limited thereto, and the first insulating layer 30 is patterned by development etching. Then, a second metal layer 40 is formed over the first insulating layer 30, and a conductive line including a second pad pattern 41 is formed by development etching. Then, a second insulating layer 50 is formed over the second metal layer 40, and the second insulating layer 50 may be made of silicon nitride, but is not limited thereto, and then a developing etching is performed to form the first via hole 70 and the second via hole 80. Next, a conductive layer 60 is formed over the second insulating layer 50, and development etching is performed to form a conductive line including a third pad pattern 61.

Referring to fig. 1 to 6, a display panel 1 according to a second aspect of the present disclosure includes an array substrate 100, an opposite substrate 200, and a display medium (not shown) as provided in the first aspect. The opposite substrate 200 is disposed opposite to the array substrate 100, and the display medium is disposed between the array substrate 100 and the opposite substrate 200.

In some embodiments, the display medium is a liquid crystal or electronic ink.

When the display medium is also liquid crystal, the display panel 1 is an LCD panel; when the display medium is electronic ink, the display panel 1 is an electronic paper panel.

Embodiments of the third aspect of the present application propose a display device comprising the display panel 1 provided in the second aspect.

The display panel 1 and the display device provided by the application include the array substrate 100 provided by the first aspect, and can also reduce the on-resistance between the upper layer and the lower layer in the bonding pad 102, thereby improving the display quality.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. An array substrate, characterized in that: the array substrate is provided with a peripheral wiring area, and the peripheral wiring area comprises:

a substrate layer;

the first metal layer is arranged on the substrate layer, and a first bonding pad pattern is arranged in the first metal layer;

the first insulating layer is arranged on the first metal layer;

the second metal layer is arranged on the first insulating layer, and a second bonding pad pattern and a vacant part are arranged above the first bonding pad pattern;

the second insulating layer is arranged on the second metal layer;

the conductive layer is arranged on the second insulating layer, and a third bonding pad pattern is arranged in the conductive layer;

the peripheral wiring area is internally provided with a first via hole corresponding to the vacancy part and a second via hole corresponding to the second bonding pad graph, the first via hole penetrates through the second insulating layer and the first insulating layer, the second via hole penetrates through the second insulating layer, and the cross sections of the first via hole and the second via hole are non-circular;

the third bonding pad pattern is connected with the first metal layer through the first via hole, and the third bonding pad pattern is also connected with the second bonding pad pattern through the second via hole.

2. The array substrate of claim 1, wherein: the first via hole and the second via hole are elliptical holes, rectangular holes or diamond holes.

3. The array substrate of claim 1 or 2, wherein: a plurality of first bonding pad patterns which are arranged at intervals are arranged in the first metal layer, a plurality of second bonding pad patterns which are arranged at intervals are arranged in the second metal layer, and a plurality of third bonding pad patterns which are arranged at intervals are arranged in the conductive layer;

the third pad pattern, the second pad pattern and the third pad pattern are stacked and form a bonding pad.

4. The array substrate of claim 3, wherein: and two first through holes and two second through holes are arranged in each binding bonding pad.

5. The array substrate of claim 3, wherein: the second pad patterns and the empty parts are arranged above the first pad patterns in parallel, and the empty parts are arranged between every two second pad patterns.

6. The array substrate of claim 1, wherein: the materials of the first metal layer and the second metal layer comprise any one of molybdenum, aluminum and alloys thereof, gold, silver and copper.

7. The array substrate of claim 1 or 6, wherein: the conducting layer is made of ITO.

8. A display panel, comprising:

the array substrate of any one of claims 1-7;

the opposite substrate is arranged opposite to the array substrate;

and the display medium is arranged between the array substrate and the opposite substrate.

9. The display panel of claim 8, wherein: the display medium is liquid crystal or electronic ink.

10. A display device comprising the display panel according to claim 8 or 9.

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