JP3202345B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a television or a display.

[0002]

2. Description of the Related Art In current television broadcasting and high-definition test broadcasting, among 525 or 1125 scanning signals in 1/30 second, odd-numbered scanning signals, that is, signals of odd-numbered fields, are sequentially transmitted. Even-numbered scanning signals, that is, signals of even-numbered fields are sequentially transmitted.

For this reason, the simplest driving method for displaying an image such as a television broadcast on a liquid crystal display device is to drive an odd-numbered pixel column from the top of the screen by using the transmitted signal as it is, Next, interlace driving is performed to sequentially drive even-numbered pixel columns. However, when an image is displayed by such a driving method, the image is displayed at a period of 1/30 second, so that the screen may flicker.

Therefore, various methods for displaying an image at a period of 1/60 second using digital signal processing technology or the like have been studied. In this case, a method of sequentially driving the pixel columns is often used as a driving method of the liquid crystal display device. In addition, as an intermediate method between interlace driving and sequential driving, when driving odd-numbered pixel columns by interlace driving, the next even-numbered pixel column is simultaneously driven by the same signal, and even-numbered pixel columns are driven. Sometimes, a method of simultaneously driving the next odd-numbered pixel column with the same signal has been studied.

[0005] When this two-line simultaneous drive is used, although the resolution is inferior to that of the sequential drive, an image is apparently displayed at a period of 1/60 second, so that the flicker of the screen can be suppressed as compared with the interlace drive. it can.

By the way, liquid crystal display devices used for small liquid crystal televisions, projection televisions, projection displays, view finders for video cameras, and the like are required to be smaller, have higher image quality, and have lower prices. . Therefore, a method of integrating a driving circuit on the same substrate as a liquid crystal display device has been devised.

A driving circuit is a so-called signal line driving circuit for supplying an image signal to each liquid crystal pixel via a drain-source of a thin film transistor, and a so-called scanning line for sequentially driving gates of the thin film transistors in a predetermined column. It is a drive circuit. A voltage is applied to the gates of the thin film transistors in a predetermined column by the scanning line driving circuit, the conduction between the drain and the source is conducted, and an image signal supplied from the signal line driving circuit is written to each liquid crystal pixel in a predetermined column. By performing this operation sequentially for each column, a predetermined signal is written to all the liquid crystal pixels, and an image is displayed.

Therefore, when a driving circuit is integrated on the same substrate as a liquid crystal display device, a driving method is determined by the configuration of the driving circuit. That is, usually, the scanning line driving circuit drives the gates of the thin film transistors in each column from the top to the bottom of the display screen or from the bottom to the top. Therefore, a driving method such as interlace driving is determined by the scanning line driving circuit.

For this reason, in a liquid crystal display device in which a drive circuit is integrated, the drive system is determined to be one system, and cannot be used in another device having a different drive system. The production of liquid crystal display devices requires expensive photomasks and many process steps, and it is extremely uneconomical to produce various types of liquid crystal display devices for each device. .

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problem that a driving method is fixed to one in a liquid crystal display device in which a driving circuit is integrated.

According to the present invention, the output of the scanning line driving circuit can be controlled by the control signal supplied to the control line.
Various driving such as interlace driving, two-line simultaneous driving, and sequential driving can be performed by one liquid crystal display device. In particular, according to the present invention, simultaneous driving of two lines can be easily performed, and flicker and the like in display can be sufficiently reduced. Further, according to the present invention, the number of stages of the shift register can be reduced as compared with the number of scanning lines. Thus, even if the number of scanning lines increases, driving can be performed by a shift register that operates at a low speed as in the related art.

[0012]

According to the liquid crystal display device of the present invention, a pixel electrode two-dimensionally arranged on each of n scanning lines via a switch element, and a switch connected to each of the scanning lines are provided. A scanning line driving circuit for controlling on / off of elements on the same substrate, wherein the scanning line driving circuit sequentially transfers a scanning signal;
Terminals are commonly connected to the output of each stage shift register
3m logic circuit groups as a set of three logic circuits,
In the three logic circuits respectively connected to the stage shift register
Are commonly connected to the other terminal of each first logic circuit group
Connected to the first control line and the shift register of each stage, respectively.
Other terminal of each second logic circuit group in the three logic circuits
A second control line commonly connected to the
Each of the third logics in the three logic circuits respectively connected to the
Third control line commonly connected to the other terminal of the circuit group
And a first logic circuit connected to an adjacent shift register
Fourth logic circuit having an input of the output of the third logic circuit as input
And the selection order of the scanning lines is switched by a control signal supplied to the control line.

[0013]

According to the present invention, the output of the scanning line driving circuit integrated on the same substrate as the liquid crystal pixels can be controlled by a control signal.

[0014]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of the liquid crystal display device of the present invention. That is, the liquid crystal display device includes an active matrix type display panel 1, a scanning line driving circuit 2, and a signal line driving circuit 3.

The display panel 1 is formed so that the scanning lines 4a,... And the signal lines 5a,... Intersect, and at the intersections, liquid crystal pixels (pixel electrodes) 7 through thin film transistors (switch elements) 6,. , ... are provided.

That is, one end of each of the liquid crystal pixels 7,... Is grounded, and the other end of each of the liquid crystal pixels 7,.
a, ... are connected. The gates of the thin film transistors 6,... Are connected to the scanning lines 4a,. The liquid crystal pixels 7,... Are arranged in a predetermined number of rows and columns to form a two-dimensional display screen.

Each of the liquid crystal pixels 7 in the vertical direction shares one signal line 5a, and each of the liquid crystal pixels 7 in the horizontal direction shares one scanning line 4a. Are arranged in the same number as the number of pixels in the horizontal direction, and the scanning lines 4a,... Are arranged in the same number as the number of pixels in the vertical direction. A predetermined voltage is applied to the signal lines 5a,... By the signal line driving circuit 3, and the scanning lines 4a,. The liquid crystal pixels 7 of the display panel 1,...
Are integrated on the same substrate 8 on which one of the electrodes of the liquid crystal pixels 7 is formed.

The scanning line driving circuit 2 has a plurality of stages (m stages).
, The logic circuit group 1
1, signal lines 12, 13, 14,... And three first lines,
It is constituted by the second and third control lines 15, 16 and 17. The shift registers 10a,... Are m-stage shift registers that sequentially transfer scanning signals.

The shift registers 10a,... Output delayed shift pulses in accordance with the cycle of the clock pulse. Therefore, the shift pulse is sequentially transferred from the upper shift register 10a,... To the lower shift register 10b,.

The signal line 12 is a clock pulse signal line, and connects the clock pulse input terminal 18 to the clock pulse input terminals of the shift registers 10a,. The signal line 13 is a signal line for a shift pulse as a start pulse, and connects a start pulse input terminal 19 to an input terminal of the shift register 10a. The signal lines 14,...
, and the lower stage shift register 10b,.
Are connected to the output terminals of the shift registers 10a,... And the logic circuit group 11. The first,
The second and third control lines 15, 16, and 17 are signal lines for control signals, respectively, and control signal input terminals 20, 21,.
22.

The logic circuit group 11 includes three AND gates (first, second, and third logic circuits) having one input terminal commonly connected to the outputs of the shift registers 10a,.
3m logic circuit group 34 as a set of 31, 32, 33
, and the OR gates (fourth logic circuit) 35a,... having the outputs of the first AND gate 31 and the third AND gate 33 connected to the adjacent shift registers 10a,. A buffer gate 36 for supplying the output of the OR gates 35a,.
, and buffer gates 37 that supply the outputs of AND gates 32,.
a,...

The first input terminals of the first AND gate groups 31,... In the three AND gates 31, 32, 33 connected to the shift registers 10a,. The control lines 15 are commonly connected. Each of the second AND gate groups 3 in the three AND gates 31, 32, 33 connected to the shift registers 10a,.
The second control line 16 is commonly connected to the other input terminals of 2,. Each stage of shift register 10a,.
AND gates 31, 32, 33 respectively connected to
Are commonly connected to the other input terminals of the third AND gate groups 33,.

The output of the buffer gate 36 corresponding to the logic circuit group 34a is output to the scanning line 4a in the display panel 1, and the buffer gate 3 corresponding to the logic circuit group 34a is output.
7 is output to the scanning line 4b in the display panel 1, and the output of the buffer gate 36 corresponding to the logic circuit group 34b is output to the scanning line 4c in the display panel 1.
The output of the buffer gate 37 corresponding to the logic circuit group 34b is output to the scanning line 4d in the display panel 1, and the output of the buffer gate 36 corresponding to the logic circuit group 34c is
The output from the buffer gate 37 corresponding to the scanning circuit 4e in the display panel 1 and corresponding to the logic circuit group 34c is output to the scanning line 4f in the display panel 1.

The logic circuit group 11 includes the first, second,
The selection order of the scanning lines 4a,... Is switched by a control signal supplied from the third control lines 15, 16, 17.

That is, every other scanning line 4c, 4e... Is sequentially selected from the first scanning line 4a, and then every other scanning line 4d, 4f... Is sequentially selected from the second scanning line 4b. Interlaced driving as a first selection order, and every other scanning line 4a from the first scanning line 4a,
4c,... Are sequentially selected together with adjacent scanning lines 4b, 4d,..., And every other scanning line 4b, 4d,. Two-line simultaneous driving as a second selection order to be selected and sequential scanning driving as a third selection order to sequentially select one scanning line sequentially from the first scanning line 4a are supplied. It is switched by a control signal. next,
The operation in the case of performing the interlace driving in the above-described configuration will be described with reference to the operation timing charts shown in FIGS.

FIG. 2A shows a clock pulse supplied by the signal line 12, FIG. 2B shows a shift register 10a,.
, (C), (d), and (e) are control signals supplied by control lines 15, 16, and 17,
(F), (g), (h), and (i) are scanning lines 4a, 4b,
4C and 4D show four waveforms.

In an odd field, a signal of "1" is supplied to the control line 15 and a control signal of "0" is supplied to the control line 16. In an even field, a signal of "0" is supplied to the control line 15 and a signal of "1" is supplied to the control line 16. You. The signal of “0” is always supplied to the control line 17.

Thus, in the odd field, first, the shift pulse output from the shift register 10a is transmitted to the scanning line 4a via the AND gate 31, the OR gate 35a, and the buffer gate 36a in the logic circuit group 34a.

Next, the shift pulse output from the shift register 10b is applied to the AND gate 3 in the logic circuit group 34b.
1, transmitted to the scanning line 4c via the OR gate 35b and the buffer gate 36b.

Next, the shift pulse output from the shift register 10c is applied to the AND gate 3 in the logic circuit group 34c.
1, transmitted to the scanning line 4e via the OR gate 35c and the buffer gate 36c. Thereafter, the shift register 10
The shift pulses from d,... are sequentially transmitted to the odd-numbered scanning lines 4g, 4i,. As a result, the odd-numbered scanning lines 4a, 4c, 4e,... Are sequentially driven from top to bottom.

In an even field, the shift register 1
The shift pulse output from 0a is transmitted to the scanning line 4b via the AND gate 32 and the buffer gate 37a in the logic circuit group 34a.

Next, the shift pulse output from the shift register 10b is applied to the AND gate 3 in the logic circuit group 34b.
2, transmitted to the scanning line 4d via the buffer gate 37b.

Next, the shift pulse output from the shift register 10c is applied to the AND gate 3 in the logic circuit group 34c.
2, transmitted to the scanning line 4f via the buffer gate 37c. Thereafter, the shift pulses from the shift registers 10d,... Are sequentially transmitted to the even-numbered scanning lines 4h, 4j,. As a result, even-numbered scanning lines 4b, 4d, 4
are sequentially driven from top to bottom.

When a voltage is applied to the gate by the scanning line drive circuit 2 so that the drain and source of the thin film transistors 6 are electrically connected to each other, all of the thin film transistors 6 connected to the scanning lines 4a,. Conduction occurs between the drain and the source, and a predetermined voltage is written to the liquid crystal pixels 7 from each of the signal lines 5a. Odd-numbered scanning lines 4a, 4c,
, And even-numbered scanning lines 4b, 4d, 4f,... Are sequentially interlaced, so that a predetermined voltage is applied to all the liquid crystal pixels 7 in two fields of an odd field and an even field. The image is displayed. Next, the operation in the case where two lines are driven simultaneously in the configuration of FIG. 1 will be described with reference to the operation timing charts shown in FIGS.

FIG. 3A shows a clock pulse supplied by the signal line 12, FIG. 3B shows a shift register 10a,.
, And (c), (d) and (e) are control signals supplied to the control lines 15, 16, and 17, and (f),
(G), (h) and (i) are scanning lines 4a, 4b, 4c, 4
4 shows four waveforms of d.

In an odd field, a signal of "1" is supplied to the control line 15 and a control line 17 is supplied with a signal of "0". In an even field, a signal of "0" is supplied to the control line 15 and a signal of "1" is supplied to the control line 12. You. The control line 16 is always supplied with a signal of “1”.

Thus, in the odd field, first, the shift pulse output from the shift register 10a is transmitted to the scanning line 4a via the AND gate 31, the OR gate 35a, and the buffer gate 36a in the logic circuit group 34a. The signal is also transmitted to the scanning line 4b via the AND gate 32 and the buffer gate 37a in the logic circuit group 34a.

Next, the shift pulse output from the shift register 10b is applied to the AND gate 3 in the logic circuit group 34b.
1, transmitted to the scanning line 4c via the OR gate 35b and the buffer gate 36b, and also transmitted to the scanning line 4d via the AND gate 32 and the buffer gate 37b in the logic circuit group 34b. Thereafter, the shift register 10
are sequentially transmitted to each of the odd-numbered and even-numbered scanning lines 4c and 4d, and the scanning lines 4e, 4f, and so on. As a result, the odd-numbered scanning lines 4a (4
c,...) and the next even-numbered scanning line 4b (4d,
..) Are simultaneously driven sequentially from top to bottom.

At the time of an even field, first, the shift pulse output from the shift register 10a is applied to the logic circuit group 3
The signal is transmitted to the scanning line 4b via an AND gate 32 and a buffer gate 37a in the logic circuit group 34a.
The signal is also transmitted to the scanning line 4c via the AND gate 33, the OR gate 35b, and the buffer gate 36b.

Next, the shift pulse output from the shift register 10b is applied to the AND gate 3 in the logic circuit group 34b.
2. The AND gate 3 in the logic circuit group 34b is transmitted to the scanning line 4d via the buffer gate 37b.
3. The signal is also transmitted to the scanning line 4e via the OR gate 35c and the buffer gate 36c.

Next, the shift pulse output from the shift register 10c is applied to the AND gate 3 in the logic circuit group 34c.
2. The AND gate 3 in the logic circuit group 34c is transmitted to the scanning line 4f through the buffer gate 37c.
3. The signal is also transmitted to the scanning line 4g via the OR gate 35d and the buffer gate 36d. As a result, the even-numbered scanning lines 4b (4d,...) And the next odd-numbered scanning lines 4c
(4e,...) Are simultaneously driven sequentially from top to bottom.

By driving the odd-numbered and even-numbered scanning lines simultaneously by two lines, a predetermined voltage is applied to all the liquid crystal pixels 7,... For each field, and an image is displayed. Next, in the configuration of FIG.
The operation in the case of performing the sequential scanning drive will be described with reference to the operation timing chart shown in (i).

FIG. 4A shows a clock pulse supplied by the signal line 12, FIG. 4B shows a shift register 10a,.
, And (c), (d) and (e) are control signals supplied to the control lines 15, 16, and 17, and (f),
(G), (h) and (i) are scanning lines 4a, 4b, 4c, 4
4 shows four waveforms of d.

The control line 15 is synchronized with the shift pulse,
A clock pulse having the same cycle as the pulse width of the shift pulse is supplied, and a clock pulse having a phase opposite to that of the clock pulse supplied to the control line 15 is supplied to the control line 16. The control line 17 is always supplied with a signal of “0”.

Thus, when the clock pulse supplied to the control line 15 is "1", the shift pulse output from the shift register 10a scans via the AND gate 32 and the buffer gate 37a in the logic circuit group 34a. When the clock pulse transmitted to the line 4a and supplied to the control line 15 is "0", that is, when the clock pulse supplied to the control line 16 is "1", the AND gate 32 in the logic circuit group 34a and the buffer The signal is transmitted to the scanning line 4b via the gate 37a.

Next, when the clock pulse supplied to the control line 15 is "1", the shift pulse output from the shift register 10b is supplied to the AND gate 31, the OR gate 35b and the buffer gate 36b in the logic circuit group 34b. When the clock pulse transmitted to the scanning line 4c and supplied to the control line 15 is "0",
Is “1”, the AND gate 32 and the buffer gate 37 in the logic circuit group 34 b
The signal is transmitted to the scanning line 4d via the line b. Thereafter, the shift pulses from the shift registers 10c,.
e, 4f,... As a result, the scanning lines 4a, 4a
are sequentially driven from top to bottom. Scan line 4
are sequentially driven, a predetermined voltage is applied to all the liquid crystal pixels 7, and an image is displayed. As described above, the driving method of the scanning lines 4,... Is switched by the control signals supplied to the control lines 15, 16, 17. As a result, various driving such as interlace driving, two-line simultaneous driving, and sequential driving can be performed by one liquid crystal display device. The invention is not limited to the embodiment of FIG. FIG. 5 is a circuit diagram showing another embodiment of the present invention.

In the embodiment of FIG. 5, OR gates 40a, 40a are connected between AND gates 32 and buffer gates 37a,... In the logic circuit groups 34a,.
, 40c,... are added, and the input terminal not connected to the AND gate 32 is grounded.

In the case of the embodiment of FIG. 1, the OR gate 35a
When the delay occurs at (35b,...), The timing of the signals applied to the odd-numbered and even-numbered scanning lines is shifted. In the case of the embodiment of FIG. 5, the OR gate 35a (35) is used.
..) and the OR gate 40a (40b,. Other operations are the same as those in the embodiment of FIG. Therefore, according to the embodiment of FIG. 5, the driving method of the scanning lines 4,... Can be switched by the control signals supplied to the control lines 15, 16, 17.

FIG. 6 is a circuit diagram showing another embodiment of the present invention. In the embodiment of FIG. 6, AND gates 31, 32, 33 and OR gates 35a,..., 40a,.
, 43, ..., 44, ..., 45, ..., and "1" is input to an input of the NAND gate 45 that is not connected to the NAND gate 42. Since such a configuration is logically the same, the circuit of FIG. 6 operates similarly to the circuit of FIG.

Therefore, according to the embodiment shown in FIG. 6, the driving method of the scanning lines 4,... Can be switched by the control signals supplied from the control lines 15, 16, 17. Normally, a NAND gate has a smaller number of transistors used therein than an AND gate or an OR gate. Therefore, the embodiment of FIG. 6 can have a smaller number of transistors than the embodiment of FIG. The area can be reduced.

Although the embodiments and modifications of the present invention have been described above, the present invention is not limited to these embodiments and modifications. In short, in a liquid crystal display device in which a driving circuit is integrated, it is sufficient that the driving method of the scanning line driving circuit can be switched, and it is not particularly limited to the circuits of FIGS. 1, 5, and 6. . Further, the signal line driving circuit is not particularly limited, and may be integrated on the same substrate as the liquid crystal pixels, or may be configured externally.

In the embodiments of FIGS. 1, 5 and 6, one end of the liquid crystal pixel 7 is grounded.
The present invention is not limited to this, and may be grounded via a DC voltage source, for example. Further, in order to improve the voltage holding characteristic of the liquid crystal pixel 7, an auxiliary capacitor may be connected in parallel with the liquid crystal pixel 7.

As described above, the driving circuit is integrated on the same substrate as the display panel so that the driving method can be selected, and the driving circuit can be applied to a plurality of devices having different driving methods without changing the design.

[0054]

As described above in detail, according to the present invention, it is possible to provide a liquid crystal display device capable of performing various kinds of driving such as interlace driving, two-line simultaneous driving, and sequential driving with one liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart for explaining an operation when performing interlace driving in the liquid crystal display device of FIG. 1;

FIG. 3 is an operation timing chart for explaining an operation when two lines are simultaneously driven in the liquid crystal display device of FIG. 1;

FIG. 4 is an operation timing chart for explaining an operation in the case where sequential scanning drive is performed in the liquid crystal display device of FIG. 1;

FIG. 5 is a circuit diagram showing a schematic configuration of a liquid crystal display device according to another embodiment of the present invention.

FIG. 6 is a circuit diagram showing a schematic configuration of a liquid crystal display device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... Scan line drive circuit, 3 ... Signal line drive circuit, 4a ...-Scan line, 5a ... Signal line, 6 ... Thin film transistor (switch element), 7 ... Liquid crystal pixel (pixel electrode) ), 8: substrate, 10a, ... shift register, 1
1: Logic circuit group, 12, 13, 14 ... signal line, 15, 1
6, 17 ... first, second, third control lines, 31, 32, 3,
3. AND gate (first, second, third logic circuit), 3
4a, 34b,..., Logic circuit group, 35a,... OR gate (fourth logic circuit), 36a,.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-115231 (JP, A) JP-A-3-85529 (JP, A) JP-A-2-42420 (JP, A) JP-A-2- 3008 (JP, A) JP-A-2-253232 (JP, A) JP-A-64-82097 (JP, A) JP-A-1-218183 (JP, A) JP-A-2-240687 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/133 505 G09G 3/36

Claims (2)

(57) [Claims] 1. A pixel electrode arranged two-dimensionally on each of n scanning lines via a switching element, and a scanning line driving circuit for controlling on / off of a switching element connected to each of the scanning lines. Wherein the scanning line driving circuit is connected to an m-stage shift register for sequentially transferring scanning signals, and a terminal is commonly connected to an output of each stage of the shift register.
3m logic circuit groups each including three logic circuits as a set, and three logic circuits respectively connected to the shift register of each stage
Connected to the other terminal of each first logic circuit group
A first control line and three logic circuits respectively connected to the shift registers of each stage
Connected to the other terminal of each second logic circuit group
Second control line and three logic circuits respectively connected to the shift registers of each stage
Connected to the other terminal of each third logic circuit group
A third control line, a first logic circuit connected to an adjacent shift register, and a third control line .
A liquid crystal display device comprising: a third logic circuit having a third logic circuit and an output as an input; and a control signal supplied to the control line, the selection order of the scanning lines is switched. 2. A first selection order in which every other scanning line is sequentially selected from the first scanning line, and then every other scanning line is sequentially selected from the second scanning line. After selecting every other scanning line from the first scanning line together with adjacent scanning lines, and sequentially selecting every other scanning line from the second scanning line together with adjacent scanning lines. A second selection order and a third selection order for sequentially selecting from the first scanning line to the n-th scanning line are switched by a control signal supplied to a control line. The liquid crystal display device according to claim 1.