JPH04297190A - Liquid crystal driving device - Google Patents

Abstract

PURPOSE:To satisfactorily display the EDTV broadcast, the high vision broadcast, etc., even when an X driver which is manufactured generally at present and whose frequency characteristic is comparatively narrow is used. CONSTITUTION:In the upper and the lower parts of a liquid crystal display part, a first and a second data line driving devices 141a, 142a are provided, respectively. From each data line driving device 141a, 142a, two pieces each of data lines 28 are connected alternately to each picture element electrode 26 train in the vertical direction of the liquid crystal display part. In each picture element electrode 26, a first and a second switching elements 25 are provided, so that when one data line is turned on, two adjacent picture element electrodes 26 are tuned on, and also, to each one piece of data line of two pieces each of data lines 28 of the first and the second data line driving devices 141a, 142a, a picture element signal is supplied at every field.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive device having a large number of pixels for displaying high-definition broadcasting and the like.

0003

2. Description of the Related Art Recently, many displays using liquid crystal panels have been seen. Examples include pocket LCD televisions, displays for laptop computers and word processors, and LCD projectors. Liquid crystal displays are also attracting a lot of attention as high-definition displays.

[0004] Many liquid crystal panels for displaying moving images such as television broadcasts employ an active matrix type in which each pixel has a switching element such as a thin film transistor. Conventionally, the number of pixels in the vertical direction of this active matrix type liquid crystal panel was about half of the effective number of scanning lines in the television broadcasting system, for example, about 220 to 240 pixels in the case of the NTSC system, due to problems in manufacturing the liquid crystal panel. but,
Improvements in manufacturing technology have made it possible to mass-produce liquid crystal panels with approximately the number of effective scanning lines of television broadcasting systems, for example, approximately 440 to 480 pixels in the case of NTSC systems. Additionally, liquid crystal panels capable of displaying high-definition broadcasts have also been developed.

[0005] In the television broadcasting system, the conventional NTS
EDTV broadcasting is located between C broadcasting and future high-definition broadcasting. In this EDTV broadcast, the video signal band is the same as conventional NTSC broadcast, but the aspect ratio is 16:9 and display is performed using double-speed line sequential scanning instead of interlace.

FIG. 10 shows a configuration diagram of the double-speed line sequential scanning method of EDTV. In addition, Figure 11(a) and (b)
The video signal waveform at 0 is shown.

In FIG. 10, the liquid crystal panel 16 is of an active matrix type using thin film transistors (hereinafter referred to as TFTs). From input terminal 11 to Figure 11 (
When a video signal as shown in a) is input, the double speed conversion circuit 12 outputs the signal at double speed as shown in FIG. 11(b). After the polarity inversion circuit 13 converts the signal into a signal whose polarity is inverted according to the field period period, frame period period, horizontal scanning period period, etc., the signal is input to the X driver 14 . This is to extend the life of the liquid crystal panel display section 17 by alternately driving with a signal whose polarity is inverted at a predetermined period. The X driver 14 samples and holds the input signal and outputs the signal to the data line of the TFT arranged in each pixel of the liquid crystal panel display section 17, and the Y driver 15 samples and holds the input signal. It controls the line.

The signal writing operation to the liquid crystal panel will be explained using FIG. In the figure, 25 represents a TFT, and 26 represents a pixel electrode. Further, the number of data lines 28 connected to the X driver, which normally number about 100 to 200, is omitted to two for convenience of explanation. The X driver 14 includes a shift register 21, a level converter 22, a sample hold circuit 23, and a buffer drive 24. When the shift register 21 is supplied with a start pulse STH indicating the start of the horizontal display period, the shift register 21 turns on sequentially from the first bit in synchronization with the clock CLK and outputs an on-pulse. When using two X drivers,
When the on-pulse shifts to the final bit, a carry-out occurs and the ST of the shift register of the next stage X driver is output.
It becomes H. Since the clock CLK is a double-speed scan, the timing is such that on-pulses of the shift register are output for twice the number of pixels in the horizontal direction of the liquid crystal panel during one horizontal effective scanning period. For example, if the number of pixels in the vertical direction is 4
80 pixels, 32M when the number of horizontal pixels is 850 pixels
This becomes the Hz clock CLK.

[0009] The level converter 22 amplifies the on-pulse of the shift register 21 and transfers it to the sample and hold circuit 23.
Output to. The sample and hold circuit 23 samples and holds the input video signal Sin at the timing of the on-pulse from the level converter 22. In this way, the sample and hold circuit 23 holds the signals of a plurality of pixels controlled by one gate line of the liquid crystal module. The output from the sample and hold circuit 23 is supplied to a buffer drive 24, and the buffer drive 24 amplifies the output of the sample and hold circuit 24 when the output instruction signal OE is on, and outputs it to the data line 28 of the TFT of the liquid crystal panel. . As shown in FIG. 11, the output instruction signal OE is turned on during the retrace period (hereinafter referred to as a blanking period) of the video signal Sin.

The Y driver 15 controls the signal output from the X driver 14 to the data line 28 so that it is supplied only to the TFT connected to one gate line. This will be explained with reference to FIG. In FIG. 11, the signal Y1 represents the signal on the gate line Y1 connected to the Y driver in FIG. 12, and the signal Y2 represents the signal on the gate line Y2. Since the gate line Y1 is the first gate line to turn on, the Y driver sends the gate line Y1 at the same time as the first OE on signal in the field period.
An on signal is output at , and the on state is maintained for approximately 1/2 horizontal scanning period. At this time, all gate lines other than gate line Y1 are off. When the gate line Y1 is turned off, the gate line Y2 is turned on instead. Similarly, when the gate line Y2 is turned off, the next gate line is turned on, and the gate lines are turned on sequentially from top to bottom. As a result, signals can be written to all pixels of the liquid crystal panel in one field period.

In this manner, the Y driver 15 sequentially outputs ON signals to each gate line for approximately 1/2 horizontal scanning period in accordance with the timing of the output from the X driver 14.
The TFT can supply a signal from the X driver 14 to the liquid crystal pixel when the gate line is on.

The double speed conversion circuit 12 of the EDTV shown in FIG.
(November 1989 issue), so I will omit it here.

Considering the frequency characteristics of the X driver 14, since the double speed signal has twice the frequency band of the standard signal, the frequency characteristics of the X driver 14 also need to have double the frequency characteristics to correspond to the double speed signal. In the case of a liquid crystal panel with 480 pixels in the vertical direction and 850 pixels in the horizontal direction, the frequency characteristic becomes very high at about 32 MHz.

Therefore, in a liquid crystal panel, normally, as shown in FIG. by X Driver 1
By halving the frequency band of the video signal input to 41 and 142, the frequency characteristic of the X driver is reduced to approximately 16 MHz, which is half of that in the case of FIG. Two-phase expansion circuit 41
Regarding, Japanese Patent Application Laid-Open No. 2-82882 (Patent Application No. 1983)
235333), the details are omitted here.

[0015] Furthermore, in the case of standard display for high-definition broadcasting, assuming that a liquid crystal panel with 960 pixels in the vertical direction and 1700 pixels in the horizontal direction is used, the frequency characteristic of the X driver is approximately 69 MHz. Even if a two-phase expansion circuit is used, the cost is about 34.
It becomes 5MHz.

[0016] By the way, the X driver is usually made of a medium-voltage CMOS integrated circuit, and the frequency characteristics of the X drivers that can be easily manufactured at present are at most 10 MHz or less, and the was difficult to manufacture.

[0017]

[Problem to be solved by the invention] As shown in the conventional example,
The LCD panel that displays EDTV broadcasts has a frequency of approximately 16MHz.
An X driver with frequency characteristics of approximately 34.5 MHz is required for high-definition broadcasting. As mentioned above, such an X driver is generally difficult to manufacture.

An object of the present invention is to provide a liquid crystal drive device that can effectively display EDTV broadcasts, high-definition broadcasts, etc. by effectively utilizing a conventional X driver with narrow frequency characteristics.

[Configuration of the invention]

[0020]

[Means for Solving the Problems] A liquid crystal driving device of the present invention includes a plurality of data lines arranged in a horizontal scanning direction, a plurality of scanning lines orthogonal to the plurality of data lines, and a scanning signal to the plurality of scanning lines. and a plurality of pixel electrodes arranged in a grid pattern corresponding to the intersections of the plurality of data lines and the plurality of scanning lines, one data line sandwiching each pixel electrode; A first switching element is connected between one scanning line sandwiching the pixel electrode, and a second switching element is connected between the other data line sandwiching the pixel electrode and the other scanning line sandwiching the pixel electrode. a liquid crystal display unit to which a switching element is connected and which supplies a pixel signal to each pixel electrode by turning on the first or second switching element during a period when a scanning signal is supplied to each scanning line; It supplies pixel signals to the lines, and includes first and second data line driving devices, and the (4m+1)th and (4m+)th lines lined up in the horizontal scanning direction.
2)・(4m+3)・(4m+4)th data line (m
=0,1,2,3,...), the (4m+1)th and (
The 4m+2) data line is connected to the first data line driver, and the (4m+3) and (4m+4) data line is connected to the second data line driver.
data line driving devices, and the first and second data line driving devices have n field periods (n=1, 3, 5, . . .
) supplies pixel signals to the (4m+1)th and (4m+3)th data lines, and supplies pixel signals to the (4m+2) and (4m+4)th data lines during the (n+1) field period. The device is characterized in that it is equipped with a device.

[0021]

[Operation] In the liquid crystal driving device shown above, when one data line is turned on, two adjacent pixel electrodes are turned on, so the number of pixels in the horizontal direction during display is halved, and therefore the frequency characteristics of the data line driving device are halved. good. Furthermore, since the horizontal resolution will be halved if the current state is maintained, a significant drop in resolution can be suppressed by shifting pixels in the horizontal direction on a field-by-field basis.

[0022]

[Embodiment] An embodiment will be described below with reference to the drawings. Figure 1
FIG. 1 is a block diagram showing an embodiment of a liquid crystal driving device according to the present invention.

In FIG. 1, the configuration of this embodiment is as shown in FIG.
The two-phase expansion circuit 41 in the conventional example is replaced with the four-phase expansion circuit 42.
This is the configuration replaced with . The configurations of the liquid crystal display section 17a and the X drivers 141a and 142a are different from those shown in FIG. 12, and are as shown in FIG. Figures 1 and 2
The same parts as in the conventional example (FIGS. 12 and 13) are given the same reference numerals.

FIG. 2 shows the configuration of the liquid crystal panel in FIG.
FIG. 3 shows the configuration of the switching circuit 51 in FIG. 2.

In FIG. 2, 2
The data lines 28 connected to the two X drivers 141a and 142a are not alternately wired one by one as in the conventional case, but are alternately wired two by two, and are connected to the pixel electrodes 26 on both sides sandwiching each data line. One TFT 25 is arranged. A data line 28 is connected to the source electrode of the TFT 25, a pixel electrode 26 is connected to the drain electrode, and a gate line of the Y driver 15 is connected to the gate electrode.

The X driver in FIG. 2 and the conventional X in FIG. 12
The difference between the drivers is that a switching circuit 51 is added. As shown in FIG. 3, this switching circuit 51 connects to the left side (A) of the data line when the switch pulse SWH is at a high level, and connects to the right side (B) of the data line when it is at a low level. It switches to
The switch pulse SWH is assumed to be a signal that switches at one vertical scanning period (one field) cycle, as shown in FIG.

Next, in FIG. 2, the X drivers 141a, 14
The operation of 2a will be explained. Although FIG. 2 shows only four data lines connected to the X driver and four gate lines connected to the Y driver for convenience of explanation, in reality, the number of lines corresponds to the number of pixels.

The input video signal Sin is input to the level converter 2.
The signal is sampled at the timing of the second on-pulse and held in the sample hold circuit 23. The on-pulse of the level converter 22 is an amplified on-pulse of the shift register 21, as in the conventional example, and this on-pulse is output at the timing of the clock CLK. The signal held in the sample hold circuit 23 is supplied to the buffer drive 24 as in the conventional example, and is output to the switching circuit 51 when the output instruction signal OE is turned on. As in the conventional example, the OE receives the video signal (
It is turned on (assuming that the high level is in the on state) during the blanking period of b). In synchronization with the switch pulse SWH, the switching circuit 51 connects to the data line (A) in, for example, odd fields, and connects to the data line (B) in even fields.
and outputs the output from the buffer drive 24 to the respective data lines (A) and (B). Further, the Y driver 15 sequentially turns on the gate lines at a timing that matches the OE of the X driver so that signals can be written to all pixels in one field as in the conventional example.

FIG. 5 shows a state in which signals are written to pixels in an odd field (a) and a state in which signals are written to a pixel in an even field (b). The shaded areas represent pixels to which signals are written from the X driver 141a placed at the top of the liquid crystal panel, and the blank areas represent pixels to which signals are written from the X driver 142a placed at the bottom of the liquid crystal panel.

In this embodiment, signals are written to two adjacent pixels in the horizontal direction, so in the case of an odd field, signals can be written in two vertical lines as shown in the shaded area in FIG. 5 using only data line A. Can be done. Furthermore, in an even field, a signal is written using the data line B on two lines that are shifted by one pixel from the vertical line written in an odd field. By shifting the lines to be written in odd and even fields by one pixel in this manner, the horizontal resolution can be increased by about 1.5 times compared to writing in the same line.

FIG. 6 is a block diagram showing the four-phase expansion circuit 42 in FIG. 1. In FIG. 6, a video signal Sin is input to an A/D conversion circuit 61 operating with a clock CLP, and its A/D conversion output is simultaneously input to D/A conversion circuits 62 and 63. On the other hand, the clock CLP is applied to the frequency divider 6
After being frequency-divided by 2 by 4, the frequency is further divided by 2 by a frequency divider 66 and inputted to one input terminal of a switch 67. Further, the output of the frequency divider 64 is inverted by the inverter 70, and then the output is inverted by the frequency divider 64.
5 and enters the other input terminal of the switch 67. The switch 67 is switched by a switch pulse SWH, and its output becomes the clock of the D/A conversion circuit 62 via the inverter 71, and the output of the switch 67 becomes the clock of the D/A conversion circuit 63.

FIG. 7 shows signals at each part in FIG. 6, where (a) is the clock CK of the frequency divider 66, (b) is the clock CK of the frequency divider 65, (c) is the output signal of the frequency divider 66, (d) is the output signal of the frequency divider 65. The input video signal Sin is first converted into a digital signal by the A/D conversion circuit 61. The clock CK at this time is indicated by CLP in FIG. The video signal converted into a digital signal is sent to D/A conversion circuits 62, 6.
3, respectively. The clock CK of the D/A conversion circuits 62 and 63 is a signal obtained by dividing CLP by 2 degrees, for example, CL
Figure 7(c) of 8MHz with P as a 32MHz signal
, (d), the clock CK of the D/A conversion circuit 62 is a signal obtained by inverting the clock CK of the D/A conversion circuit 63. (For detailed operation, see Japanese Patent Application Laid-Open No. 2-8288.
See Publication No. 2 (Japanese Patent Application No. 63-235333). ) In the present invention, the clock CK of the D/A conversion circuits 62 and 63 is switched by the switch 67 as shown in FIGS. 7(c) and 7(d). This switch 67 is switched by the switch pulse SWH of the switch 51 shown in FIGS. 2, 3, and 4. For example, the switch 67
When the switch 51 is connected to the data line A,
When the switch 51 is connected to the frequency divider 66 that outputs the signal shown in FIG. 7(c) and the data line B is connected, the signal shown in FIG.
) is connected to a frequency divider 65 that outputs a signal. Video signal Si
n is D/A converted with a clock of 1/4 period of the clock to be A/D converted, so the signal frequency band is 1/4
The output 68 of the D/A conversion circuit 62 is input to the X driver 141a, and the output 69 of the D/A conversion circuit 63 is input to the X driver 142a.

The frequency characteristics of the X driver of this example are as follows:
With the 4-phase expansion circuit, the frequency band of the video signal is half that of the conventional 2-phase expansion circuit, and the data lines used by the 1X driver in one field are 1/4 of the number of pixels in the horizontal direction, so the number of pixels in the vertical direction is 480. In the case of a liquid crystal panel with 850 pixels in the horizontal direction, the conventional frequency was 16 MHz, but it can be reduced to 8 MHz, which is half that.

Next, considering the case of high-definition broadcasting, the number of pixels in the vertical direction is 960, so in the above embodiment, the Y driver was turned on one gate line at a time in double-speed display, but in the standard display of high-definition broadcasting, As shown in FIG. 8, gate lines Y1 and Y2 are turned on simultaneously. This is because when receiving an interlaced signal, it is difficult for a liquid crystal panel to display an interlaced image due to the retention performance of the liquid crystal material. Signals Y1 and Y2 in FIG. 8 are signals of gate lines Y1 and Y2 connected to the Y driver 15 in FIG. 2. Gate line Y
1 and Y2 turn on at the same time as the output instruction signal OE, remain on for one horizontal scanning period, and turn off at the next OE. Next Y
1 and Y2 are turned off, and Y3 and Y4 are turned on for one horizontal scanning period. This operation is performed sequentially to write signals to all pixels in one field.

As described above, if signals are repeatedly written to pixels by turning on two gate lines at the same time in one horizontal scanning period, the display image will be about 480 lines if the liquid crystal module has 960 pixels in the vertical direction. This results in a vertical resolution of . Therefore, in the present invention, in order to increase the resolution, as shown in FIG. 9, the gate lines are shifted by one gate line and turned on in odd and even fields. This means that in odd-numbered fields, gate lines Y1 and Y2 are turned on at the same time, and then gate lines Y3 and Y4 are turned on at the same time, whereas in even-numbered fields, gate lines Y2 and Y3 are turned on at the same time, and then gate lines Y4 and Y4 are turned on at the same time. Just set the Y driver so that Y5 is turned on at the same time. As mentioned above, by shifting the gate lines that are turned on in odd and even fields, the display becomes close to the interlaced scanning display of a CRT, and the vertical resolution is approximately 70.
Improved to 0.

At this time, since the X driver performs the same operation as in the embodiment shown in FIG. 2, the frequency characteristic may be 17.25 MHz, which is half that of the conventional example.

[0037]

[Effects of the Invention] According to the present invention, the frequency characteristic of the X driver is only half that of the conventional one, and in the case of a liquid crystal panel with 480 pixels in the vertical direction and 850 pixels in the horizontal direction, the frequency characteristic of the X driver can be reduced to 16 MHz.
The frequency response has been halved to 8MHz, making it possible to use the currently common medium-voltage CMOS integrated circuit X driver. Also, like high-definition broadcasting, 960 pixels in the vertical direction,
When using a liquid crystal panel with 170 pixels in the horizontal direction, the frequency response of approximately 34.5 MHz is halved to 17.25 MHz.
That would be enough.

Furthermore, since two TFTs are provided in one pixel electrode, if one TFT fails, even if one field signal cannot be displayed, signals can be written in the remaining TFT in the next field, making pixel defects less noticeable. You can do without it.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a liquid crystal driving device according to the present invention.

FIG. 2 is a configuration diagram showing one embodiment of the liquid crystal panel in FIG. 1;

FIG. 3 is a configuration diagram showing the switching circuit of FIG. 2;

FIG. 4 is a timing diagram showing switch pulses of a switching circuit.

FIG. 5 is an explanatory diagram showing a method of writing pixel signals to a liquid crystal display section.

FIG. 6 is a configuration diagram showing the four-phase expansion circuit of FIG. 1;

FIG. 7 is a clock timing diagram of a four-phase expansion circuit.

FIG. 8 is a timing diagram showing a scanning signal when the present invention is applied to high-definition broadcasting.

FIG. 9 is an explanatory diagram showing an example of a horizontal scanning method when the present invention is applied to high-definition broadcasting.

FIG. 10 is a configuration diagram showing a conventional liquid crystal driving device.

FIG. 11 is a timing chart of signals in the double-speed line sequential scanning method.

FIG. 12 is a configuration diagram of a conventional liquid crystal panel.

FIG. 13 is a configuration diagram showing another conventional example of a liquid crystal driving device.

[Explanation of symbols]

15...Y driver (scanning line driving device) 17a...Liquid crystal display section 25...Thin film transistor (TFT) 26...Pixel electrode 28...Data line 51...Data line switching circuit

Claims (1)

[Claims] 1. A plurality of data lines arranged in a horizontal scanning direction, a plurality of scanning lines perpendicular to the plurality of data lines, a scanning line driving device for supplying scanning signals to the plurality of scanning lines, and a scanning line driving device for supplying scanning signals to the plurality of scanning lines; A plurality of pixel electrodes are arranged in a grid pattern corresponding to the intersections of the data line and the plurality of scanning lines, and between one data line sandwiching each pixel electrode and one scanning line sandwiching the pixel electrode. A first switching element is connected to the pixel electrode, and a second switching element is connected between the other data line sandwiching the pixel electrode and the other scanning line sandwiching the pixel electrode, and a scanning signal is applied to each scanning line. a liquid crystal display section that turns on the first or second switching element to supply a pixel signal to each pixel electrode during a period when the pixel signal is supplied; and a liquid crystal display section that supplies the pixel signal to the plurality of data lines, Equipped with first and second data line driving devices, the (4m+1)th, (4m+2)th, (4m+3)th, and (4m+4)th data lines (m=0, 1, 2, 3) arranged in the horizontal scanning direction are provided. ,...), the (4m+1
) and the (4m+2)th data line are connected to the first data line driving device, the (4m+3) and (4m+4)th data lines are connected to the second data line driving device, and the first and the 2
The data line driving device has n field periods (n=1, 3
, 5, ...) supplies pixel signals to the (4m+1)-th and (4m+3)-th data lines, and supplies pixel signals to the (4m+2)-th and (4m+4)-th data lines during the (n+1) field period. 1. A liquid crystal driving device comprising a data line driving device.