KR19980067902A - Display device and driving method thereof - Google Patents

Abstract

In the display device according to the present invention, scanning signals are simultaneously supplied to two gate lines to double the scanning signal supply time, and to double the period of the image data output from the frame memory than the period of the image data input to the frame memory. Increasingly, by doubling the image data period and doubling the time for which the image data voltage is charged in the pixel, good image quality can be obtained.

Description

Display device and driving method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a driving method, and more particularly, to a matrix display device and a driving method thereof capable of applying sufficient data to a pixel.

Substituting the heavy, high power consumption of the cathode ray tube (CRT), which is mainly used as a display device such as a computer monitor, liquid crystal display (LCD), plasma display There are various flat panel displays (FPD) such as plasma display panel (PDP), electroluminescince (EL), and field emission display (FED). The pixels of the flat panel display are arranged in a matrix.

Liquid crystal displays are typical of portable matrix type flat panel displays, and among them, active matrix liquid crystal displays using thin film transistors as switching elements are mainly used.

Next, a conventional active matrix liquid crystal display and a driving circuit thereof will be described in detail with reference to FIG. 1.

In the liquid crystal substrate 1, a plurality of pixels (not shown) that perform a display operation are formed in a matrix form. In this case, the matrix of pixels is defined as a pixel matrix, and the pixel row and the pixel column are each a row of the pixel matrix. And heat.

The pixels are driven by signals applied via the wiring, the wiring is a scanning signal line or the gate lines for transmitting a scan signal to the pixel _{(G 1, G 2, ......} , G m-1, G m, G m + 1 ,..., G _M ), an image signal line or a data line D ₁ , D ₂ ,..., D _2N which transfers an image signal or image data to a pixel, each pixel having an angry gate line and one data. It is connected to the line. The number of gate lines G ₁ , G ₂ , ……, G _m-1 , G _m , G _{m + 1} , ……, G _M is equal to the number of pixel rows, and the data lines D ₁ , D ₂ ,..., D _2N ) is equal to the number of pixel columns.

The gate lines G ₁ , G ₂ ,..., G _m-1 , G _m , G _{m + 1} ,..., G _{M are} connected to the liquid crystal substrate 1 in a horizontal manner with the audio gate driver 20. The data lines D ₁ , D ₂ ,..., D _2N are formed vertically and connected to the source driving units 12 and 14. Source driving unit (12, 14) are located respectively on the bottom and top of the substrate (1), data lines _(first D, D _2, ......, D _2N), the odd-numbered data lines (D _1, of the D _3, D ₅ ,..., D _{2N-1 are} connected to the lower source driver 14, and even-numbered data lines D ₂ , D ₄ , D ₆ ,..., D _2N are connected to the upper source driver 12. have.

The upper source driver 12 and the lower source driver 14 are connected to the controller 100, respectively.

In the conventional liquid crystal display, a method of applying an image signal or image data to each pixel is as follows.

When image data input from the outside is input to the controller 100, the controller 100 outputs image data of odd-numbered pixels to the lower source driver 14 and image data of even-numbered pixels to the upper source driver 12. do.

When the start signal (Start) is applied to the gate driver 20, the gate driver 20 has the first gate line is supplied to the scanning signal (G _1), and connected to the first gate line (G _1), accordingly, the pixels of which The switching element is turned on. At this time, the upper source driver 12 and the lower source driver 14 apply the image data corresponding to the first pixel row to the first pixel row through the data lines D ₁ , D ₂ ,..., D _2N .

Subsequently, when all data is applied to the first pixel row, the scan signal applied to the first gate line G ₁ is cut off and the scan signal is applied to the second gate line G ₂ . Then, the switching element connected to the first gate line G ₁ is turned off and the switching element connected to the second gate line G ₂ is turned on to apply an image signal corresponding to the second pixel row.

In this manner, when the scan signal is sequentially scanned to the last gate line G _M , scanning of one frame is ended, and scanning is started again from the first gate line G ₁ , and then the frame is moved to the next frame.

However, as the resolution of the display screen increases, a larger number of gate lines are required, while the time required to scan from the first gate line to the last gate line, that is, the time taken to scan one frame, is limited. There is a problem that the image quality is low because the time to apply the signal. In addition, as the display screen becomes larger, there is a problem in that the data line becomes longer and the RC delay increases accordingly.

An object of the present invention is to improve the image quality by increasing the time for applying an image signal to a pixel.

1 is a sectional view showing a conventional liquid crystal display device and a driving circuit thereof;

2 is a sectional view showing a liquid crystal display and a driving circuit thereof according to an embodiment of the present invention;

3 is a timing diagram of various signals used in a method of driving a liquid crystal display according to a second embodiment of the present invention.

In order to achieve this problem, the present invention divides a pixel into two pixel groups each including a plurality of pixel bundles. Accordingly, the gate line is also divided into two gator line groups each including a plurality of gate line bundles, and the data line is also divided into two data line groups. The scan signal is simultaneously applied to the two pixel groups, and the scan signal and the image data are successively applied to the pixels belonging to the pixel bundle in each pixel group.

Then, with reference to the accompanying drawings will be described in detail to be easily carried out by those of ordinary skill in the art with respect to the embodiment of the present invention.

2 is a block diagram illustrating a liquid crystal display and a driving circuit thereof according to an exemplary embodiment of the present invention.

As can be seen in FIG. 2, the gate lines G ₁ , G ₂ ,..., Gn, Gn + 1,..., G 2n, and G 2n + that are formed horizontally on the liquid crystal substrate 1 according to the present embodiment. 1, ……, G3n, G3n + 1, ……, G4n) are classified into four bundles, and each bundle is the first, second, third and fourth gate drivers 21, 22, 23 and 24, respectively. Is connected to. Each gate line bundle includes the same number of gate lines, and for convenience, the first gate line bundle from the first gate line G1 to the nth gate line Gn, and the (n + 1) th gate line Gn + 1. To 2n-th gate line G2n, bundle of second gate lines, (2n + 1) -th gate line G2n + 1 to 3n-th gate line G3n, bundle of third gate lines, (3n + 1) Assume that the fourth gate line G3n + 1 to the fourth gate line G4n are the fourth gate line bundles. In addition, the first gate driver 21 and the third gate driver 23 are connected to each other, and the second gate driver 22 and the fourth gate driver 24 are also connected to each other, so that the first and second gates are connected to each other. After the scanning in the driving units 21 and 23 is finished, the scanning in the second and fourth gate driving units 22 and 24 is started. Although only four bundles are shown in Fig. 2, any number may be used as long as they are even.

On the other hand, a pair of data lines are formed vertically for each pixel column. Among them, the plurality of first data lines connected to the upper data driving IC 12 existing on the upper portion of the substrate are connected to pixels connected to the odd-numbered, that is, the first and third gate line bundles, and are located below the substrate. A plurality of second data lines connected to the lower data driver IC 14 are connected to pixels connected to even-numbered, that is, second- and fourth-gate line bundles. In detail, the pixels from the first pixel row to the nth pixel row (hereinafter referred to as the first pixel bundle) and the pixels from the (2n + 1) th pixel row to the 3n pixel row (hereinafter referred to as the third pixel bundle) Is connected to the first data line, pixels of the (n + 1) th pixel row from the 2nth pixel row (hereinafter referred to as the third pixel bundle), and from the (3n + 1) th pixel row to the 4nth pixel row. The leading pixels (hereinafter referred to as a fourth pixel bundle) are connected to the second data line. Of course, each pixel is connected to only one gate line and one data line.

The upper and lower data driving ICs 12 and 14 are connected with a memory (not shown) for storing image data, and there are upper and lower output buffers (not shown), respectively.

Next, an operation of the liquid crystal display according to the first exemplary embodiment of the present invention will be described with reference to the timing diagram of FIG. 3 along with FIG. 2.

First, an input signal containing image data of a pixel is input to the memory from the outside. The input image data is written and stored sequentially from the image data corresponding to the first pixel row at a time determined by the vertical and male sync signals (V _sync , H _sync ) and at a speed determined by the write clock signal. . The image data stored in this way is not output until the image data corresponding to the last pixel row of the first pixel bundle, that is, the nth pixel row, is written.

Image data corresponding to pixels belonging to the second pixel bundle starts to be written to the memory, and at the speed at which the image data corresponding to pixels belonging to the first pixel bundle and the second pixel bundle are determined as read clock signals from the memory. It is output accordingly and starts to be input to the upper and lower source drivers 12 and 14 via the upper and lower output buffers, respectively. At this time, if the read clock signal has a frequency of 1/2 of the write clock signal, the output image data is twice as long as the input image data.

Meanwhile, at the same time, the start signal STV is simultaneously applied to the first gate driving IC 21 and the second gate driving IC 22, and the gate belonging to the first gate line bundle and the gate belonging to the second gate line bundle. The scan signal begins to be supplied to the line at the same time. The scan signal is sequentially supplied from the first gate line and the (n + 1) th gate line, and the time for which the scan signal is supplied to each gate line is doubled as compared with the conventional one. Then, the image data from the upper and lower data driving ICs 12 and 14 are first pixel rows through the first and second data lines D ₁ , D ₂ ,..., C ₁ , C ₂ ,... And (n + 1) th pixel rows.

When the scanning of the first and second pixel bundles is finished, a scan signal is applied from the second gate driver 22 and the fourth gate driver 24, thereby scanning the third and fourth pixel bundles ( 2n + 1) and (3n + 1) pixel rows.

At this time, since the scan signal is supplied to each gate line twice as conventionally, and the period of the image data output from the memory is twice as conventional, the time to input data to the pixel is doubled as compared with the conventional method.

Claims (8)

A plurality of first pixel rows formed transversely from the top of the substrate, A plurality of second pixel rows formed under the first pixel row; A plurality of third pixel rows formed under the second pixel rows; A plurality of fourth pixel rows formed under the third pixel rows; A plurality of first, second, third and fourth gate lines connected to the pixels of the first, second, third and fourth pixel rows, respectively; A first data line connected to the pixels of the first pixel row and the third pixel row, and And a second data line connected to the second pixel row and the pixels of the fourth pixel row. The matrix display device of claim 1, wherein a scan signal is simultaneously supplied to the first gate line and a third gate line, and a scan signal is simultaneously supplied to the second gate line and the fourth gate line. 3. The matrix display device of claim 2, wherein the number of the first pixel rows is the same as the number of the second pixel rows, and the number of the third pixel rows is the same as the number of the fourth pixel rows. The matrix type display device of claim 3, further comprising first, second, third, and fourth gate drivers connected to the first, second, third, and fourth gate lines, respectively, to supply a scan signal. A plurality of pixels arranged in a matrix and classified into first and second pixel groups, A plurality of gate lines formed horizontally and classified into a first gate line group connected to pixels belonging to the first pixel group and a second gate line group connected to pixels belonging to the second pixel group; A plurality of data lines formed vertically and classified into a first data line group connected to pixels belonging to the first pixel group and a second data line group connected to pixels belonging to the second pixel group; Each of the first and second pixel groups is divided into a plurality of pixel bundles, and each pixel bundle includes pixels of neighboring pixel rows, and the pixel bundle of the first pixel group and the pixel bundle of the second pixel group are upper portions. Formed alternately from The number of gate lines is the same as the number of pixel rows, and the first gate line group is divided into a plurality of gate line bundles corresponding to each pixel bundle of the first pixel group, and the second gate line group is the second pixel. A matrix display device divided into a plurality of gate line bundles corresponding to each pixel group of a group. 6. The matrix display device of claim 5, wherein one of the gate lines belonging to the first gate line group and one of the gate lines belonging to the second gate line group are simultaneously applied with a scanning signal. 7. The matrix display device of claim 6, wherein scan signals are sequentially applied to the gate line bundles belonging to the first gate line group, and scan signals are sequentially applied to the gate line bundles belonging to the second gate line group. A plurality of pixels arranged in a matrix and classified into first and second pixel groups, a plurality of gate lines formed horizontally and connected to the pixels, and a plurality of vertically formed and connected to the pixels The first and second pixel groups are each divided into a plurality of pixel bundles, and each pixel bundle includes pixels of neighboring pixel rows, the pixel bundle of the first pixel group and the second pixel group. The pixel group of the pixel group is a driving method of the matrix display device which is formed alternately from the top. Writing to a memory at a first speed in order from image data corresponding to the pixel formed at the top; A gate connected to the pixels of the uppermost pixel groups belonging to the first and second pixel groups after all of the image data corresponding to the pixels of the uppermost pixel groups belonging to the first pixel group are written in the memory Applying a scan signal through a line, Reading image data corresponding to a pixel connected to the gate line to which the scan signal is applied, and applying the image data to the pixel at a second speed, which is half of the first speed, from the memory; A second scan signal applying step of sequentially applying a scan signal to gate lines connected to a second pixel bundle from an upper portion among the pixel bundles belonging to the first and second pixel groups, respectively, immediately after the end of the first scan signal applying step; And reading image data corresponding to a pixel connected to the gate line to which the scan signal is applied, to the pixel at a second speed, which is half the first speed, from the memory. Driving method.