JP3082227B2 - LCD color display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a liquid crystal color for displaying images by arranging liquid crystal display elements provided with, for example, red, green and blue filters in an XY matrix. It relates to a display device.

[Summary of the Invention]

The present invention relates to a liquid crystal color display device, in which the first signal line is formed into a set of red, green, and blue for every three consecutive signal lines, and the pixel electrodes are arranged every other vertical direction at a half pixel pitch in the horizontal direction. The first signal lines are alternately connected to the left and right alternately in every other vertical direction, and these first signal lines are respectively connected to respective red, green, and blue images via switches. Connected to three third signal lines to which signals are supplied, and to the red signal supplied to these third signal lines,
By providing a delay amount corresponding to the pixel pitch relatively to the green and blue video signals and simultaneously controlling the switches in units of a set of red, green and blue, the number of scanning circuit stages driving the switches can be reduced. The configuration is simplified and the power consumption is reduced so that a good display image can be obtained.

[Conventional technology]

For example, it has been proposed to display a television image using a liquid crystal (see Japanese Patent Application Laid-Open No. 59-220793).

That is, in FIG. 3, (1) is an input terminal to which a video signal is supplied, and a signal from this input terminal (1) is a switching element M _H1 , M _H2. L _Hm are supplied to lines (first signal lines) L _H1 , L _H2 ... L _Hm in the vertical (Y-axis) direction through _Hm . Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction.

Further provided horizontal scanning circuit (2) is provided comprising a shift register of m stages, the clock signal [Phi _IH of m times the horizontal frequency in the horizontal scanning circuit (2), [Phi _2H is supplied, the clock signal [Phi _IH, [Phi _The driving pulse signals φ _H1 , φ _H2 ... Φ _Hm sequentially scanned by _2H are taken out from each output terminal of the horizontal scanning circuit (2), and the switching elements M _{H1 to} M _{Hm are obtained.}
Is supplied to each control terminal. A low potential (V _SS ) and a high potential (V _DD ) are supplied to the horizontal scanning circuit (2), and drive pulses of these two potentials are formed.

Also, for example, each channel L _{H1 to} L _Hm has N channels, for example.
FET or Nararu switching elements _{M 11, M 21 ··· M n1} , M 12, M
_{22 ··· M n2, ··· M 1m} , one end of the M _2m ··· M _nm is connected. Note that n is a number corresponding to the number of horizontal scanning lines.

The other end of the switching element M ₁₁ ~M _nm are respectively connected to the Tadetto terminal (3) through the liquid crystal cell _{C 11, C 21 ··· C nm} . Note that P ₁₁ , P ₂₁ ... P _nm indicated by broken lines in the drawing schematically indicate pixel electrodes.

Further, a vertical scanning circuit (4) composed of an n-stage shift register is provided, and clock signals Φ _1V and Φ _2V of a horizontal frequency are supplied to the vertical scanning circuit (4), and the clock signals Φ _1V and Φ _2V are sequentially used. The driving pulse signals φ _V1 , φ _V2 ... Φ _{Vn to} be scanned are taken out from the respective output terminals of the vertical scanning circuit (4), and the gate lines in the horizontal (X-axis) direction (second
G _V1 , G _V2 ... G _Vn are supplied to this gate line.
G _V1 ~G _Vn through the switching element M ₁₁ ~M _nm in the X-axis direction each column of _{(M 11 ~M 1m), (} M 21 ~M 2m) ··· (M n1 ~M nm)
Are supplied to the respective control terminals. Note that _VSS and _VDD are also supplied to the vertical scanning circuit (4) as in the horizontal scanning circuit (2).

That is, in this circuit, the scanning circuits (2) and (4)
The clock signals Φ _1H , Φ _2H , Φ as shown in FIGS.
_1V and _Φ2V are supplied. The horizontal scanning circuit (2) outputs φ _H1 to φ _Hm for each pixel period as shown in FIG. C, and the vertical scanning circuit (4) outputs for each horizontal period as shown in FIG. φ _{V1 to} φ _Vn are output. Further, the input terminal (1) is supplied with a signal as shown in FIG.

When φ _V1 and φ _H1 are output, the switching elements M _H1 and M _{11 to} M _1m are turned on, and the input terminal (1) → M
_{H1 → L H1 → M 11 →} C 11 → the potential difference between the target terminal (3) the signal current path is supplied is formed in the input terminal to the liquid crystal cell C ₁₁ (1) of the target terminal (3) is supplied You.
Therefore, a charge corresponding to the potential difference due to the signal of the first pixel is sampled and _{held in} the capacity of the cell C11. The light transmittance of the liquid crystal is changed according to this charge amount. It similar to this is successively performed for the cell C ₁₂ -C _nm, the charge amount of each cell C ₁₁ -C _nm is rewritten further when the signal is supplied for the following fields.

Thus, the liquid crystal cell C ₁₁ -C _nm light transmittance is changed corresponding to each pixel of the video signal, which displays the television image is repeated sequentially.

In the case of performing display using liquid crystal, AC driving is generally used to improve the reliability and extend the life. For this reason, the input terminal (1) is connected to one field or one
A signal obtained by inverting the video signal for each frame is supplied.

[Problem to be solved by the invention tile]

However, in this apparatus, when the number of horizontal pixels is increased for the purpose of increasing the resolution of an image, the number of stages of the shift register as the horizontal scanning circuit (2) increases, thereby increasing power consumption for driving. (In proportion to the number of stages), and the clock frequency becomes higher due to the increase in the number of stages, so that the power consumption also increases (in proportion to the frequency).

The signal supplied to the input terminal (1) is, phi _H1 to [phi] _Hm
Switching elements M ₁₁ to the period is once charged in the wiring capacitance C _H of the vertical signal line L _H via ~M _nm, but is then supplied to the respective liquid crystal cell, wherein the number of stages is the clock frequency is increased higher, phi _H1 the length of the ~φ _Hm is shortened. If you try this for sufficiently driving the video signal wiring capacitance C _H of phi _H period to the vertical signal line L _H of (charge), the on resistance of the switching element M _H must be fairly low and therefore element Size (W / L) must be increased. On the other hand, when the number of horizontal pixels is to be increased, the number of switching elements _MH is also large, and the number and size are large. The proportion of the area occupied by _MH was extremely large.

By the way, the applicant of the present application has previously described Japanese Patent Application Laid-Open
58-214865 (see JP-A-60-107862),
Japanese Patent Application Laid-Open Nos. 59-221581 (see Japanese Patent Application Laid-Open No. 61-100086) and Japanese Patent Application Laid-Open No. 60-232018 (see Japanese Patent Application Laid-Open No. 62-90692) are proposed.

The present application has been made in view of such a point, and reduces the power consumption by reducing the number of stages of the scanning circuit, and also reduces the proportion of the area occupied by the switching elements on the chip, which is favorable with a simple configuration. It is intended to obtain a suitable display image.

[Means for solving the problem]

According to the present invention, a plurality of first signal lines (lines L _{H1 to} L _Hm ) which are arranged in parallel in the vertical direction and form a set of red, green and blue for every three consecutive lines, respectively, A plurality of second signal lines (gate lines G _{V1 to} G _Vn ),
Each of the intersections of the second signal lines is provided via a selection element (M _{11 to} M _nm ), and is provided at every other one of the vertical directions so as to be shifted by a half pixel pitch in the horizontal direction. Pixel electrodes (P _{11 to} P _nm ) alternately connected to the first signal line to the left and right in every other direction;
A plurality of first switches (horizontal switching elements M _R1 , M _G1 , M _{B1 to} M _Rs , M _Gs ,
M _Bs ) and three third signal lines ((14R) (14G) connected to each of the first signal lines via these switches and supplied with red, green, and blue video signals, respectively. )(14
B)), and the above-mentioned red supplied to these three signal lines,
First delay means (circuit (11R) (11) for mutually providing delay amounts corresponding to ± 1 pixel pitch to green and blue video signals.
G) (11B)) and a second delay means for commonly providing a delay amount corresponding to a 3/2 pixel pitch to the red, green, and blue video signals supplied to the three signal lines. (Circuit (13
R), (13G), and (13B)) and a second switch ((()) that selects a signal from the first delay unit and a signal from the second delay unit at every other timing in the vertical direction. 12
R) (12G) (12B)) and switch driving means (horizontal scanning circuit (2)) for simultaneously controlling the first switch in units of the red, green, and blue units. This is a liquid crystal color display device.

[Action]

According to this, the first signal line is set to red, green and blue every three consecutive signal lines, and the pixel electrodes are provided at every other vertical direction and shifted by 1/2 pixel pitch in the horizontal direction. And alternately connected to the left and right with respect to the first signal line every other in the vertical direction. These first signal lines are supplied with red, green, and blue video signals for each color via switches. Connected to the three third signal lines, and the red, green, and blue video signals supplied to these third signal lines are reduced by half.
The delay amount corresponding to the pixel pitch is given relatively, and the switches are simultaneously controlled in units of red, green and blue, so that the number of scanning circuit stages is reduced and power consumption is reduced. Also, the ratio of the area occupied by the switching elements on the chip is reduced, and a good display image can be obtained with a simple configuration.

〔Example〕

In Figure 1, the switching element M ₁₁ ~M _nm with is provided in the opposite direction to the line L _H1 ~L _nm every other vertical and horizontal position of each pixel electrode P ₁₁ to P _nm At a half pixel pitch. Further with respect to the pixel electrode P ₁₁ to P _nm, red (R), green (G), and blue 3 from the position of the so-called vertical stripes horizontally every other vertical as the color filters shown in (B) It is provided shifted by a / 2 pixel pitch. Note that, specifically, the lines L _{H1 to} L _nm are formed of an opaque member such as aluminum, so that the lines L _{H1 to} L _nm are provided in a zigzag along the boundaries of the pixel electrodes P _{11 to} P _nm. Switching element
M _{11 to} M _nm are provided facing the outside of the zigzag.

On the other hand, input terminals (1R), (1G), and (1B) for supplying red, green, and blue video signals are provided.
R) (1G) (1B) signals from the delay circuit (11R)
It is supplied to the (11G) (11B), the delay of the signal corresponding to the position of the pixel electrode P ₁₁ to P _nm is performed. With these delayed signals are supplied to a switch (12R) (12G) (12B ), a delay circuit (11R) (11G) pixel electrode P ₁₁ of each scanning line to which a signal from the (11B) is above ~P _The signal is supplied to the switches (12R), (12G), and (12B) through delay circuits (13R), (13G), and (13B) that delay the signal corresponding to the position of _nm . Then, signals from these switches (12R), (12G), and (12B) are supplied to the third signal lines (14R), (14G), and (14B), respectively.

The horizontal switching elements M _H1 ~M _nm described above, three per each red continuous, green, blue and set _{(M R1, M G1, M} B1 ~
M _Rs , M _Gs , M _Bs : where s = m / 3), and signal lines (14R) of colors corresponding to these switching elements M _R1 , M _G1 , M _{B1 to} M _Rs , M _Gs , M _Bs respectively. ) (14G) and (14B) are connected. These switching elements M _R1 , M _G1 , M _{B1 to} M _Rs , M _Gs , M _Bs
Are commonly connected to each of the above-described red, green, and blue sets.

Further, a horizontal scanning circuit (21) composed of s-stage shift registers is provided. Clock signals Φ _1X and Φ _2X having s times the horizontal frequency are supplied to the horizontal scanning circuit (21), and the clock signals Φ _1X and Φ _The driving pulse signals φ _X1 , φ _X2 ... Φ _Xs sequentially scanned by _2X are taken out from each output terminal of the horizontal scanning circuit (21), and the switching elements M _R1 , M _G1 ,
The signals are supplied to common control terminals of M _{B1 to} M _Rs , M _Gs and M _Bs . A low potential (V _SS ) and a high potential (V _DD ) are supplied to the horizontal scanning circuit (21), and drive pulses of these two potentials are formed.

Otherwise, the configuration is the same as that of the circuit described in the description of the related art.

Therefore, in this apparatus, the number of stages of the shift register as the horizontal scanning circuit (21) is 1/3 of the number of horizontal pixels, and the clock frequency for driving this horizontal scanning circuit (21) is also
The power consumption can be reduced to 1/3, for example, to 1/9.

Since the time width of the drive pulse signal phi _X is 3 times the phi _H, the switching element M _R, M _G, the size of M _B and (W / L) M _H
The can to 1/3, even if the number of horizontal pixels three times, the area occupied by the switching element M _R, M _G, of M _B can be approximately equal.

Furthermore, in this device, red, green, since the position of the pixel of blue is offset in the horizontal direction, the switching element M _R as described above, M _G, when driving the M _B by the same drive pulse signal phi _M For example, the horizontal resolution may be degraded due to a shift between the signal position and the display position. Therefore, in this apparatus, signals from the input terminal (1R) (1G) (1B ) is supplied to the delay circuits (11R) (11G) (11B ), corresponding to the position of the pixel electrode P ₁₁ to P _nm The signal is delayed. That is, in this apparatus, for example, the red video signal two clocks of the original drive pulse signal phi _H, 1 clock is green video signal, a video signal of blue delay 0 clocks (no delay) is performed.

Thereby, for example, the red (R) as shown in FIG. 2A
When there are green (G) and blue (B) video signals, the conventional apparatus performs sampling as shown in FIG. In the above-described apparatus, sampling is performed as shown in FIG. In this case, the delay circuit (11
Red by the delay in R) (11G) (11B) , green video signals and blue is as shown in FIG. D, even if sampling at the same drive pulse signal phi _X, similar to the conventional Sampling can be performed.

Further delay circuit (13R) (13G) (13B ) in this section of the specification corresponding to the horizontal direction of displacement of the pixel electrode P ₁₁ to P _nm of each scan line, for example, 3 / delay amount of 2 [phi _H is provided I have. The switches (12R), (12G), and (12B) are switched every horizontal period, so that the signal lines (14R), (14G), (14
Supply of a signal corresponding to the horizontal direction of displacement of the pixel electrode P ₁₁ to P _nm is performed in B).

Thus, according to this device, the first signal line is set to red, green and blue every three consecutive lines, and the pixel electrodes are shifted in the horizontal direction by 1/2 pixel pitch every other vertical line. And alternately connected to the left and right with respect to the first signal line every other in the vertical direction, and these first signal lines are respectively connected to the red, green,
A delay amount corresponding to a 1/2 pixel pitch is connected to the three third signal lines to which the blue video signal is supplied, and to the red, green, and blue video signals supplied to these third signal lines. And the switches are simultaneously controlled in units of red, green, and blue, thereby reducing the number of stages of the scanning circuit and power consumption, and reducing the number of switching elements on the chip. The proportion of the occupied area has also been reduced,
A good display image can be obtained with a simple configuration.

In this device, the scanning circuit, sampling means, etc.
The present invention is applied to a liquid crystal color display device on-chip together with a liquid crystal cell.

〔The invention's effect〕

According to the present invention, the first signal line is set to red, green, and blue for every three consecutive signal lines, and the pixel electrodes are shifted by 1/2 pixel pitch in the horizontal direction every other vertical direction. And alternately connected to the left and right with respect to the first signal line every other in the vertical direction. These first signal lines are respectively connected to respective red, green and blue video signals via switches via the respective switches. Connected to the three supplied third signal lines, and to the red, green, and blue video signals supplied to these third signal lines.
The delay amount corresponding to 1/2 pixel pitch is given relatively, and the switches are controlled simultaneously in units of red, green and blue, so the number of scanning circuit stages is reduced and power consumption is reduced. At the same time, the ratio of the area occupied by the switching elements on the chip is reduced, and a good display image can be obtained with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a liquid crystal color display device according to the present invention, FIG. 2 is a timing chart diagram for explaining the same, FIG. 3 is a configuration diagram of a conventional liquid crystal display device, and FIG. FIG. M is an element constituting a horizontal switching element and a selection element, L is a line as a first signal line, G is a gate line as a second signal line, P is a pixel electrode, C is a liquid crystal cell,
(1R) (1G) (1B) are input terminals to which red, green, and blue video signals are supplied, and (11R) (11G) (11B) (13R) (13G) (1
3B) is a delay circuit, (12R) (12G) (12B) is a switch,
(14R), (14G) and (14B) are third signal lines, (21) is a horizontal scanning circuit, (3) is a target terminal, and (4) is a vertical scanning circuit.

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁷ identification symbol FI H04N 9/12 H04N 9/12 B (58) Investigated field (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1 / 133 G09G 3/20 H04N 9/12

Claims (1)

(57) [Claims] 1. A plurality of first signal lines which are arranged in parallel in the vertical direction and form a set of red, green and blue for every three consecutive lines, and a plurality of first signal lines which are arranged in parallel in the horizontal direction. 2 signal lines and the intersections of the first and second signal lines are provided via selection elements, respectively, and are provided at every other vertical direction and shifted by 1/2 pixel pitch in the horizontal direction. A pixel electrode alternately connected to the first signal line to the left and right every other in the vertical direction, a plurality of first switches provided respectively corresponding to the first signal line, Three third signal lines connected to each color of the first signal line via these switches and supplied with red, green, and blue video signals, respectively, and supplied to these three signal lines. A delay amount corresponding to ± 1 pixel pitch is given to each of the red, green, and blue video signals. First delay means, and second delay means for commonly providing a delay amount corresponding to a 3/2 pixel pitch to the red, green, and blue video signals supplied to the three means. A second switch for selecting a signal from the first delay unit and a signal from the second delay unit at every other timing in the vertical direction; and setting the first switch to the red and green. And a switch driving means for simultaneously controlling a blue group as a unit.