JP2006330510A - Electro-optic device, driving method and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a period for sampling a data signal Vid supplied to an image signal line 171. <P>SOLUTION: This electro-optic device has pixels 110 provided corresponding to scanning lines 112 and data lines 114, a scanning line drive circuit 130 for selecting the scanning lines in a predetermined order, an image signal line 171 to which the data signal Vid with voltage according to tone of the pixels corresponding to the selected scanning line 112 is supplied, a sampling signal output circuit 140 for sequentially and exclusively outputting sampling signals in the predetermined order, a sampling circuit 152 for sampling the data signal Vid according to the sampling signal and an amplifier circuit 156 for holding voltage of the data signal sampled by the sampling circuit 152, amplifying the held voltage by an amplification factor based on predetermined potential to be supplied to the data lines 114. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for shortening a period for sampling a data signal supplied to an image signal line.

  In recent years, projectors that form a small reduced image by using a display panel such as a liquid crystal and enlarge and project the small reduced image by an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data designates the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the display panel used in the projector, the scanning lines are selected one by one in a predetermined order, and the data lines are selected one by one in order during the period in which the scanning line is selected. In general, driving is performed in a dot sequential manner in which a data signal converted to be suitable for driving a liquid crystal is supplied to a selected data line.

On the other hand, recently, high definition of a display image is progressing like high vision. High definition can be achieved by increasing the number of scanning lines and the number of data lines, but since the frame frequency is fixed, the increase in the number of scanning lines shortens one horizontal scanning period. Furthermore, in the dot sequential method, the data line selection period is shortened by increasing the number of data line columns. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient.
Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1). In this phase expansion drive, data lines are blocked every predetermined column, for example, every six columns, and blocks are selected one by one in a predetermined order in one horizontal scanning period, and six columns belonging to the selected block are selected. In this method, a data signal expanded to 6 times the time axis is supplied to each data line. In this phase development driving method, the time for supplying the data signal to the data line can be secured 6 times in this example as compared with the dot sequential method, and thus it is considered suitable for high definition. Yes.
JP 2000-112437 A

By the way, in such a phase development drive system, a data signal is expanded six times on the time axis and a configuration for distributing the data signal to six image signal lines is additionally required, and blocks are selected one by one. Due to the configuration, vertical streak-like unevenness, that is, a phenomenon in which the gradation of pixels slightly changes every six columns corresponding to one block, and the deterioration of display quality becomes conspicuous.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device, a driving method, and an electronic apparatus capable of achieving high-definition display without employing a phase expansion driving method. Is to provide.

  In order to achieve the above object, according to the present invention, a plurality of pixels provided corresponding to a plurality of scanning lines and a plurality of data lines, and scanning that selects the plurality of scanning lines in a predetermined order. A line driving circuit, an image signal line to which a data signal having a voltage corresponding to a gradation of a pixel corresponding to the scanning line selected by the scanning line driving circuit is supplied, and a sampling signal are sequentially output in a predetermined order. Corresponding to a sampling signal output circuit, a sampling circuit provided corresponding to each of the plurality of data lines, and sampling a data signal supplied to the image signal line according to the sampling signal, and the plurality of data lines And holding the voltage of the data signal sampled by the sampling circuit and using the held voltage with reference to a predetermined potential. Was then amplified by the amplification factor, characterized by comprising an amplifier circuit for supplying to the data lines. According to the present invention, since the data signal supplied to the image signal line is indirectly supplied to the data line via the sampling circuit and the amplifier circuit, the data signal sampling period can be shortened.

In the present invention, the sampling circuit may be configured as an n or p channel type transistor, or may be configured such that n and p channel type transistors are connected in parallel. In the present invention, the amplifier circuit includes n-channel and p-channel transistors connected in series, and the data signal sampled by the sampling circuit is commonly input to the gates of both transistors. The drains may be connected to the data line in common.
Furthermore, the present invention can be conceptualized not only as an electro-optical device but also as a driving method of an electro-optical device and an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit that controls the operation of the display panel 100 and the like, and is a circuit module mounted on a printed board, and is connected to the display panel 100 by an FPC (Flexible Printed Circuit) board or the like. ing.

The processing circuit 50 is further divided into a scanning control circuit 52, a D / A conversion circuit 54, and a polarity inversion circuit 56.
Among these, the D / A conversion circuit 54 converts the image data Vin supplied from a host device (not shown) into an analog signal in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal Dclk. It is. Here, the image data Vin is digital data for designating the gradation (brightness) of the pixel.

In the horizontal effective display period, the polarity inversion circuit 56 supplies the analog signal converted by the D / A conversion circuit 54 to the power source by the voltage of the analog signal when the positive polarity is instructed by the polarity instruction signal Pol. Is converted to a higher level than the voltage Vc, which is a substantially intermediate value between the high-side voltage Vdd and the ground potential Gnd. On the other hand, when a negative polarity is indicated by the polarity indication signal Pol, it is converted to a lower side than the voltage Vc Thus, the data signal Vid is supplied to the image signal line 171 of the display panel 100.
For this reason, in this embodiment, regarding the polarity of the data signal Vid, the higher side than the voltage Vc is referred to as positive polarity, and the lower side is referred to as negative polarity. The voltage is based on the ground potential Gnd of the power supply unless otherwise specified.
In addition, the polarity inversion circuit 56 uses the data signal Vid as a voltage that causes the pixel to blacken in the polarity specified by the polarity instruction signal Pol in the horizontal blanking period. However, when the precharge signal Pre is designated by the precharge signal Pre in the horizontal blanking period, the polarity inversion circuit 56 sets the data signal Vid to the voltage Vc only during the precharge period.

It should be noted that how pixels are inverted in one vertical scanning period (frame) is (a) every scanning line, (b) every data signal, (c) every pixel, (d) every surface (frame), etc. Although there are various modes, in this embodiment, it is assumed that (a) polarity inversion is performed for each scanning line. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the data signal Vid as shown in FIG. In the present embodiment, the image data Vd is converted to analog after serial-parallel conversion, but of course, analog conversion may be performed before serial-parallel conversion.

  The scanning control circuit 52 controls the scanning of the display panel 100 and outputs a polarity instruction signal Pol and a precharge signal Pre in synchronization with the scanning. Specifically, the scanning control circuit 52 generates a transfer start pulse DX and a clock signal CLX from the dot clock signal Dclk, the vertical scanning signal Vs, and the horizontal scanning signal Hs supplied from the host device, and performs horizontal scanning of the display panel 100. And a transfer start pulse DY and a clock signal CLY are generated to control vertical scanning of the display panel 100, and in addition to the horizontal scanning, a polarity instruction signal Pol and a precharge signal Pre are output.

On the other hand, the display panel 100 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and liquid crystal is sealed in the gap. A predetermined image is formed by the change.
As shown in FIG. 1, in this display panel 100, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 columns of data lines 114 extend in the Y (vertical) direction in the figure. Exist. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns in the display region 100a, but the present invention is not limited to this.

FIG. 2 is a diagram showing a detailed configuration of the pixel 110 in the display panel 100, corresponding to the intersection of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto. A 2 × 2 configuration for a total of four pixels is shown. Here, i and (i + 1) are symbols for generally indicating a row in which the pixels 110 are arranged, are integers of 1 to 864, and j and (j + 1) are columns in which the pixels 110 are arranged. In general, the symbol is an integer of 1 to 1152.
As shown in FIG. 2, in the pixel 110, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114 and the drain is connected to the pixel electrode 118, while the gate is the scanning line 112. It is connected to the.
Further, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a pixel capacitor composed of the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.
Note that a constant voltage LCcom is applied to the common electrode 108 in time, but this voltage (potential) is the same as the reference voltage Vc in this embodiment. However, it may be set slightly lower than the reference voltage Vc for reasons described later.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the effective voltage applied to the pixel capacitor is zero, the light passing between the pixel electrode 118 and the common electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the effective voltage value is As it increases, the liquid crystal molecules tilt in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in the transmission type, when the polarizers are respectively arranged on the incident side and the back side so that the polarization axis coincides with the alignment direction, the light transmittance is maximum if the voltage effective value is close to zero. On the other hand, while the white display is obtained, the amount of transmitted light decreases as the effective voltage value increases, and finally the black display with the minimum transmittance is obtained (normally white mode).

Further, in order to reduce the influence of charge leakage from the pixel capacitor via the TFT 116 at the off time, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), while the other end is commonly connected to the capacitor line 107 over all pixels. Although not shown in FIG. 1, the capacitor line 107 is maintained at the same voltage LCcom as the common electrode 108 in the present embodiment. Specifically, although the capacitor line 107 is formed on the element substrate and the common electrode 108 is formed on the counter substrate, the capacitor line 107 and the common electrode 108 are electrically connected by a conductive material (not shown). ing. For this reason, the pixel electrode 118 (the drain of the TFT 116) and the common electrode 108 have a configuration in which a pixel capacitor and a storage capacitor are added in parallel for each pixel 110.
Note that the TFT 116 in the pixel 110 is formed by a common manufacturing process with a scanning line driving circuit 130, a sampling signal output circuit 140, and the like, which will be described below, and contributes to downsizing and cost reduction of the entire device.

In FIG. 1, peripheral circuits such as a scanning line driving circuit 130 and a sampling signal output circuit 140 are provided around the display region 100a in which the pixels 110 are arranged.
Among these, the scanning line driving circuit 130 supplies the scanning signals G1, G2, G3,..., G864 to the scanning lines 112 in the first row, the second row, the third row,. is there. The details of the scanning line driving circuit 130 are omitted because they are not directly related to the present invention. However, as shown in FIG. 4, the scanning line driving circuit 130 is supplied at the beginning of each vertical effective display period and corresponds to a half cycle of the clock signal CLY. The transfer start pulse DY having a pulse width (H level) to be shifted is sequentially shifted every time the level of the clock signal CLY transitions (rises or falls), and the pulse width is narrowed so that the scanning signals G1, G2 , G3,..., G864.
In the present embodiment, the vertical scanning period is divided into a vertical blanking period and a vertical effective display period following the blanking period. Here, the vertical effective display period is from the timing at which the level of the clock signal CLY transitions immediately before the scanning signal G1 becomes H level to the timing at which the level of the clock signal CLY transitions immediately after the scanning signal G864 becomes L level. The period excluding the vertical effective display period in the vertical scanning period is defined as a vertical blanking period.

Next, as shown in FIG. 4 or FIG. 5, the sampling signal output circuit 140 is supplied at the start of the horizontal effective display period and starts transfer having a pulse width (H level) corresponding to a half cycle of the clock signal CLX. The pulse DX is sequentially shifted each time the level of the clock signal CLX changes, and is output as sampling signals S1, S2, S3,..., S1152. That is, the sampling signals S1, S2, S3,..., S1152 are sequentially set to the H level exclusively during the horizontal effective display period.
In the present embodiment, the horizontal scanning period is divided into a horizontal blanking period and a horizontal effective display period following the blanking period. Here, as shown in FIG. 5, the horizontal effective display period corresponds to a period during which any one of the scanning signals is at the H level. Specifically, the sampling signal S1152 from the timing at which the sampling signal S1 is at the H level. Is a period up to the timing at which only time T1 has passed, and a period excluding the horizontal effective display period in the horizontal scanning period is defined as a horizontal blanking period.
Further, as shown in FIG. 5, in the horizontal blanking period, the sampling signal output circuit 140, when the precharge signal Pre becomes H level, only during the period when the precharge signal Pre becomes H level, the sampling signals S1, S2, S3,..., S1152 are simultaneously set to the H level.

The sample and hold circuit 150 is an aggregate of a set of a sampling circuit 152 and an amplification circuit 156 provided corresponding to each of the data lines 114.
Since the configuration of the sampling circuit 152 and the amplification circuit 156 is the same in each column, FIG. 3 shows the configuration of the sampling circuit 152 and the amplification circuit 156 generally corresponding to the data line 114 in the jth column. The description will be given with reference.

As shown in FIG. 3, the sampling circuit 152 corresponding to the j-th data line is an n-channel TFT, and a sampling signal Sj is supplied to the gate thereof. The source of the TFT constituting the sampling circuit 152 is connected to the image signal line 171, and the drain thereof is connected to the input terminal Aj of the amplifier circuit 156.
The amplifier circuit 156 corresponding to the data line 114 in the j-th column has a p-channel type TFT 1562 and an n-channel type TFT 1564 having complementary characteristics. Among these, the source of the TFT 1562 supplies the power supply voltage Vdd. On the other hand, the source of the TFT 1564 is grounded to the potential Gnd. The gates of the TFTs 1562 and 1564 are commonly connected to the input terminal Aj, while the drains of the TFTs 1562 and 1564 are commonly connected to the output terminal Bj. The output terminal Bj is connected to the data line 114 in the jth column.
Therefore, the amplifier circuit 156 has a configuration in which a voltage obtained by inverting the voltage of the input terminal Aj appears at the output terminal Bj with reference to Vc, which is an intermediate value of the voltage (Vdd−Gnd).
It should be noted that the gate capacitance Cs of the TFTs 1562 and 1564 is parasitic on the input terminal Aj as indicated by a broken line in FIG.

Next, the operation of the electro-optical device 10 will be described.
First, the transfer start pulse DY is supplied to the scanning line driving circuit 130 at the beginning of one vertical effective display period. By this supply, as shown in FIG. 4, the scanning signals G1, G2, G3,..., G864 sequentially and exclusively become H level every horizontal scanning period.
Here, attention is paid to the horizontal effective display period in which the scanning signal G1 is at the H level and the horizontal blanking period immediately before the horizontal effective display period. In the horizontal blanking period, as shown in FIG. 5, in the horizontal blanking period, after the logic level of the polarity instruction signal Pol is inverted, the precharge signal Pre becomes an H level pulse. Further, the image data Vin is not supplied in the horizontal blanking period.

Here, in the period when the precharge signal Pre is at the H level, the polarity inversion circuit 56 sets the data signal Vid to the voltage Vc, while the sampling signal output circuit 140 sets all the sampling signals S1, S2, S3,. S1152 is set to H level. Therefore, the TFTs of all the sampling circuits 152 are in a conductive state (on) between the source and the drain, and sample the data signal Vid of the voltage Vc supplied to the image signal line 171. In the j-th column, since the input terminal Aj of the amplifier circuit 156 is the voltage Vc, the output terminal Bj is also the voltage Vc. Since this operation is performed over all of the 1st to 1152th columns, all the data lines 114 are precharged to the voltage Vc.
When the precharge signal Pre returns to the L level during the horizontal blanking period, the TFTs of all the sampling circuits 152 are in a non-conductive state (off) between the source and the drain. The input terminal is held at the voltage Vc by the capacitor Cs and the data line 114 by the parasitic capacitance.

Next, when the horizontal blanking period ends and the horizontal effective display period starts, image data Vin corresponding to the pixels 110 in the first row and the first column is first supplied. Here, in the one horizontal effective display period in which the scanning signal G1 is at the H level, when the polarity instruction signal Pol is at the H level and the positive polarity is instructed, the data signal Vid is the image data Vin on the basis of the voltage Vc. Only the voltage specified in (1) becomes the higher voltage (see FIG. 5).
On the other hand, the sampling signal S1 becomes H level in accordance with the supply of the image data Vin corresponding to the pixel 110 in the first row and the first column. When the sampling signal S1 becomes the H level, only the TFT of the sampling circuit 152 in the first column is turned on, the data signal Vid supplied to the image signal line 171 is sampled, and is input to the input terminal of the amplification circuit 156 in the first column. Supply. The amplifier circuit 156 inverts the data signal Vid supplied to the input terminal with respect to the voltage Vc and supplies the inverted data signal Vid to the first column data line 114 connected to the output terminal.
Further, since the TFT 116 is turned on in all the pixels 110 located in the first row when the scanning signal G1 is at the H level, the data signal Vid inverted with reference to the voltage Vc is in the first column. When supplied to the data line 114, the data signal is applied to the pixel electrode 118.

Next, image data Vin corresponding to the pixels 110 in the first row and the second column is supplied. For this reason, the data signal Vid becomes a higher voltage by the voltage specified by the image data Vin with reference to the voltage Vc (see FIG. 5).
In addition, referring to the relationship of the voltages in FIG. 5, when the voltages Vw (−) and Vg (−) are applied to the pixel electrode 118, the pixel is set to the highest gradation white and the intermediate gradation gray, respectively. Negative voltage. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the pixel electrode 118, cause the pixel to have the highest gradation white and the intermediate gradation gray, respectively. It is symmetrical with Vw (−) and Vg (−) when used as a reference.

  On the other hand, in accordance with the supply of the image data Vin corresponding to the pixel 110 in the first row and the second column, the sampling signal S2 is now at the H level. When the sampling signal S2 becomes H level, only the TFT of the sampling circuit 152 in the second column is turned on, the data signal Vid supplied to the image signal line 171 is sampled, and is input to the input terminal of the amplification circuit 156 in the second column. Supply. The amplifier circuit 156 inverts the data signal Vid supplied to the input terminal with respect to the voltage Vc, and supplies the inverted data signal Vid to the second column data line 114 connected to the output terminal. For this reason, when the data signal Vid inverted with reference to the voltage Vc is supplied to the data line 114 in the second column, the data signal is applied to the pixel electrode 118.

  In the same manner, image data Vin corresponding to the pixels 110 in the first row, the third column, the first row, the fourth column, the first row, the fifth column,..., The first row and the 1152 columns are supplied, and the sampling signals S3, S4, S5,. .., S1152 sequentially becomes H level, the inverted signals of the data signal Vid are sampled on the data lines 114 of the 3, 4, 5,..., 1152 columns, respectively, and these inverted signals are located in the first row. The voltage is sequentially applied to the pixel electrode 118 of the pixel 110. As a result, writing of the negative polarity signal in which the positive polarity data signal Vid is inverted by the amplification circuit 156 of each column is completed for all 1152 pixels located in the first row.

  Subsequently, a horizontal effective display period in which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, the data signal Vid is negative in this one horizontal effective display period. For this reason, the data signal Vid output from the polarity inversion circuit 56 becomes a lower voltage by the voltage specified by the image data Vin with reference to the voltage Vc (see FIG. 5). Other operations are the same as in the one horizontal scanning period in which the immediately preceding scanning signal G1 is at the H level, and the input terminals and output terminals (that is, the data lines 114) in the amplifier circuits 156 of all the columns are connected to the horizontal blanking period. After the precharge to the voltage Vc at, the writing of the positive polarity signal in which the negative polarity data signal Vid is inverted is completed for the pixel 110 located in the second row.

Similarly, the scanning signals G3, G4,..., G864 become H level, and writing is performed on the pixels in the third row, fourth row,. As a result, a negative polarity signal in which the positive polarity data signal Vid is inverted is written to the pixels in the odd-numbered rows, while a positive polarity in which the negative polarity data signal Vid is inverted for the pixels in the even-numbered rows. In this one vertical scanning period, the writing is completed over all the pixels in the first to 864th rows.
In the next one vertical scanning period, the same writing is performed. At this time, the writing polarity for the pixels in each row is switched by the polarity instruction signal Pol. That is, in the next one vertical scanning period, a positive polarity signal in which a negative polarity data signal Vid is inverted is written to an odd row pixel, while a positive polarity data is written to an even row pixel. The negative polarity signal in which the signal Vid is inverted is written. In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal 105, and deterioration of the liquid crystal 105 is prevented.

In the present embodiment, the data signal Vid supplied to the image signal line 171 is sampled in order by the sampling circuit 152 provided in each of the data lines 114, and the sampled data signal is inverted and amplified by the amplifier circuit 156. The data line 114 is supplied.
If each of the parasitic capacitances in each data line 114 is large, the configuration in which the data signal Vid is directly sampled on the data line 114 by the sampling circuit 152 not only lowers the output impedance of the data signal Vid in the polarity inversion circuit 56, but also As shown in FIG. 6B, sampling is performed in order to secure time until the voltage sampled on the data line 114 is charged to the voltage Vg1 (+) of the data signal Vid supplied to the image signal line 171. It is necessary to lengthen the sampling time during which the signal is at the H level, and it becomes impossible to increase the definition of the image by increasing the number of pixels.
In order to lengthen the sampling time, as described in the background art section, data signals expanded in the time axis are supplied to a plurality of image signal lines, and a plurality of data lines are simultaneously used by a plurality of sampling circuits. Although there is a so-called phase expansion technique for sampling a data signal, there is a problem in that phase unevenness causes display unevenness due to sampling of data signals on a plurality of data lines.

On the other hand, in this embodiment, for example, the data signal Vid supplied to the image signal line 171 by the sampling circuit 152 in the j-th column is sampled. At this time, the voltage sampled by the sampling circuit 152 is j-th column. It is applied not to the data line 114 of the eye but to the portion from the drain of the sampling circuit 152 to the input terminal Aj of the amplifier circuit 156. In this part, since only the capacitance Cs parasitic to the gates of the TFTs 1562 and 1564 constituting the amplifier circuit 156 is present, in this embodiment, as shown in FIG. 6A, for example, the data signal Vid is a positive voltage. In the case of Vg1 (+), it is possible to shorten the time until the voltage of the input terminal Aj sampled in the portion is charged to the Vg1 (+).
As described above, in this embodiment, even in the so-called dot sequential method, the data signal Vid can be sampled to the input terminal of the amplifier circuit 156 in a short time. There is no room for generation, high-quality display is possible, and no circuit for phase expansion is required.
Note that the amplifier circuit 156 outputs the output terminal Bj, that is, the j-th column so that the voltage Vg1 (+) of the input terminal Aj held by the capacitor Cs becomes the voltage Vg1 (−) obtained by inverting the voltage Vc. The data line 114 is charged.
Here, in this embodiment, the time for sampling the data signal Vid supplied to the image signal line 171 can be shortened, but before the voltage of the data line 114 becomes the inverted voltage of the sampled voltage. Only time T1 is required. For this reason, in this embodiment, the scanning signal is changed from the H level to the L level at the timing when the sampling signal S1152 becomes the H level and only the time T1 has elapsed, and the data line 114 of the last 1152th column is changed. The voltage is set to be an inverted voltage of the sampled voltage.

In the above-described embodiment, the sampling circuit 152 is an n-channel TFT, but may be a p-channel TFT. Furthermore, if the sampling circuit 152 is a transmission gate combining both channels as shown in FIG. 7, the voltage drop from the image signal line 171 to the input terminal Aj can be improved to near zero. .
In the amplifier circuit 156, when the voltage aj of the input terminal Aj is expressed at the output terminal Bj, the voltage (Vc−aj) appears. However, a voltage obtained by multiplying this by a certain coefficient is obtained. You may make it appear.
Further, when the number of pixels is increased, the above-described phase expansion may be used in combination.

Further, in the embodiment, the voltage LCcom applied to the common electrode 108, it had to match the potential V _C is a measure of the polarity inversion, since elements constituting the sampling circuit 152 is a TFT, of the TFT gate -Due to the parasitic capacitance between the drains, a phenomenon in which the potential of the drain (pixel electrode 118) decreases from on to off (referred to as push-down, penetration, field-through, etc.) occurs. In order to prevent the deterioration of the liquid crystal, AC driving is basically used for the pixel capacitance, so that the same gradation is alternately written on the high-order side (positive polarity) and the low-order side (negative polarity) with respect to the common electrode 108. in a state of being matched voltage LCcom the voltage V _C, when the alternating writing, for pushdown, the effective voltage value of the pixel capacitance, who negative writing becomes larger than the positive polarity writing. Therefore, as the voltage effective value of the pixel capacity and the positive polarity and negative polarity writing at the same gray level are equal to each other, the voltage LCcom of the common electrode 108, the voltage V _C is the amplitude reference of the data signal May be set slightly lower.

In the embodiment, the vertical scanning direction is the downward direction of G1 → G864 and the horizontal scanning direction is the right direction of S1 → S1152. However, in order to cope with the case of a projector or a rotatable display device described later. In addition, the scanning direction may be switched.
Furthermore, instead of the normally white mode in which white display is performed when the effective voltage value of the pixel capacitance is small, a normally black mode in which black display is performed may be used.

In the above-described embodiment, the TN type is used as the liquid crystal. However, a bistable type having a memory property such as a BTN (Bi-stable Twisted Nematic) type or a ferroelectric type, a polymer dispersed type, or a molecular length A dye (guest) having anisotropy in the absorption of visible light in the axial direction and the minor axis direction is dissolved in a liquid crystal (host) having a certain molecular arrangement, and the dye molecule is arranged in parallel with the liquid crystal molecule (GH) A guest-host type liquid crystal may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure.
Further, in the present invention, the electro-optical material is not limited to liquid crystal, and thus, the present invention can be applied to various liquid crystal and alignment methods.
Although the liquid crystal device has been described so far, in the present invention, for example, EL (Electronic Luminescence) may be used as long as image data (video signal) is supplied to the image signal line 171 and sampled on the data line 114. ) It is also applicable to a device using an element, an electron emitting element, an electrophoretic element, a digital mirror element, or a plasma display.

Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described.
FIG. 8 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and images corresponding to the R, G, and B colors supplied from the processing circuit (not shown in FIG. 8). Each is driven by a signal. In other words, the projector 2100 has a configuration in which three sets of electro-optical devices including the display panel 100 are provided corresponding to the R, G, and B colors.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

  In addition to the electronic devices described with reference to FIG. 8, the electronic devices include televisions, viewfinder type / monitor direct-view type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, televisions. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the sample & hold circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows another example of the sample & hold circuit. It is a figure which shows the structure of the projector to which the same electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Display panel, 105 ... Liquid crystal, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 130 ... Scan line drive circuit, 140 ... Sampling signal output circuit, 150 ... Sample & Hold circuit, 152 ... Sampling circuit, 156 ... Amplifier circuit, 1562, 1564 ... TFT, 2100 ... Projector

Claims (6)

A plurality of pixels provided corresponding to the plurality of scanning lines and the plurality of data lines;
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
An image signal line to which a data signal having a voltage corresponding to the gradation of the pixel corresponding to the scanning line selected by the scanning line driving circuit is supplied;
A sampling signal output circuit that sequentially outputs sampling signals in a predetermined order;
A sampling circuit which is provided corresponding to each of the plurality of data lines and samples the data signal supplied to the image signal line according to the sampling signal;
Each of the data lines is provided corresponding to each of the plurality of data lines, holds the voltage of the data signal sampled by the sampling circuit, and amplifies the held voltage at an amplification factor with reference to a predetermined potential. An electro-optical device comprising: an amplifier circuit for supplying to the line. The electro-optical device according to claim 1, wherein the sampling circuit is an n-channel or p-channel transistor. The electro-optical device according to claim 1, wherein the sampling circuit includes n and p-channel transistors connected in parallel. The amplifier circuit has n and p channel transistors connected in series, and the data signal sampled by the sampling circuit is commonly input to the gates of both transistors, and the drains of both transistors are commonly connected. The electro-optical device according to claim 1, wherein the electro-optical device is connected to the data line. A method for driving an electro-optical device having a plurality of pixels provided corresponding to a plurality of scanning lines and a plurality of data lines,
Selecting the plurality of scanning lines in a predetermined order;
A voltage data signal corresponding to the gradation of the pixel corresponding to the selected scanning line is supplied to a predetermined image signal line;
In a period for selecting the scanning line, a sampling signal is sequentially output in a predetermined order,
Sampling the data signal supplied to the image signal line according to the sampling signal,
A method for driving an electro-optical device, which holds a voltage of a sampled data signal, amplifies the held voltage with an amplification factor based on a predetermined potential, and supplies the amplified voltage to the data line.   An electronic apparatus comprising the electro-optical device according to claim 1.

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