JP2006227468A - Opto-electronic apparatus and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus for preventing the lowering of display quality by accurately controlling the output timing of sampling signals so as not to be delayed from the supply timing of image signals, and to provide an electronic apparatus. <P>SOLUTION: A panel 100 is provided with a scanning line driving circuit which selects scanning lines in a prescribed order, a shift register which generates pulse signals by transferring a transfer start pulse DX supplied through a first control line 141 in accordance with a clock signal CLX, an AND circuit which generates sampling signals based on the pulse signals and an enable signal Enb supplied through a second control line 145, a sampling circuit which samples data signals Vid1 to Vid6 for data lines in accordance with the sampling signals and a detection circuit which detects delay time of the sampling signals with respect to the data signals. A scanning control circuit 212 conducts control so that generation timing of the sampling signals becomes quicker as the detected delay timing becomes longer and adds resistors R<SB>1</SB>(R<SB>2</SB>) and capacitors C<SB>1</SB>(C<SB>2</SB>) so that the time constants of the lines 141 and 145 are mutually matched with each other in an approximate manner. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a technique for preventing deterioration in display quality caused by sampling a data signal at a delayed timing.

In recent years, a projector that forms a reduced image by a display panel such as a liquid crystal and enlarges and projects the reduced image on a screen, a wall surface, or the like by an optical system is becoming popular.
The projector does not have a function of creating an image by itself, and is supplied with image data (also referred to as video data or video signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical scanning and horizontal scanning of the pixels arranged in a matrix, so that the panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the panel used for the projector, the scanning lines are selected in a predetermined order, while the data lines are sequentially selected over a period (one horizontal scanning period) in which one row of scanning lines is selected, and the image signal A dot sequential method is generally used in which a data signal supplied to a line is sampled on a selected data line. Here, the data signal is a signal obtained by converting image data so as to be suitable for driving a liquid crystal.

Recently, a method called phase expansion driving has been devised in order to cope with the high definition of a display image such as high definition. This phase expansion drive method is used in one horizontal scanning period.
A predetermined number of data lines, for example, six, are selected as a block at the same time, and the image signal to the pixel corresponding to the intersection of the selected scanning line and the selected data line is expanded six times with respect to the time axis. Thus, sampling is performed on each of the six data lines corresponding to the selected block. There is no difference in that the data signal is sampled on the data line regardless of the point sequential type or the phase expansion driving type.

Here, the data line is selected by the sampling signal. Specifically, a sampling switch is provided between the image signal line and each data line, and the data signal is sampled on the data line when the sampling switch is turned on according to the sampling signal. .
On the other hand, in the panel itself, since transistors, various wirings, and the like are formed on a substrate such as glass, capacitance and the like are parasitic on various signal lines and control lines, and signal delay is likely to occur. Particularly, since the sampling signal passes through various elements such as a shift register, the delay tends to be accumulated.
On the other hand, the image signal is directly supplied from the host device without passing through various elements like the sampling signal. For this reason, a state in which the sampling signal is delayed with respect to the supply timing of the image signal is likely to occur. When this state occurs, a data signal to be sampled on a certain data line is not correctly sampled, so that a so-called ghost is generated and display quality is deteriorated.

Therefore, in recent years, the delay amount of the data signal sampled with the sampling signal is detected by the panel with respect to the supply timing of the data signal, and the delay amount is fed back so as not to be delayed with respect to the supply timing of the image signal. A technique for controlling the output timing of a sampling signal has been proposed (see Patent Document 1).
Japanese Patent Laid-Open No. 11-119746

However, in the above technique, in theory, the output timing of the sampling signal could not be accurately controlled in practice.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to display the display quality by accurately controlling the output timing of the sampling signal so as not to be delayed with respect to the supply timing of the image signal. It is an object of the present invention to provide an image processing apparatus and an electronic apparatus that can prevent the deterioration.

In order to achieve the above object, the present invention is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and data sampled on the data lines when the scanning lines and the data lines are selected. A pixel to which a signal is supplied, and a scanning line driving circuit that selects the scanning lines in a predetermined order;
A shift register that generates a pulse signal for selecting the data line over a period during which the scanning line is selected by transferring a pulse supplied via a predetermined first control line according to a predetermined clock signal And a logic circuit that generates a sampling signal based on a pulse signal generated by each of the shift registers and an enable signal supplied via a predetermined second control line, and supplied via a predetermined image signal line A sampling circuit for sampling the data signal to be recorded on the data line according to the sampling signal, and a delay time of the sampling signal with respect to the data signal supplied via the image signal line is supplied to the first control line Detection circuit that detects by inputting a pulse and a long delay time That As, and a control circuit for controlling as generation timing of the sampling signal is accelerated, characterized in that substantially aligned with each other a time constant of said first and second control lines.
Here, in the present invention, a resistance value is inserted in the first control line, a capacitance is added between the first control line and a predetermined potential line, and a resistance value is inserted in the second control line. Preferably, a capacitance is added between the second control line and the predetermined potential line, or a combination thereof is used to make the time constants of the first and second control lines substantially coincide with each other. .
In addition, the electronic apparatus according to the present invention preferably includes the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed circuit board.
The panel 100 is connected by an FPC (Flexible Printed Circuit) substrate or the like.
The processing circuit 50 includes a data signal supply circuit 300, a scan control circuit 212, and a phase comparator 2.
14, of which the data signal supply circuit 300 further includes an S / P conversion circuit 31.
0, a D / A conversion circuit group 320, and an amplification / inversion circuit 330.
The S / P conversion circuit 310 is synchronized with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK, distributes digital image data Vid supplied from a host device (not shown) to six channels, and The image data is expanded six times on the time axis (also referred to as phase expansion or serial-parallel conversion) and output as image data Vd1d to Vd6d. For convenience of explanation, the image data Vd1d to Vd6d may be referred to as channels 1 to 6, respectively.

Here, the image data Vid is data that designates the brightness of the pixel by a gradation value in the horizontal effective display period, and designates the pixel to the lowest gradation (black) in the horizontal blanking period. Note that the reason why the pixel is designated as the lowest gradation in the horizontal blanking period is that the pixel is not contributed to the display even if it is supplied to the pixel due to timing shift or the like. Also, the image data Vi
The reason why d is converted from serial to parallel is to increase the time during which a data signal is applied in a sampling switch to be described later to ensure the sample and hold time and charge / discharge time.

The D / A converter circuit group 320 is an aggregate of D / A converters provided for each channel,
The phase-developed image data Vd1d to Vd6d are converted into analog signals having voltages corresponding to the gradation values.
The amplification / inversion circuit 330 performs normal rotation or polarity inversion on the analog-converted signal with reference to the voltage Vc, and supplies the signal to the panel 100 as data signals Vid1 to Vid6.
For polarity inversion, (a) every scanning line, (b) every data signal, (c) every pixel, (d) surface (
There are various modes such as every frame). In this embodiment, (a) polarity inversion for each scanning line is assumed. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the image signal as shown in FIG. In the present embodiment, for convenience, a higher voltage than the amplitude center voltage Vc is referred to as positive polarity, and a lower voltage is referred to as negative polarity. In this embodiment, the image data Vid is converted to analog after serial-parallel conversion, but of course, analog conversion may be performed before serial-parallel conversion.

Here, for convenience, the configuration of the panel 100 will be described. The panel 100 forms a predetermined image by the electro-optical change of the liquid crystal, and FIG. 2 is a block diagram showing the electrical configuration of the panel 100. FIG. 3 is a diagram illustrating a detailed configuration of the pixels of the panel 100.
As shown in FIG. 2, in the panel 100, a plurality of scanning lines 112 are arranged in the horizontal direction (X direction).
On the other hand, a plurality of data lines 114 are extended in the vertical direction (Y direction) in the figure. Then, the pixels 110 are provided so as to correspond to the intersections of the scanning lines 112 and the data lines 114, respectively, thereby constituting the display area 100a.
In the present embodiment, the number of scanning lines 112 (number of rows) is “m” and the number of data lines (number of columns).
Is assumed to be “6n” (a multiple of 6), and the pixel 110 is assumed to be arranged in a matrix of m rows × 6n columns.

The six image signal lines 171 have data signals Vid1 to Vi by the amplification / inversion circuit 330.
d6 is supplied respectively.
The sampling circuit 150 includes a sampling switch 15 provided for each data line 114.
Each sampling switch 151 is for sampling each of the data signals Vid1 to Vid6 supplied to the image signal line 171 to the corresponding data line 114.
In this embodiment, each sampling switch 151 is an n-channel thin film transistor (hereinafter referred to as TFT), and its drain is connected to the data line 11.
On the other hand, the gates are connected in common with six data lines 114 as one unit.

Here, the data line 114 to which the gates of the sampling switches 151 are commonly connected is considered as one block. When such a block is considered, the sampling switch 151 whose drain is connected to one end of the data line 114 in the j-th column from the left in FIG. 2 has a remainder obtained by dividing j by 6 as “1”. If so, the source is the data signal Vi
It is connected to the image signal line 171 supplied with d1. Similarly, the remainder when j is divided by 6 is “2”.
, “3”, “4”, “5”, “0”, each of the sampling switches 151 whose drains are connected to the image signal lines to which the data signals Vid2 to Vid6 are supplied. 171, respectively. For example, in FIG.
The source of the sampling switch 151 whose drain is connected to the data line 114 in the first column is “5” when “11” is divided by 6 and thus connected to the image signal line 171 to which the data signal Vid5 is supplied. Is done. Note that “j” here is for generalizing the data line 114 and is a positive integer satisfying 1 ≦ j ≦ 6n.

As shown in FIG. 4, the scanning line driving circuit 130 takes in the transfer start pulse DY supplied at the beginning of the vertical effective display period at the timing when the level of the clock signal CLY changes (rises or falls) and sequentially. The signals are shifted and exclusively output sequentially as scanning signals G1, G2,..., Gm that become H level only during the horizontal scanning period (1H). Note that the details of the scanning line driving circuit 130 are not directly related to the present invention, and thus are omitted.

In FIG. 2, the block selection circuit 140 includes a shift register 142 and n AND circuits 146.
Among these, the shift register 142 includes n latch circuits 143 that latch and output an input signal each time the level of the clock signal CLX transitions (rising and falling). The n latch circuits 143 in the shift register 142 are cascaded so that the output signal of a latch circuit at a certain stage becomes the input signal of the latch circuit at the next stage, except for the first stage and the last stage. Here, pulse signals that are outputs of the latch circuit 143 of 1, 2,..., (N−1) and the n-th stage are Sa1, Sa2,..., Sa (n−1), and San, respectively.

The first stage latch circuit 143 is supplied with a transfer start pulse DX that becomes H level at the beginning of one horizontal effective display period as an input signal through the first control line 141.
Although not shown in the figure for the configuration of the latch circuit 143 in each stage, the first clocked inverter that clocks the input signal with one of the clock signal CLX or its inverted signal,
An inverter that re-inverts the output, a second clocked inverter that clocks the output of the inverter with the clock signal CLX or the other of the inverted signals, and the like. For this reason, with respect to the latch circuit 143 at each stage, two of the first clocked inverter and the inverter are interposed from the input to the output.

An AND circuit (logic circuit) 146 is provided at each output stage of the latch circuit 143, respectively.
The output signal from the output stage and the enable signal En supplied via the second control line 145
A logical product signal with b is obtained and output as a sampling signal. Here, sampling signals obtained from the pulse signals Sa1, Sa2,..., Sa (n-1), San and the enable signal Enb are denoted as S1, S2,..., S (n-1), Sn, respectively. .
As shown in FIG. 5, the enable signal Enb is generated so that the pulse width at which the level is H becomes narrower than the half cycle of the clock signal CLX. Therefore, the pulse signals Sa1, Sa2,..., Sa (n−1), San generated by the shift register 142 are used as the enable signal Enb.
, The pulse width is narrowed and output as sampling signals S1, S2, S3,..., Sn.

These sampling signals S1, S2, S3,..., Sn are commonly supplied to the gates of the sampling switches corresponding to the data lines 114 that are blocked in FIG. For example, since the second block from the left corresponds to the data lines 114 in the seventh column to the twelfth column, the sampling signal S2 is commonly used for the gates of the sampling switches 151 corresponding to these data lines 114. Supplied.
Note that the TFT constituting the sampling switch 151 is an n-channel type in this embodiment, but may be a p-channel type or a complementary type combining both channels.

The dummy circuit 160 includes a clocked inverter 163, an inverter 164, an AND circuit 166, and a TFT 168. The first clocked inverter in the latch circuit 143, the inverter, the AND circuit 146, the sampling switch 151, Are simulated. For this reason, the transfer start pulse DX is also supplied as a clock signal of the clocked inverter 163, while an H level signal is always supplied to one input terminal of the AND circuit 166 and the source of the TFT 168, respectively. An output signal of the AND circuit 166 is supplied to the gate of the TFT 168.
Therefore, in the dummy circuit 160, the response characteristics from the generation of the pulse signal of the latch circuit 143 to the sampling of the data signals Vid1 to Vid6 (any one) supplied to the image signal line 171 are simulated. . Here, the signal DXb output from the drain of the TFT 168 is used.

Next, the pixel 110 will be described.
As shown in FIG. 3, in the pixel 110, the source of the n-channel TFT 116 is connected to the data line 114 and the drain is connected to the pixel electrode 118.
A gate is connected to the scanning line 112.
Further, the counter electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118, and is maintained at a constant voltage LCcom. A liquid crystal layer 105 is sandwiched between the pixel electrode 118 and the counter electrode 108. Therefore, for each pixel, the pixel electrode 1
18, a liquid crystal capacitor composed of the counter electrode 108 and the liquid crystal layer 105 is formed.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the voltage effective value applied to the liquid crystal layer 105 is zero, the light passing between the pixel electrode 118 and the counter electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, if the voltage effective value is close to zero, the light transmittance is While the maximum is white display, the amount of transmitted light decreases as the effective voltage value increases, and finally black display with the minimum transmittance is obtained (normally white mode).
In addition, a storage capacitor 109 is formed for each pixel in order to make it difficult for charge to leak in the liquid crystal capacitor. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), while the other end is, for example, the lower potential Vss of the power supply over all the pixels.
Common ground.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to the scanning line driving circuit 130, the shift register 142, the AND circuit 146, and the constituent elements of the sampling switch 151, and contributes to downsizing and cost reduction of the entire device. is doing.

The description returns to FIG. 1 again. The scanning control circuit 212 generates the transfer start pulse DX and the clock signal CLX from the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK supplied from the host device, and controls the horizontal scanning of the block selection circuit 140. At the same time, a transfer start pulse DY and a clock signal CLY are generated to control vertical scanning by the scanning line driving circuit 130. At this time, the scanning control circuit 212 supplies the transfer start pulse DX to the first control line 141.
In addition, the scanning control circuit 212 becomes L level in a transient period including the timing at which the logic level of the clock signal CLX changes, and in other periods, that is, the clock signal CL.
Enable signal Enb which becomes H level during the period when the logic level of X is stable (see FIG. 5)
Is generated in synchronization with the clock signal CLX and supplied to the second control line 145.
Note that the scan control circuit 212 also controls the phase expansion operation and the polarity inversion operation in the data signal supply circuit 300 in accordance with the control of the vertical scan and the horizontal scan.

The phase comparator (detection circuit) 214 compares the phase of the transfer start pulse DX generated by the scan control circuit 212 with the signal DXb returned from the panel 100, and transfers the transfer start pulse D.
Data Pd indicating how much the pulse DXa is delayed with respect to X is generated and supplied to the scanning control circuit 212.

Next, the operation of the electro-optical device will be described. First, sampling signals S1, S2,...
, S (n−1), Sn will be described in an ideal state where the data signals Vid1 to Vid6 are not delayed.
FIG. 4 is a timing chart for explaining the vertical scanning, FIG. 5 is a timing chart for explaining the horizontal scanning, and FIG. 6 shows the display operation of the electro-optical device over a continuous horizontal scanning period. It is a figure which shows the example of the voltage waveform of the data signal supplied.
At the beginning of the vertical effective display period, the transfer start pulse DY is supplied to the scanning line driving circuit 130. By this supply, as shown in FIG. 5, the scanning signals G1, G2, G3,.
Since m sequentially becomes H level exclusively and is output to each scanning line 112, here, attention is first focused on the horizontal scanning period in which the scanning signal G1 is H level. In this horizontal scanning period, positive writing is performed.

The horizontal scanning period is divided into a horizontal blanking period and a subsequent horizontal display period. In the horizontal effective display period, the image data Vid supplied in synchronization with the horizontal scanning is first distributed to 6 channels by the S / P conversion circuit 310 and expanded six times with respect to the time axis. Secondly, the distributed and expanded image data Vd1d to Vd1d are converted into analog signals by the D / A converter circuit group 320, and thirdly, the amplifier / inverter circuit 330 supports positive writing. The output is outputted with normal rotation based on the voltage Vc. For this reason, the voltage of the data signals Vid1 to Vid6 by the amplifying / inverting circuit 330 is such that the darker the pixel, the voltage Vid
Higher than c.

On the other hand, in the horizontal effective display period in which the scanning signal G1 is at the H level, as shown in FIG.
The signals Sa1, Sa2,..., Sa (n-1), San are sequentially set to the H level exclusively. .., Sa (n−1), San in these signals Sa1, n2, and San are narrowed by the enable signal Enb, and the sampling signals S1, S2,.
n-1) and output as Sn.

Now, in the horizontal effective scanning period in which the scanning signal G1 is at the H level, the sampling signal S
When 1 becomes H level, the corresponding data signals Vid1 to Vid6 are sampled on the six data lines 114 belonging to the first block from the left. The sampled data signals Vid1 to Vid6 are the pixels of the crossing lines of the scanning lines 112 in the first row counted from the top in FIG. 2 and the six data lines 114 (1st to 6th columns counted from the left). Each is applied to the pixel electrode 118.
Thereafter, when the sampling signal S2 becomes H level, the data signals Vid1 to Vid6 are sampled on the six data lines 114 belonging to the second block, respectively, and these data signals Vid1 to Vid6 are 1 This is applied to the pixel electrode 118 of the pixel that intersects the scanning line 112 in the row and the six data lines 114 (seventh to twelfth columns from the left).

Similarly, when the sampling signals S3, S4,..., Sn sequentially become H level,
Corresponding data signals Vid1 to Vid6 are sampled on the six data lines 114 belonging to the third, fourth,..., Nth block, and these data signals Vi.
d1 to Vid6 are respectively applied to the pixel electrodes 118 of the pixels intersecting with the scanning line 112 in the first row and the six data lines 114. As a result, writing to all the pixels in the first row is completed.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, in this horizontal effective display period,
Negative polarity writing is performed.
On the other hand, the image data Vid designates the blackening of the pixel in the horizontal blanking period, but since the positive writing was performed in the immediately preceding horizontal effective display period, the data signals Vid1 to Vid6 are as shown in FIG. At the approximate center timing of the horizontal blanking period, when applied to the pixel electrode 118 of the pixel 110, the pixel is made the black of the lowest gradation from the positive voltage Vb (+) that makes the pixel the black of the lowest gradation. It switches to the negative polarity voltage Vb (-).
Note that the relationship between the voltages in FIG. 6 is as follows. The voltages Vw (−) and Vg (−)
This is a negative voltage that, when applied to the pixel electrode 118 at 0, causes the pixel to have the highest gradation white and the intermediate gradation gray, respectively. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the electrode 118 in the pixel 110, cause the pixel to have the highest gradation white and the intermediate gradation gray, respectively. Vc (−) and Vg (−) are symmetrical with respect to Vc. In addition, regarding the voltage relationship of the scanning signals G1, G2, G3,..., Gm, the L level is a potential Vss (power supply voltage lower side) lower than the voltage Vb (−), and the H level of the scanning signal is the voltage Vb. The potential Vdd is higher than (+) (the higher power supply voltage side) (both not shown).

The operation in the horizontal effective display period in which the scanning signal G2 is at the H level is the same as the horizontal effective display period in which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Thus, writing to all the pixels in the second row is completed.
However, since the horizontal effective display period in which the scanning signal G2 is at the H level is negative polarity writing, the amplifying / inverting circuit 330 distributes the signal distributed to the six channels and expanded six times with respect to the time axis. Corresponding to negative polarity writing, the voltage Vc is inverted and output. For this reason, the data signal V
As shown in FIG. 6, the voltages of id1 to Vid6 become lower than the voltage Vc as the pixel is darkened.

In the same manner, the scanning signals G3, G4,..., Gm become H level, and the third row, fourth row
Writing is performed on the pixels in the row,..., The m-th row. As a result, the positive polarity writing is performed for the pixels in the odd-numbered rows, and the negative polarity writing is performed for the pixels in the even-numbered rows. In this one vertical scanning period, the first to m-th rows are performed. Writing is completed over all the pixels in the row.
Note that the data signals Vid to Vid6 are supplied from the voltage Vb (+) when shifting from the horizontal effective display period of positive polarity writing to the horizontal effective display period of negative polarity writing at substantially the center timing of the horizontal blanking period. When shifting from the horizontal effective display period for negative polarity writing to the horizontal effective display period for positive polarity writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, the writing polarity for the pixels is changed every vertical scanning period, so that the liquid crystal layer 1
No direct current component is applied to 05, and deterioration of the liquid crystal layer 105 is prevented.

By the way, the processing circuit 50 (scanning control circuit 212) initially has the data signals Vid1 to Vi.
d6, the clock signal CLX, and the enable signal Enb are output at the same timing.
On the other hand, in the panel 100, since the wiring and the like are formed on the glass substrate, the resistivity and the parasitic capacitance are larger than those of the FPC substrate. Further, in the panel 100, the clock signal CLX,
The enable signal Enb and the data signals Vid1 to Vid6 have different supply paths. For this reason, even if the timing coincides at the time of input in the panel 100, the clock signal CLX with respect to the supply timing of the data signals Vid1 to Vid6 in the panel 100.
And the enable signal Enb tends to be delayed. Further, when the data signal is sampled on the data line 114, the delay of each part is accumulated because the data passes through the shift register 142, the AND circuit 146, and the sampling switch 151.
If the delay of the clock signal CLX or the enable signal Enb occurs with respect to the supply timing of the data signals Vid1 to Vid6 in the panel 100, the sampling signals S1, S2,..., S (n-1), Sn Since there is a delay from the normal timing shown in FIG. 5, after the data signal corresponding to the original pixel is sampled on the data line 114, the data signal corresponding to a different pixel may be sampled. If a data signal corresponding to a different pixel is sampled, a so-called ghost or the like is generated and the display quality is significantly lowered.

For this reason, in this embodiment, the dummy circuit 160 simulates the path from when the transfer start pulse DX is transferred to when the data signal is sampled on the data line 114 according to the sampling signal, and also simulates the sampling. While the output signal DXb is output, the transfer start pulse D output to the panel 100 in the phase comparator 214
X is compared with the signal DXb, and the signal DX with respect to the transfer start pulse DX is compared.
The delay amount of b is detected. Then, the scan control circuit 212 advances the phases of the transfer start pulse DX, the clock signal CLX, and the enable signal Enb from the beginning, and the phase comparator 21
The delay amount detected in 4 is eliminated.
Thus, even if a delay occurs in the panel 100, the data signals Vid1 to Vi
Sampling signals S1, S2,..., S (n−1), Sn with respect to the supply timing of d6
Since the output timing is controlled so as not to be delayed, deterioration of display quality should be prevented.

Here, in FIG. 1, a description will be given of a point that a resistor and a capacitor are connected to the first control line 141 and the second control line 145, respectively.
First, in the present embodiment, the reason why the transfer start pulse DX is input to the dummy circuit 160 is because the transfer start pulse DX is a signal having an appropriate cycle among various signals. On the other hand, it is the enable signal Enb that determines the phases of the sampling signals S1, S2, ..., S (n-1), Sn.
Therefore, ideally, it is desirable to supply the enable signal Enb to the dummy circuit 160 and detect the delay. However, the enable signal Enb has a higher frequency than the transfer start pulse DX, and when the second control line 145 is connected to the dummy circuit 160, the response characteristic changes, and the waveform of the sampling signal is directly changed. The effect will appear. For this reason, the configuration for supplying the enable signal Enb to the dummy circuit 160 is not realistic.

In addition, except for the dummy circuit 160, the first control line 141 to which the transfer start pulse DX is supplied.
Is only input to the latch circuit 143 in the first stage, whereas the second control line 145 to which the enable signal Enb is supplied is connected to one of the input ends of the AND circuit 146, respectively.
Since there are n AND circuits 146 corresponding to each block, there are n AND circuits. Further, the AND circuit 146 is composed of a NAND circuit composed of four transistors and a NOT circuit composed of two transistors, considering a negative logic complementary element. One AND circuit 1
The input terminal 46 means the gates of two transistors among the four transistors constituting the NAND circuit. For this reason, the gates of 2n transistors are connected to the second control line 145, and the load capacitance is larger than that of the first control line 141.
As described above, in the panel 100, the first control line 141 and the second control line 145 have different response characteristics because they have different load capacitances as well as input resistances. Therefore, even if the transfer start pulse DX is supplied to the dummy circuit 160, the response characteristic of the enable signal Enb is not accurately simulated. In this respect, the data signals Vid1 to Vid6
It is considered that the phases of the sampling signals S1, S2,..., S (n-1), Sn cannot be precisely controlled.

Therefore, in this embodiment, as shown in FIG. 1, in the middle of the path to the processing circuit 50 to the panel 100, the resistor R ₁ with interposing the first control line 141, the capacitance C ₁
Is added to a signal line having a constant potential (for example, Vss), and the time constant indicated by the product of the resistance and the capacitance in the first control line 141 is substantially matched with the time constant of the second control line 145. It is said.
Therefore, according to the present embodiment, the response characteristics of the first control line 141 and the second control line 145,
In particular, since the delay amounts substantially coincide, the data signal Vid1 is obtained by comparing the phase of the signal DXb obtained by passing the transfer start pulse DX through the dummy circuit 160 and the transfer start pulse DX.
~ Vid6 can be sampled on the corresponding data line 114 at a more appropriate timing.

In the first control line 141, the time constant increases. As described above, the transfer start pulse DX is only input to the dummy circuit 160 and the first-stage latch circuit 143.
Since the output of the shift register 142 is defined by the clock signal CLX, even if the phase is slightly delayed, the display image is hardly affected.

In the configuration described above, the time constant of the first control line 141, for substantially match the time constant of the second control line 145, by adding a capacitor C ₁ with interposing a resistor R ₁ to the first control line 141 but also to the second control line 145, as indicated by a broken line in FIG. 1, by adding the capacitor C ₂ with interposing the resistor R _2, the time constant of the two control lines consequently so as to coincide May be. However, when the capacitor C ₂ is added to the second control line 145, the response (the waveform is also affected) of the enable signal Enb is affected. Therefore, the value of the capacitor C ₂ should be as small as possible.
Note that the point of providing a resistor _R 1 _{(R 2)} and the capacitor _C 1 _{(C 2),} the processing circuit 5
FPC that connects 0 and the panel 100 may be used, may be in the module of the processing circuit 50, may be in the panel 100, or may be distributed in these places. In the configuration of the present embodiment, as long as the time constants of the first control line 141 and the second control line 145 coincide with each other as a result, it may be anywhere. Therefore, depending on the panel 100, the resistor R ₁ (R ₂ ) or the capacitor C ₁ (C
There may be only one of ₂ ).

In the embodiment described above, the image data Vid is converted into the image data Vd1d of 6 channels.
Although it is configured to expand to Vd6d, the number of channels to be expanded is not limited to “6”. Further, the configuration is not limited to the phase expansion, and a dot sequential method may be used.
On the other hand, in the above-described embodiment, the data signal supply circuit 300 processes the digital image signal Vid. However, the data signal supply circuit 300 may be configured to process an analog image signal. Further, in the data signal supply circuit 300, the analog conversion is performed after the S / P expansion. However, if the final output is the same analog signal, the S / P expansion may be performed after the analog conversion. .

Furthermore, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the counter electrode 108 and the pixel electrode 118 is small. However, the normally black mode in which black display is performed may be used. good.
In the above-described embodiment, the TN type is used as the liquid crystal, but BTN (Bi-stable Twisted Ne) is used.
matic) and ferroelectric types such as bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the long and short axis directions of molecules (guests) ) May be dissolved in a liquid crystal (host) having a certain molecular arrangement, and a GH (guest host) type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.
The liquid crystal device has been described so far. In the present invention, image data (video signal) is used.
Can be supplied via the image signal line 171, for example, EL (Electronic Lumines)
cence) element, LCOS (Liquid Crystal On Silicon), electron emission element, electrophoresis element,
The present invention can also be applied to an apparatus using a digital mirror element or the like, or a plasma display.

<Electronic equipment>
Next, a projector using the panel 100 described above as a light valve will be described as an example of an electronic apparatus using the electro-optical device according to the embodiment described above.
FIG. 7 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 includes a lamp unit 21 made of a white light source such as a halogen lamp.
02 is provided. The projection light emitted from the lamp unit 2102 is R (by the three mirrors 2106 and two dichroic mirrors 2108 arranged inside.
The light valve 100 is divided into three primary colors of red, G (green), and B (blue), and corresponds to each primary color.
Guided to R, 100G and 100B, respectively. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the panel 100 in the above-described embodiment, and R, G, and N supplied from the processing circuit (not shown in FIG. 7).
It is driven by an image signal corresponding to each color of B.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight.
Therefore, after the images of the respective colors are combined, the projection lens 2114 is displayed on the screen 2120.
As a result, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, there is no need to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The left-right reversed image is displayed in the direction opposite to the horizontal scanning direction by the light valve 100G.

In addition to the electronic device described with reference to FIG. 7, the direct view type, for example, a mobile phone, personal computer, television, video camera monitor, car navigation device, pager, electronic notebook, calculator, word processor , Workstations, videophones, POS terminals, digital still cameras, devices equipped with touch panels, and the like. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. It is a figure which shows the structure of the panel in the same electro-optical apparatus. It is a figure which shows the structure of the pixel in the panel. 6 is a timing chart for explaining a display operation of the electro-optical device. 6 is a timing chart for explaining a display operation of the electro-optical device. FIG. 6 is a diagram for explaining a display operation of the electro-optical device. FIG. 2 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Panel, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 130 ... Scan line drive circuit, 140 ... Data line drive circuit, 141 ... First control line, 142 ... Shift register,
145 ... second control line, 146 ... AND circuit, 150 ... sampling circuit, 171 ... image signal line, 212 ... scanning control circuit, 214 ... phase comparator, 2100 ... projector

Claims (3)

A pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when a scanning line and a data line are selected, a pixel supplied with a sampled data signal;
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A shift register that generates a pulse signal for selecting the data line over a period during which the scanning line is selected by transferring a pulse supplied via a predetermined first control line according to a predetermined clock signal When,
A logic circuit that generates a sampling signal based on a pulse signal respectively generated by the shift register and an enable signal supplied via a predetermined second control line;
A sampling circuit for sampling a data signal supplied via a predetermined image signal line to the data line according to the sampling signal;
A detection circuit for detecting a delay time of the sampling signal with respect to a data signal supplied via the image signal line by inputting a pulse supplied to the first control line;
And a control circuit for controlling the generation timing of the sampling signal to be advanced as the detected delay time becomes longer, and the time constants of the first and second control lines are made to substantially coincide with each other. Electro-optic device. Inserting a resistance value in the first control line;
A capacitor is added between the first control line and a predetermined potential line;
Inserting a resistance value in the second control line;
A capacitor is added between the second control line and a predetermined potential line;
2. The electro-optical device according to claim 1, wherein the time constants of the first and second control lines are substantially matched to each other by any one of these or a combination thereof. An electronic apparatus comprising the electro-optical device according to claim 1.

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