JP2006267359A - Electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation in the optimum voltage of a common electrode by simple constitution. <P>SOLUTION: Pixels are arranged so as to correspond to intersections between a plurality of scanning lines and a plurality of data lines and include: an individual pixel electrode for each pixel; a common electrode common to each of the pixels; a pixel capacitor holding an electro-optical substance between the pixel electrode and the common electrode; and a TFT which is turned to a conductive state when the scanning line is selected and then writes voltage corresponding to a data signal supplied to the data line to the pixel capacitor. Where, a resistor element 56 is electrically connected between a voltage output circuit 54 for outputting voltage to be applied to the common electrode and the common electrode and a capacitor element 58 is electrically connected between the common electrode and ground potential Gnd. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for preventing deterioration of display quality in an electro-optical device.

In particular, in an electro-optical device that displays an image using an electro-optical material such as liquid crystal, the electro-optical material is driven with an alternating current in order to prevent deterioration of characteristics. For example, in an active matrix type liquid crystal device using a thin film transistor as a switching element, a substantially constant voltage is applied to a common electrode facing a plurality of pixel electrodes across the liquid crystal, while corresponding to the gradation of the pixel. A data signal having a voltage to be applied is periodically inverted in polarity with reference to a predetermined potential and then applied to each pixel electrode.

In such AC driving, if the effective voltage value applied to the electro-optic material differs between the case where the data signal is positive and higher than the reference potential, and the negative polarity which is lower than the reference potential, In addition to the occurrence of flicker in which the amount of emitted light periodically varies, a direct current component is applied as a result, resulting in deterioration of the electro-optical material. For this reason, when displaying an image, the optimum voltage of the common electrode (counter electrode) is set so that the periodic fluctuation amount of the amount of light emitted from the electro-optical device is minimized, that is, the flicker is minimized. The 1st technique which adjusts is proposed (for example, refer to patent documents 1).
In addition, since it is known that the optimum voltage of such a common electrode varies with time, the voltage applied to the common electrode according to the amount of charge charged to the counter substrate on the side where the common electrode is provided. A second technique for controlling the above has also been proposed (see, for example, Patent Document 2).
JP-A-8-286169 JP 2003-302648 A

However, since the first technique automatically adjusts the common electrode so that the flicker is minimized immediately after manufacturing, it cannot be handled during normal use after installation. In the second technique, the voltage applied to the common electrode is designated by digital data and converted to an analog voltage by a D / A converter.
The present invention has been made in view of such circumstances, and an object of the present invention is to cope with fluctuations in the optimum voltage of the common electrode, and to determine the effective voltage value applied to the liquid crystal with positive polarity and negative polarity. An object of the present invention is to provide an electro-optical device and an electronic apparatus in which application of flicker and a direct current component due to differences is prevented.

In order to achieve the above object, the present invention provides a plurality of pixels provided corresponding to intersections of a plurality of rows of scanning lines and a plurality of columns of data lines, and each pixel includes an individual pixel electrode and each pixel. A common electrode, a pixel including the pixel electrode and the common electrode, a voltage output circuit for outputting a voltage to be applied to the common electrode, and a resistor electrically interposed between the common electrode And an element. The resistance value of the resistance element in the present invention is desirably 1 kΩ or more.
If only the resistance element is inserted, the potential of the common electrode fluctuates due to the influence of the voltage change of the data signal. Therefore, in the present invention, between the common electrode and a predetermined potential line maintained at a constant potential. A configuration including a capacitive element electrically interposed between the two is preferable.
In the present invention, a scanning line driving circuit for selecting the scanning lines in a predetermined order and a data signal corresponding to the gradation of the pixel are supplied to the data lines for the pixels corresponding to the selected scanning lines. A configuration including a data line driving circuit may be employed. Further, the electronic apparatus may include the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed board, and is connected to the display panel 100 by an FPC (Flexible Printed Circuit) board or the like.

The processing circuit 50 further includes a data signal supply circuit 300, a scanning control circuit 52, a voltage output circuit 54, and the like. Among these, the data signal supply circuit 300 includes the S / P conversion circuit 320, D
/ A conversion circuit group 340 and amplification / inversion circuit 350 are included.
The S / P conversion circuit 320 is digital image data Vd supplied from a host device (not shown) in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK.
Are distributed to 6 channels, and each is expanded 6 times on the time axis (also referred to as phase expansion or serial-parallel conversion) and output as image data Vd1d to Vd6d. Here, the image data Vd is digital data that designates the gradation (brightness) of the pixel, and is designated as the lowest gradation (black) in the horizontal blanking period. The reason for designating the lowest gradation in the horizontal blanking period is that even if the pixel is supplied to the pixel mainly due to timing deviation,
This is because the pixel does not contribute to display. For convenience of explanation, the image data Vd1d to Vd6
d is referred to as channels 1 to 6, respectively.

The D / A converter circuit group 340 is an aggregate of D / A converters provided for each channel,
The image data Vd1d to Vd6d are converted into analog signals having voltages corresponding to the gradation values.
The amplifying / inverting circuit 350 performs normal rotation or polarity inversion on the analog-converted signal with reference to a voltage Vc described later, and supplies the signal to the display panel 100 as data signals Vid1 to Vid6.
For polarity inversion, (a) every scanning line, (b) every data line, (c) every pixel, (d) surface (
There are various modes such as every frame). In this embodiment, it is assumed that (a) polarity inversion is performed for each scanning line. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the image signal as shown in FIG. In the present embodiment, for the sake of convenience, the amplitude center voltage V V is applied to the data signals Vid1 to Vid6.
The higher side than c is referred to as positive polarity, and the lower side is referred to as negative polarity.
In the present embodiment, the image data Vd is converted to analog after serial-parallel conversion, but of course, analog conversion may be performed before serial-parallel conversion.

Here, for convenience, the configuration of the display panel 100 will be described. The display panel 100 forms a predetermined image by electro-optic change. FIG. 2 is a block diagram showing an electrical configuration of the display panel 100, and FIG. 3 is a diagram showing a detailed configuration of pixels of the display panel 100. The display panel 100 has a configuration in which an element substrate and a counter substrate on which a common electrode is formed are bonded together with a sealing material with a certain gap, and liquid crystal is sealed in the gap.
As shown in FIG. 2, in the display panel 100, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 (= 192 × 6) columns of data lines 114 in the figure Y ( It extends in the (vertical) direction. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, the pixel 110 is
In the present embodiment, they are arranged in a matrix of 864 rows × 1152 columns, but the present invention is not limited to this.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every six columns. For convenience of explanation, the first, second, third,..., 192th blocks from the left are denoted as B1, B2, B3,.

As for the detailed configuration of the pixel 110, as shown in FIG.
A thin film transistor (116) has a source connected to the data line 114, a drain connected to the pixel electrode 118, and a gate connected to the scanning line 112.
Further, the common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118 formed on the element substrate. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. For this reason, a pixel capacitor composed of the pixel electrode 118, the common electrode 108, and the liquid crystal 105 is formed for each pixel.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the effective voltage applied to the pixel capacitor is zero, the light passing between the pixel electrode 118 and the common electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the effective voltage value is As it increases, the liquid crystal molecules tilt in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, if the voltage effective value is close to zero, the average over the unit time The maximum light transmittance becomes white and the white display is achieved, while the amount of light transmitted decreases as the effective voltage value increases, and finally the black display with the minimum transmittance is obtained (normally white mode). .

Further, in order to reduce the influence of charge leakage from the pixel capacitor via the TFT 116 at the off time, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is
While connected to the pixel electrode 118 (the drain of the TFT 116), the other end is connected to the capacitor line 107 over all the pixels.
As shown in FIG. 2, the capacitor line 107 is common across the pixels 110, and is electrically connected to the common electrode 108 via the electrode 107a and conductive particles mixed in the sealing material. ing.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to a scanning line driving circuit 130, a block selection circuit 140, a sampling switch 151, and the like described below, and contributes to downsizing and cost reduction of the entire device. ing.

Subsequently, peripheral circuits such as the scanning line driving circuit 130 and the block selection circuit 140 are provided around the area where the pixels 110 are arranged. Among these, as shown in FIG. 4, the scanning line driving circuit 130 sequentially scans the scanning signal G that becomes H level exclusively over one horizontal scanning period.
1, G 2, G 3,..., G 864 are supplied to the scanning lines 112 in the first row, the second row, the third row,. The details of the scanning line driver circuit 130 are omitted because they are not directly related to the present invention, but are supplied at the beginning of one vertical scanning period (1F) and have a pulse width (H of about a half cycle of the clock signal CLY. The transfer start pulse DY having a level) is output as scanning signals G1, G2, G3,..., G864 in a form that is sequentially shifted every time the level of the clock signal CLY transitions (rises or falls), The display panel 100 is configured to perform vertical scanning.

Next, as shown in FIG. 4, the block selection circuit 140 is supplied with a transfer start pulse DX having a pulse width (H level) of about one cycle of the clock signal CLX while being supplied at the start of one horizontal scanning period. Each time the level of the clock signal CLX transitions, the signal is sequentially shifted, and the pulse width is narrowed and output as sampling signals S1, S2, S3,..., S192, and the display panel 100 is horizontally scanned.
The voltage corresponding to the H level of the scanning signal or sampling signal is the higher voltage Vdd of the power supply.
The voltage corresponding to the L level is the lower voltage Vss of the power supply, and this voltage Vss is the ground potential Gnd (voltage zero) (see FIG. 6 described later).

The sampling circuit 150 is an aggregate of sampling switches 151 provided corresponding to each of the data lines 114. Each sampling switch 151 is, for example, an n-channel TFT, and its drain is connected to the data line 114.
Here, the sampling signals corresponding to the blocks are commonly supplied to the gates of the six sampling switches 151 corresponding to the data lines 114 belonging to the same block. For example, the sampling signal S4 corresponding to the block B4 is commonly supplied to the gates of the six sampling switches 151 corresponding to the 19th to 24th data lines 114 belonging to the block B4.

The source of the sampling switch 151 is connected to the data signals Vid1 to Vi according to the following relationship.
It is connected to one of the six image signal lines 171 supplied with d6.
That is, in the sampling switch 151 whose drain is connected to one end of the data line 114 in the j-th column from the left in FIG. 2, if the remainder obtained by dividing j by 6 is “1”, the source is the data Similarly, it is connected to the image signal line 171 to which the signal Vid1 is supplied, and similarly to the data line 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0”. The sampling switch 151 to which the drain is connected has its source connected to the data signal Vid2.
Each is connected to an image signal line 171 supplied with Vid6. For example, in FIG. 2, the source of the sampling switch 151 whose drain is connected to the data line 114 in the 23rd column has a remainder of “5” obtained by dividing “23” by 6; Connected to the signal line 171. In addition, j is a code | symbol for demonstrating the row | line | column of the data line 114, and is 1 or more and 1152 or less integer in this embodiment.
Here, when a certain sampling signal becomes H level, the six sampling switches 151 of the block corresponding to the sampling signal are turned on, and the data signals Vid1 to Vid6 supplied to the image signal line 171 are supplied to the block. Sampling is performed on the data lines 114 belonging to six columns. For this reason, the block selection circuit 140 and the sampling circuit 150 constitute a data line driving circuit.

Returning to FIG. 1 again, the scanning control circuit 52 generates a transfer start pulse DX and a clock signal CLX from the dot clock signal DCLK, the vertical scanning signal Vs, and the horizontal scanning signal Hs supplied from the host device and blocks them. While controlling the horizontal scanning by the selection circuit 140, the transfer start pulse DY and the clock signal CLY are generated, and the scanning line driving circuit 13
This controls vertical scanning by zero. The scanning control circuit 52 controls the phase development in the S / P conversion circuit 320 described above in synchronization with the horizontal scanning and designates the writing polarity in the amplification / inversion circuit 350.
The voltage output circuit 54 supplies a voltage LCcom to be applied to the common electrode 108 (a saturation value V described later).
₁ ) generated and output. The resistor element 56 has one end connected to the voltage output circuit 54 and the other end connected to the capacitor line 107 in the display panel 100. Further, one end of the capacitive element 58 is connected to the capacitive line 107, and the other end is grounded to the potential Gnd.

Next, the operation of the electro-optical device 10 of this embodiment will be described. FIG. 4 is a timing chart showing vertical and horizontal scanning of the electro-optical device 10 according to the present embodiment.
It is a figure which shows the example of the voltage waveform of the data signal supplied over a continuous horizontal scanning period.
As described above, the scanning signals G1, G2, G3,..., G864 are sequentially and exclusively set to the H level for each horizontal scanning period by the scanning line driving circuit 130 as shown in FIG.
In each horizontal scanning period, image data Vd supplied in synchronization with the horizontal scanning is first changed to S /
In addition to being distributed to 6 channels by the P conversion circuit 320, it is expanded 6 times with respect to the time axis, and secondly, it is converted into an analog signal by the D / A conversion circuit group 340, respectively.
In addition, the analog signal is forwardly output with reference to the voltage Vc in the case of positive polarity writing by the amplification / inversion circuit 350, and inverted with respect to the voltage Vc in the case of negative polarity writing.

Here, in the horizontal scanning period in which the scanning signal G1 is at the H level, assuming that writing is performed with a positive polarity, the data signal V by the amplification / inversion circuit 350 in the horizontal scanning period.
The voltages id1 to Vid6 become higher than the voltage Vc as the pixels are darkened (see FIG. 5).
On the other hand, in the horizontal scanning period in which the scanning signal G1 is at the H level, the transfer start pulse DX is sequentially shifted by the block selection circuit 140, and the pulse width is narrowed, so that the sampling signals S1, S2, S3,. Is output.

In the horizontal scanning period in which the scanning signal G1 is at the H level, the TFT 116 of the pixel 110 located on the scanning line 112 in the first row is in a conductive (on) state between the source and the drain. On the other hand, when the sampling signal S1 becomes H level, the data signals Vid1 to Vid6 are sampled on the data lines 114 in the first to sixth columns belonging to the block B1, respectively. Therefore, the sampled data signals Vid1 to Vid6 are pixels that intersect the first scanning line 112 counted from the top in FIG. 2 and the six (first to sixth columns counted from the left) data lines 114. The pixel electrodes 118 are applied respectively.
After this, when the sampling signal S2 becomes H level, this time, it belongs to the block B2.
The data signals Vid1 to Vid6 are sampled on the data line 114 in the twelfth column, respectively, and these data signals Vid1 to Vid6 are connected to the scanning line 112 in the first row and the seventh to seventh data lines.
This is applied to the pixel electrode 118 of each pixel intersecting the twelfth column data line 114.

In the same manner, when the sampling signals S3, S4,..., S192 sequentially become H level exclusively, the data signals Vid1 to Vid6 correspond to the six columns of data lines 114 belonging to the blocks B3, B4,. Are sampled, and these data signals Vid1 to Vid6 are respectively applied to the pixel electrodes 118 of the pixels intersecting the scanning lines 112 in the first row and the data lines 114 in the six columns. As a result, writing to all the pixels in the first row is completed. After that, even if the scanning signal G1 becomes L level and the TFT 116 is turned off, the written voltage is held by the pixel capacitor or the storage capacitor 109.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, negative polarity writing is performed in this horizontal scanning period.
On the other hand, in the horizontal blanking period, the image data Vd designates the blackening of the pixel. However, since the positive writing is performed in the immediately preceding horizontal effective display period, the data signals Vid1 to Vid6 are as shown in FIG. At a substantially central timing of this horizontal blanking period, a negative electrode that, when applied to the pixel electrode 118, causes the pixel to have the lowest gradation black from the positive voltage Vb (+) that causes the pixel to have the lowest gradation black. Switched to the voltage Vb (-).
In addition, referring to the relationship of the voltages in FIG. 5, when the voltages Vw (−) and Vg (−) are applied to the pixel electrode 118, the pixel is set to the highest gradation white and the intermediate gradation gray, respectively. Negative voltage. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the pixel electrode 118, cause the pixel to have the highest gray level and the intermediate gray level, respectively.
When the voltage Vc is used as a reference, there is a symmetrical relationship with Vw (−) and Vg (−).

The operation in the horizontal scanning period in which the scanning signal G2 is at the H level is the same as the horizontal scanning period in which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Thus, writing to all the pixels in the second row is completed. However, since the horizontal scanning period in which the scanning signal G2 is at the H level is negative writing, the amplification / inversion circuit 350 applies the signal Vc distributed and expanded to 6 channels to the voltage Vc corresponding to the negative writing. Inverted with reference to output. For this reason, the voltage of the data signals Vid1 to Vid6 becomes lower than the voltage Vc as the pixels are darkened (see FIG. 5).

Similarly, the scanning signals G3, G4,..., G864 become the H level, the third row,
Writing is performed on the pixels in the fourth row,..., The 864th row. Thus, positive polarity writing is performed on the pixels in the odd-numbered rows, and negative polarity writing is performed on the pixels in the even-numbered rows. In this one vertical scanning period, the first to 864th rows are performed. Writing will be completed across all of the eye pixels.
The data signals Vid1 to Vid6 are substantially at the center timing of the horizontal blanking period.
When shifting from the horizontal effective display period of positive polarity writing to the horizontal effective display period of negative polarity writing, the voltage Vb (+) is changed to the voltage Vb (-), and the positive polarity is applied from the horizontal effective display period of negative polarity writing. When shifting to the horizontal effective display period of writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, since the writing polarity for the pixel is switched every vertical scanning period, the liquid crystal 1
No direct current component is applied to 05, and deterioration of the liquid crystal 105 is prevented.

Incidentally, the voltage LCcom applied to the common electrode 108 is a voltage Vc which is a reference for polarity inversion.
Is set to be lower. This is because the so-called sampling switch 151 is used.
This is because the influence of the push-down of TFTs constituting the TFT is taken into consideration. Briefly explaining this pushdown, when the gate voltage (sampling signal) of the sampling switch 151 which is a TFT changes from H level to L level (when turning from on to off),
This is a phenomenon in which the voltage held on the drain side decreases. The cause is a parasitic capacitance between the gate and the drain, and becomes more prominent as the source voltage is lower.

The effect of this pushdown is illustrated as a waveform. For example, in order to make a certain pixel gray, a voltage Vg (+) is written as a positive polarity writing in a certain vertical scanning period as a data signal, and then a voltage Vg (-) is written in a negative polarity in the next vertical scanning period. In the case where data is written as an error, the voltage waveform of the pixel electrode 118 in the pixel is as shown in FIG.
Specifically, the TFT 116 is turned on over one horizontal scanning period in which the pixel is selected, but the sampling switch 151 of the data line corresponding to the pixel is turned on only in the horizontal scanning period in which the block is selected. . In other words, the sampling switch 151 is turned off during the horizontal scanning period. For this reason, the data signal sampled on the data line 114 is affected by the push-down when the sampling switch 151 is turned off. Specifically, as shown in this figure, the push-down immediately after writing the negative gray equivalent voltage Vg (-) rather than the push-down PD immediately after writing the positive gray equivalent voltage Vg (+). ND is larger.

For this reason, when the voltage Vc, which is a reference for polarity inversion, is applied to the common electrode 108, the effective voltage of the liquid crystal capacitance is larger in negative polarity writing than in positive polarity writing. A direct current component is applied to. In order to avoid this, the voltage LCcom applied to the common electrode 108 is set to a lower side than the voltage Vc even when the pushdown amount differs in polarity (
(See FIG. 6). As a result, the effective voltage values applied to the liquid crystal capacitors are equalized.
Here, a voltage LCcom that makes the effective voltages of both polarities equal to each other when writing a voltage having a symmetrical relationship with respect to the voltage Vc in the positive polarity writing and the negative polarity writing is particularly set to the optimum voltage. Called.
In FIG. 6, a hatched region is a portion that contributes to the difference between the voltage of the pixel electrode 118 and the voltage LCcom of the common electrode 108, that is, the effective value of the voltage applied to the pixel capacitor.

As shown in FIG. 7, this optimum voltage varies with the passage of time since the start of display (power-on). Therefore, the voltage output circuit 54 may be configured to output the voltage LCcom while varying the elapsed time so as to match such an optimum voltage. However, this configuration requires a separate D / A converter or the like according to digital data, as described in the background art. Furthermore, since the optimum voltage varies not only with the elapsed time but also with other factors such as environmental temperature and humidity, the voltage LCcom is generated so as to match the optimum voltage that varies according to these various factors. Is difficult as a practical matter.

By the way, since the polarity of the data signal applied to the pixel electrode 118 is alternately switched,
Even if the voltage LCcom is not applied to the common electrode 108 (even if the common electrode 108 is set to a high impedance state), the common electrode 108 is a temporal average value of the voltage held in each pixel electrode 118, that is, near the optimum voltage. It becomes floating in the vicinity. However, in a state where no voltage is applied to the common electrode 108, the potential of the common electrode 108 varies finely in time due to the influence of the voltage change of the data signal, so that each pixel cannot maintain a predetermined gradation.

Therefore, in this embodiment, the output line of the voltage output circuit 54 is not directly connected to the common electrode 108 in the display panel 100 but is indirectly connected via the resistance element 56. As a result, the potential of the common electrode 108 is pulled by the voltage LCcom output by the voltage output circuit 54 in a state of floating near the optimum voltage.
In the present embodiment, the potential of the common electrode 108 is pulled to the voltage LCcom by the resistance element 56. However, since the potential of the common electrode 108 is likely to fluctuate only by the resistance element 56, the common electrode 108 and the ground potential Gnd. The capacitive element 58 is electrically inserted between the two. As a result, the potential of the common electrode 108 is stabilized near the optimum voltage while being pulled by the voltage LCcom.

Therefore, according to this embodiment, even without varying the voltage LCcom according to the voltage output circuit 54 elapsed time and environmental conditions, the voltage to be the saturation value V ₁ of the optimum voltage in FIG. 7 LCC
With a simple configuration that outputs om, it becomes possible to cope with fluctuations in the optimum voltage.
The purpose of the resistance element 56 is to make the input impedance of the common electrode 108 sufficiently high with respect to the output impedance of the voltage output circuit 54, and the resistance value varies depending on the size of the display panel 100. It is considered that it should be approximately 1 kΩ or more. The purpose of the capacitor element 58 is to smooth the potential of the common electrode 108 so that it does not fluctuate. Therefore, the capacitance value only needs to be large enough to achieve the above object. Also,
Since the connection destination of the other end of the capacitive element 58 only needs to be a constant potential, the capacitor 58 may be connected to the power supply line of the higher voltage Vdd of the power supply instead of being grounded to the potential Gnd.

In the above-described embodiment, the capacitor line 107 and the common electrode 108 are electrically connected to have the same potential. However, the capacitor line 107 is electrically separated to make the capacitor line 107 have a constant potential (for example, the power supply voltage Vdd,
Vss) may be adopted.
In addition, the resistor element 56 and the capacitor element 58 may be provided not on the processing circuit 50 but on the FPC board or in the display panel 100.
In the embodiment, the pixel electrode 118 is formed on the element substrate, while the common electrode 10 is formed on the counter substrate.
However, a so-called in-plane switching method may be employed in which both electrodes are formed on the element substrate and the direction of the electric field applied to the liquid crystal is the substrate surface direction.

In the embodiment, the vertical scanning direction is G1 → G864 downward, and the horizontal scanning direction is S1 →
Although it was the right direction of S192, it is good also as a structure which can switch a scanning direction in order to cope with the case where it is set as the projector mentioned later and a rotatable display apparatus.
In the embodiment, the six lines of data lines 114 are blocked to generate image data Vd.
Although the phase expansion drive method for converting the channels to 1d to Vd6d is adopted, the number of channels and the number of data lines applied simultaneously (that is, the number of data lines belonging to one block) are not limited to “6”. Also, so-called dot sequential driving may be used.
Further, the data signal supply circuit 300 processes the digital image data Vd, but may be configured to process an analog image signal. In the embodiment,
Although the description has been given of the normally white mode in which white display is performed when the voltage effective value between the common electrode 108 and the pixel electrode 118 is small, a normally black mode in which black display is performed may be employed.

In the above-described embodiment, the TN type is used as the liquid crystal, but BTN (Bi-stable Twisted Ne) is used.
matic) and ferroelectric types such as bistable types with memory properties, polymer dispersed types, and dyes that have anisotropy in visible light absorption in the long and short axis directions of molecules (guests) ) May be dissolved in a liquid crystal (host) having a certain molecular arrangement, and a GH (guest host) type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.
The present invention can also be applied to potential adjustment of display electrodes of a plasma display.

Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described. FIG.
It is a top view which shows the structure of this projector. As shown in this figure, the projector 2
Inside the 100, a lamp unit 2102 made of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Light valves 100R and 100G corresponding to each primary color
And 100B, respectively. B light is compared with other R and G colors.
Since the optical path is long, the light is guided through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an output lens 2124 in order to prevent the loss.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and R, supplied from a processing circuit (not shown in FIG. 8).
It is driven by an image signal corresponding to each color of G and B. In other words, the projector 2100 has a configuration in which three sets of electro-optical devices including the display panel 100 are provided corresponding to the R, G, and B colors.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight.
Therefore, after the images of the respective colors are combined, the projection lens 2114 is displayed on the screen 2120.
As a result, a color image is projected.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to the primary colors of R, G, and B is incident by 108, there is no need to provide a color filter. Further, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

In addition to the electronic devices described with reference to FIG. 8, the electronic devices include a television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the above-described electro-optical device can be applied to these various electronic devices.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel of the display panel. It is a figure for demonstrating the vertical and horizontal scanning of the same electro-optical apparatus. It is a figure for demonstrating the sampling in the same electro-optical apparatus. FIG. 6 is a diagram illustrating a voltage and the like held by a pixel capacitor in the same electro-optical device. It is a figure which shows the fluctuation | variation of the optimal voltage. FIG. 2 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 50 ... Processing circuit, 52 ... Scanning control circuit, 54 ... Voltage output circuit, 5
6 ... resistive element, 58 ... capacitor element, 100 ... display panel, 107 ... capacitor line, 108 ... common electrode, 109 ... storage capacitor, 110 ... pixel, 112 ... scan line, 114 ... data line, 116 ... T
FT, 118 ... pixel electrode, 130 ... scanning line drive circuit, 140 ... block selection circuit, 151 ...
Sampling switch, 171 ... Image signal line, 2100 ... Projector

Claims (4)

A plurality of pixels provided corresponding to intersections of a plurality of rows of scanning lines and a plurality of columns of data lines,
An individual pixel electrode for each pixel;
A common electrode common across each pixel;
A pixel including the pixel electrode and the common electrode;
An electro-optical device, comprising: a voltage output circuit that outputs a voltage to be applied to the common electrode; and a resistance element electrically interposed between the common electrode. The electro-optical device according to claim 1, further comprising a capacitive element electrically interposed between the common electrode and a predetermined potential line maintained at a constant potential. A scanning line driving circuit for selecting the scanning lines in a predetermined order;
3. The data line driving circuit according to claim 1, further comprising: a data line driving circuit that supplies a data signal corresponding to a gray level of the pixel corresponding to the selected scanning line to the data line. Electro-optic device.   An electronic apparatus comprising the electro-optical device according to claim 1.

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