WO2013031552A1 - Liquid-crystal display device and method for driving same - Google Patents

Liquid-crystal display device and method for driving same Download PDF

Info

Publication number
WO2013031552A1
WO2013031552A1 PCT/JP2012/070883 JP2012070883W WO2013031552A1 WO 2013031552 A1 WO2013031552 A1 WO 2013031552A1 JP 2012070883 W JP2012070883 W JP 2012070883W WO 2013031552 A1 WO2013031552 A1 WO 2013031552A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
video signal
scanning
auxiliary capacitance
pixel
Prior art date
Application number
PCT/JP2012/070883
Other languages
French (fr)
Japanese (ja)
Inventor
耕平 田中
誠二 金子
小川　康行
山本　薫
誠一 内田
泰 高丸
森　重恭
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2013031552A1 publication Critical patent/WO2013031552A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device that changes the potential of an auxiliary capacitance line in a liquid crystal display device at a predetermined timing and a driving method thereof.
  • a driving method in which the potential of the corresponding auxiliary capacitance line is changed after the selection period of each gate line (scanning signal line) is completed.
  • a driving method is referred to as a “CS driving method”.
  • This CS driving method generally includes a CS driver (auxiliary capacitance line driving circuit) for sequentially changing the potential of each CS line (the auxiliary capacitance line) in a liquid crystal display device. It is realized by providing it.
  • the CS driver is configured using, for example, a shift register. According to such a CS driving method, a large voltage can be applied to the liquid crystal layer with a small video signal amplitude, so that power consumption can be reduced.
  • Patent Document 1 for example.
  • Patent Document 2 discloses a liquid crystal display device in which a plurality of CS lines (auxiliary capacitance lines) are grouped into a plurality (for example, four) groups, and a plurality of CS lines included in each group are collectively driven. It is disclosed. With this configuration, the CS driver (auxiliary capacitor driver) can be simplified.
  • Japanese Unexamined Patent Publication No. 5-143021 Japanese Unexamined Patent Publication No. 2009-75418 Japanese Unexamined Patent Publication No. 2001-31253
  • an object of the present invention is to provide a CS driving type liquid crystal display device that reduces power consumption while reducing the frame area, and a driving method thereof.
  • a first aspect of the present invention is a liquid crystal display device, A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of video signal lines and the plurality of scanning signal lines, A plurality of auxiliary capacitance lines arranged along a plurality of predetermined signal lines which are either the plurality of video signal lines or the plurality of scanning signal lines, and each pixel electrode and the plurality of auxiliary capacitance lines.
  • a display unit including an auxiliary capacitor formed between the two, A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle.
  • a scanning signal line driving circuit for driving the plurality of scanning signal lines as shown in FIG.
  • a video signal line drive that applies a video signal to the plurality of pixel electrodes via the plurality of video signal lines and sets the video signal to have a first polarity or a second polarity different from each other in the scanning period.
  • a storage capacitor signal to be applied to each storage capacitor line is generated, and a potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the first polarity video signal is applied. And the potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the video signal of the second polarity is applied and
  • An auxiliary capacitance signal generation circuit is provided that makes the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period. .
  • the pause period is longer than the scanning period.
  • the predetermined signal line is the scanning signal line;
  • the auxiliary capacitance is formed between a pixel electrode corresponding to each scanning signal line and an auxiliary capacitance line along the scanning signal line,
  • the video signal line driving circuit selects the predetermined number of the scanning signal lines to select the polarity of the plurality of video signals to be applied to the plurality of video signal lines, respectively. It is characterized by inversion every period.
  • the predetermined signal line is the video signal line;
  • the auxiliary capacitance is formed between a pixel electrode corresponding to each video signal line and an auxiliary capacitance line along the video signal line,
  • the video signal line driving circuit reverses the polarity of the plurality of video signals to be given to the plurality of video signal lines for each of a predetermined number of the video signal lines in the scanning period.
  • a pixel electrode corresponding to an odd-numbered scanning signal line counted from the arrangement position side of the video signal line driving circuit, arranged in the direction in which the video signal line extends to the pixel electrode, and of the video signal line driving circuit The pixel electrodes corresponding to the even-numbered scanning signal lines counted from the arrangement position side correspond to the video signal lines adjacent to each other.
  • the predetermined signal line is the scanning signal line;
  • the auxiliary capacitor includes a pixel electrode corresponding to an odd-numbered video signal line counted from an arrangement position side of the scanning signal line driving circuit among pixel electrodes corresponding to each scanning signal line, and along the scanning signal line.
  • the video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. It is characterized in that each signal line is inverted.
  • the predetermined signal line is the video signal line;
  • the auxiliary capacitor includes pixel electrodes corresponding to odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit among pixel electrodes corresponding to the video signal lines, and along the video signal lines.
  • the video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. It is characterized in that each signal line is inverted.
  • the video signal line driving circuit is characterized in that the amplitude of the plurality of video signals in a selection period in which each scanning signal line is in a selected state is reduced from the start time to the end time of the scanning period.
  • Each auxiliary capacitance line is formed as a transparent electrode.
  • Each auxiliary capacitance line is formed as an electrode of the same material as the predetermined signal line along the auxiliary capacitance line.
  • An eleventh aspect of the present invention is any one of the first to tenth aspects of the present invention,
  • the display unit further includes a thin film transistor in which the scanning signal line corresponding to each pixel electrode is connected to a gate terminal, and a semiconductor layer is formed of an oxide semiconductor,
  • the video signal line and the pixel electrode corresponding to the video signal line are connected via the thin film transistor in which the scanning signal line corresponding to the pixel electrode is connected to the gate terminal.
  • a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of scanning signal lines are arranged in a matrix.
  • a driving method for a display device comprising: a video signal line driving circuit for supplying video signals to a plurality of pixel electrodes; and an auxiliary capacitance signal generating circuit for generating an auxiliary capacitance signal to be given to each auxiliary capacitance line,
  • a scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle.
  • the video signal has a polarity that is either a first polarity or a second polarity different from each other;
  • the storage capacitor signal potential to be applied to the storage capacitor line in which the storage capacitor is formed between the electrodes is different from each other, and the storage capacitor signal potential to be applied to each storage capacitor line in the pause period is And a step of making the potential different from the potential of the auxiliary capacitance signal to be applied to the auxiliary capacitance line in the scanning period immediately before the pause period.
  • a thirteenth aspect of the present invention is the twelfth aspect of the present invention, wherein the pause period is longer than the scanning period.
  • the amplitude of the plurality of video signals in the selection period in which each scanning signal line is in a selected state is reduced from the start point to the end point of the scanning period.
  • the method further comprises the step of:
  • CS driving is performed in a liquid crystal display device that performs so-called low-frequency refresh driving in which a rest period is provided after the scanning period.
  • the potential of the auxiliary capacitance signal to be given to each auxiliary capacitance line in the pause period is made different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period.
  • This is performed by an auxiliary capacitance signal generation circuit.
  • This auxiliary capacitance signal generation circuit changes the potential of each auxiliary capacitance line (auxiliary capacitance signal) in a pause period without sequentially changing the potential of each auxiliary capacitance line unlike the conventional CS driver.
  • the circuit scale is smaller than that of a conventional CS driver. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
  • the pause period is longer than the scanning period, further power consumption can be achieved.
  • the storage capacitor is formed between the pixel electrode corresponding to each scanning signal line and the storage capacitor line along the scanning signal line.
  • the polarities of the plurality of video signals to be applied to the plurality of video signal lines are inverted every predetermined number of selection periods in which the predetermined number of scanning signal lines are selected. Therefore, line inversion driving can be performed in units of a predetermined number of scanning signal lines.
  • the storage capacitor is formed between the pixel electrode corresponding to each video signal line and the storage capacitor line along the video signal line. Further, in the scanning period, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted every predetermined number of video signal lines. Therefore, line inversion driving can be performed in units of a predetermined number of video signal lines.
  • the pixel electrodes corresponding to the odd-numbered pixels counted from the arrangement position side of the video signal line driving circuit, arranged in the extending direction of the video signal line, and the arrangement of the video signal line driving circuit correspond to the video signal lines adjacent to each other. For this reason, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted every selection period in which each scanning signal line is selected. Thereby, so-called dot inversion driving can be performed.
  • the auxiliary capacitor is a pixel corresponding to an odd-numbered video signal line counted from the arrangement position side of the scanning signal line driving circuit among the pixel electrodes corresponding to each scanning signal line.
  • An even-numbered image that is formed between the electrode and the auxiliary capacitance line along the scanning signal line and counted from the arrangement position side of the scanning signal line driving circuit among the pixel electrodes corresponding to each scanning signal line It is formed between the pixel electrode corresponding to the signal line and the auxiliary capacitance line along the scanning signal line preceding the scanning signal line.
  • the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted for each selection period in which each scanning signal line is selected, and are inverted for each video signal line. For this reason, so-called dot inversion driving can be performed.
  • the auxiliary capacitors correspond to the odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit.
  • the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted for each selection period in which each scanning signal line is selected, and are inverted for each video signal line. For this reason, so-called dot inversion driving can be performed.
  • the amplitude of the plurality of video signals in each selection period decreases from the start point to the end point of the scanning period.
  • the amplitude of the video signal decreases from the first selection period to the last selection period.
  • the scanning signal line that is earlier in the selection state in the scanning period has a higher pixel potential in the pixel formation portion corresponding to the scanning signal line, and the scanning signal line that has the later timing in the selection period in the scanning period.
  • each auxiliary capacitance line is formed as a transparent electrode. For this reason, the fall of an aperture ratio can be suppressed.
  • each auxiliary capacitance line is formed as an electrode made of the same material as a predetermined signal line. For this reason, since the auxiliary capacitance line and the predetermined signal line can be formed in the same process, the cost can be reduced.
  • a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor is provided corresponding to each pixel electrode. For this reason, since the pixel potential can be held for a long time, the pause period can be made sufficiently long. In addition, since the writing of the video signal to the pixel electrode can be speeded up, the scanning period can be sufficiently shortened. Thereby, it is possible to suppress a decrease in the frame frequency (driving frequency in one frame period) while performing the low-frequency refresh driving.
  • the driving method of the liquid crystal display device has the same effects as the first aspect, the second aspect, and the eighth aspect of the present invention, respectively. be able to.
  • FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 3 is a circuit diagram illustrating a configuration of a pixel formation unit in the first embodiment. It is a circuit diagram which shows the structure of the display part in the said 1st Embodiment. It is a signal waveform diagram which shows operation
  • FIG. 6 is a cross-sectional view taken along line A-A ′ in FIG. 5.
  • FIG. 8 is a sectional view taken along line B-B ′ in FIG. 7. It is a figure which shows the drain current-gate voltage characteristic of a-SiTFT and IGZOTFT. It is a circuit diagram which shows the structure of the display part in the 2nd Embodiment of this invention. It is a signal waveform diagram which shows operation
  • FIG. 15 is a sectional view taken along line D-D ′ in FIG. 14.
  • It is a circuit diagram which shows the structure of the display part in the 3rd Embodiment of this invention. It is a signal waveform diagram which shows operation
  • It is a top view which shows the implementation example of the pixel layout in the said 3rd Embodiment. It is a circuit diagram which shows the structure of the display part in the 1st modification of the said 3rd Embodiment.
  • FIG. 1 is a block diagram showing an overall configuration of an active matrix type liquid crystal display device adopting a CS driving method according to a first embodiment of the present invention.
  • the liquid crystal display device includes a power supply 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a display. Part 500 and common electrode driving circuit 600.
  • the liquid crystal display device according to this embodiment does not include a CS driver in the frame portion of the display unit 500 (panel).
  • the display unit 500 includes m source lines (video signal lines) SL1 to SLn, m gate lines (scanning signal lines) GL1 to GLm, and m gate lines GL1 to GLm.
  • a plurality of (m ⁇ n) pixel formation portions provided corresponding to the intersections of the CS lines (auxiliary capacitance lines) CL1 to CLm and the source lines SL1 to SLn and the gate lines GL1 to GLm, respectively. Is formed.
  • m and n are assumed to be even numbers, but the present invention is not limited to this.
  • These m ⁇ n pixel forming portions are arranged in a matrix to form a pixel array.
  • FIG. 2 is a circuit diagram showing a configuration of each pixel forming portion in the present embodiment.
  • the symbol P (i, j) is given to the pixel formation portion in the i-th row and j-th column.
  • the constituent elements other than the pixel formation portion the constituent elements in the i-th row, the j-th column, and the i-th row and j-th column are respectively referred to as “i-th row”, “j-th column”, and “i-row j” The description may be made using the continuation modifier of the “column”.
  • the pixel forming portion P (i, j) in the i-th row and j-th column has a gate terminal connected to the i-th gate line GLi passing through the corresponding intersection and the j-th source line SLj passing through the intersection.
  • a thin film transistor 50 having a source terminal connected thereto, a pixel electrode Ep connected to a drain terminal of the thin film transistor 50, a common electrode Ec commonly provided in the m ⁇ n pixel forming portions, and the m ⁇ n number
  • the liquid crystal layer is provided between the pixel electrode Ep and the common electrode Ec.
  • the symbol Ep (i, j) is attached to the pixel electrode in the pixel formation portion P (i, j) in the i-th row and j-th column. Further, the potential of the pixel electrode Ep (i, j) is referred to as a pixel potential, and is denoted by a reference symbol Vp (i, j).
  • a liquid crystal capacitance Clc is formed by the pixel electrode Ep and the common electrode Ec. Further, an auxiliary capacitor Ccs is formed by the CS line and the pixel electrode Ep. A pixel capacitor Cp is formed by the liquid crystal capacitor Clc and the auxiliary capacitor Ccs.
  • the semiconductor layer of the thin film transistor 50 in this embodiment is formed of, for example, an oxide semiconductor.
  • the present invention is not limited to this, and the semiconductor layer may be formed of, for example, amorphous silicon, polycrystalline silicon, or microcrystalline silicon. Note that an example in which an oxide semiconductor is used for a semiconductor layer will be described later.
  • the power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 600.
  • the DC / DC converter 110 generates a predetermined DC voltage for operating the source driver 300 and the gate driver 400 from the power supply voltage, and supplies it to the source driver 300 and the gate driver 400.
  • the common electrode drive circuit 600 applies a predetermined potential Vcom to the common electrode Ec. This potential Vcom is typically a fixed potential.
  • the display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and controls a digital video signal DV and a source start pulse signal for controlling image display on the display unit 500.
  • SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK are output.
  • the display control circuit 200 in this embodiment is provided with an auxiliary capacitance signal generation circuit 201.
  • the display control circuit 200 generates and outputs an auxiliary capacitance signal CS for applying a bias to the pixel potential in each pixel formation unit by the auxiliary capacitance signal generation circuit 201.
  • This auxiliary capacitance signal CS is composed of two-phase auxiliary capacitance signals CSa and CSb.
  • the auxiliary capacitance signal CSa is referred to as a “first auxiliary capacitance signal”
  • the auxiliary capacitance signal CSb is referred to as a “second auxiliary capacitance signal”.
  • the first auxiliary capacitance signal CSa is applied to the odd-numbered CS lines
  • the second auxiliary capacitance signal CSb is applied to the even-numbered CS lines.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb are respectively sent to two power supply circuits (not shown) provided in the auxiliary capacitance signal generation circuit 201, for example, according to the timing signal group TG described above. Is generated.
  • the present invention is not limited to this, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb may be generated using three or more power supply circuits. In this case, the addition per power supply circuit is reduced.
  • the source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives the video signal SS (1) on the source lines SL1 to SLn, respectively. Apply ⁇ SS (n).
  • the gate driver 400 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 scans signals GS (1) to GS at a high level potential (potential at which each gate line is selected). The application of (m) to each of the gate lines GL1 to GLm is repeated with one frame period as a cycle. A detailed description of the operation of the gate driver 400 will be given later.
  • the video signals SS (1) to SS (n) are applied to the source lines SL1 to SLn, respectively, and the scanning signals GOUT (1) to GOUT (m) are applied to the gate lines GL1 to GLm, respectively.
  • the display unit 500 an image based on the image signal DAT sent from the outside is displayed on the display unit 500.
  • FIG. 3 is a circuit diagram showing a configuration of the display unit 500 in the present embodiment.
  • the CS lines CL1 to CLm in this embodiment are arranged along the gate lines GL1 to GLm, respectively.
  • the auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. ing.
  • the first auxiliary capacitance signal CSa is applied to the CS lines CL1, CL3,... CLm ⁇ 1 in the odd-numbered rows (hereinafter simply referred to as “odd-numbered rows”) counted from the side where the source driver 300 is arranged.
  • the second auxiliary capacitance signal CSb is applied to the CS lines CL2, CL4,... CLm of even-numbered rows (hereinafter simply referred to as “even-numbered rows”) counted from the side where the source driver 300 is disposed.
  • FIG. 4 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment.
  • the pixel potential Vp (1,1) in the first row and the first column the pixel potential Vp (1 in the first row and the second column).
  • the pixel potential Vp (2,1) in the second row and the first column and the pixel potential Vp (m, 1) in the mth row and the first column are illustrated (in FIG. 23, however, Vp (1,1) ) And Vp (m, 1) only).
  • Vp (1,1) the pixel potential in the second row and the first column
  • Vp (m, 1) the pixel potential Vp (m, 1) in the mth row and the first column
  • one frame period is composed of a scanning period T1 and a pause period T2 provided after the scanning period T1. That is, the gate driver 400 drives the m gate lines GL1 to GLm so that the scanning period T1 and the scanning period T2 appear alternately with one frame period as a cycle.
  • the scanning period T1 the scanning signals GS (1) to GS (m) are sequentially set to the high level potential based on the gate clock signal GCK.
  • the suspension period T2 all of the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) are in a non-selected state (low level potential).
  • the driving performed by providing the pause period T2 after the scanning period T1 is called “low frequency refresh driving”, and is disclosed in, for example, Patent Document 3.
  • the length of the scanning period T1 is 8.3 msec
  • the length of the pause period T2 is 991.7 msec. That is, the pause period T2 is longer than the scanning period T1.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh.
  • the video signals SS (1) to SS (n) repeat positive polarity (first polarity) and negative polarity (second polarity) every horizontal scanning period, and have the same polarity in each horizontal scanning period. .
  • the polarities of these video signals SS (1) to SS (n) are inverted every frame period.
  • the polarity inversion of the video signals SS (1) to SS (n) for each frame period is similarly performed in the following embodiments and modifications.
  • the horizontal scanning periods in which the gate lines GL1 to GLm in the 1st to mth rows are selected are referred to as “first to m selection periods”, respectively.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on.
  • the pixel capacitor Cp is charged by the video signal that is output.
  • the pixel potential Vp (1,1) in the first row and the first column which is the pixel potential in the first row
  • the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig.
  • the pixel potential in the first row has a positive polarity.
  • the pixel potentials in the pixel forming portions adjacent to the extending direction of the gate line have the same polarity.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (2, 1) in the second row and the first column which is the pixel potential in the second row, becomes the write potential Vsig.
  • the pixel potential in the second row has a negative polarity.
  • the pixel potential after the second-row gate line GL2 is not selected is the same as that for the first row.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (m, 1) in the m-th row and the first column which is the pixel potential in the m-th row, becomes the write potential Vsig.
  • the pixel potential in the m-th row has a negative polarity.
  • the pixel potential after the m-th gate line GLm is not selected is the same as that for the first row.
  • pixel potentials in pixel forming portions adjacent to the extending direction of the source line (hereinafter referred to as “Y direction”) have different polarities.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
  • the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb are maintained until the end of the scanning period T1 in the subsequent frame period. Further, as described above, all of the gate lines GL1 to GLm are in a non-selected state during the suspension period T2, and each video signal is at a Vcom potential (not limited to this, but may be another fixed potential). Yes. Note that this video signal is not applied to the pixel electrode because the gate lines GL1 to GLm are all in a non-selected state.
  • the pixel potential Vp (1, 1) in the first row and first column is changed to the first potential.
  • the bias voltage ⁇ Vcs corresponding to the change in the one auxiliary capacitance signal CSa is applied.
  • the pixel potential Vp (1, 1) in the first row and the first column is expressed by the following formula (1) (however, the left side is shown as each pixel potential Vp).
  • Cpa represents a parasitic capacitance in the pixel.
  • the pixel potential Vp (1, 1) in the first row and the first column is larger than the write potential Vsig corresponding to the amplitude of the video signal by (Ccs / (Clc + Ccs + Cpa)) ⁇ (Vh ⁇ Vl).
  • the pixel potential Vp (1, 1) in the first row and first column is held until the thin film transistor 50 is turned on again in the scanning period T1 of the frame period subsequent to the present frame period.
  • the timing at which the video signal is written in the scanning period T1 is different in the 1st to mth rows, while the auxiliary capacitance signal is simultaneously changed in the 1st to mth rows in the rest period T2. For this reason, wrinkles may occur in the effective voltage for one frame in the first to mth rows.
  • each row has a different period from when the bias voltage ⁇ Vcs is added to the pixel potential Vp in the pause period T2 until the video signal is written in the immediately following scanning period T1. Because of.
  • “effective voltage for one frame” refers to a scanning period in a frame period subsequent to a video signal writing point (hereinafter simply referred to as “writing point”) in a scanning period T1 in an arbitrary frame period.
  • the effective voltage applied to the pixel capacitor Cp in the period up to the writing time at T1 (hereinafter referred to as “one frame holding period”).
  • the voltage applied to the pixel capacitor Cp of the pixel formation portion P (1,1) in the first row and first column corresponds to the difference between the pixel potential Vp (1,1) and the Vcom potential shown in FIG.
  • Such a difference in effective voltage for one frame is particularly large in a difference in period from when the bias voltage ⁇ Vcs is added to the pixel potential Vp in the pause period T2 to when the video signal is written in the immediately following scanning period T1. It becomes large between the 1st line and the m-th line.
  • the pause period T2 (991.7 msec) is set longer than the scanning period T1 (8.3 msec).
  • the pause period T2 is sufficiently longer than the scanning period T1
  • the influence of the difference in the 1st to mth rows of the timing at which the video signal is written in the scanning period T1 with respect to the one frame holding period is reduced. Therefore, the effective voltage drop for one frame in the 1st to mth rows is reduced.
  • FIG. 5 is a plan view showing a first implementation example of the pixel layout in the present embodiment.
  • 6 is a cross-sectional view taken along line AA ′ in FIG. 5 and 6 and the subsequent drawings relating to the pixel layout, the portion corresponding to the pixel formation portion P (i, j) is mainly shown.
  • the source line, the gate line, and the CS line are hatched, but the transparent electrode is not hatched.
  • illustration of an insulating substrate etc. is omitted.
  • the source line and the gate line are provided so as to cross each other, and the CS line is provided along the gate line.
  • the thin film transistor 50 is connected to a source line (more specifically, a part of the source line is a source electrode), is connected to a gate line (more specifically, a part of the gate line is a gate electrode), and is connected to a drain electrode. Connected to Ed.
  • the drain electrode Ed and the pixel electrode Ep are connected to each other through a contact hole CH.
  • the source line and the gate line are formed by a laminated film of an Al film and a Ti film, for example.
  • the CS line is also formed by a laminated film of an Al film and a Ti film.
  • a first insulating layer 51 is formed on the CS line (and the gate line).
  • the first insulating layer 51 is made of, for example, SiN x .
  • a source line and drain electrode Ed are formed on the first insulating layer 51.
  • the first insulating layer 51 forms an auxiliary capacitor Ccs between the CS line and the drain electrode Ed (that is, the pixel electrode Ep).
  • a second insulating layer 52 is formed on the source line and drain electrode Ed.
  • the second insulating layer 52 is made of, for example, SiN x . In the second insulating layer 52, the contact hole CH described above for connecting the drain electrode Ed and the pixel electrode Ep to each other is formed.
  • the pixel electrode Ep is formed so as to cover the contact hole CH. For this reason, the drain electrode Ed and the pixel electrode Ep are connected to each other.
  • the pixel electrode Ep is a transparent electrode made of ITO (Indium Tin Oxide) or the like.
  • a liquid crystal layer 60 is formed by filling liquid crystal between the pixel electrode Ep and the common electrode Ec which is a transparent electrode made of ITO or the like facing the pixel electrode Ep.
  • the liquid crystal layer 60 forms a liquid crystal capacitance Clc (not shown) between the pixel electrode Ep and the common electrode Ec.
  • the CS line is made of the same material as the gate line, these can be formed in the same process.
  • FIG. 7 is a plan view showing a second implementation example of the pixel layout in the present embodiment.
  • 8 is a cross-sectional view taken along the line BB ′ in FIG. Note that description of portions common to the first implementation example is omitted.
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line in this implementation example is continuously formed across pixel forming portions adjacent in the X direction.
  • the drain electrode Ed is connected only to the pixel electrode Ep via the contact hole CH, and is not connected to the CS line.
  • the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
  • a first insulating layer 51 is formed on the source line.
  • a CS line which is a transparent electrode made of ITO or the like, is formed on the first insulating layer 51.
  • a second insulating layer 52 is formed on the CS line.
  • a pixel electrode Ep is formed on the second insulating layer 52. The second insulating layer 52 forms an auxiliary capacitor Ccs between the CS line and the pixel electrode Ep.
  • the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
  • a-Si TFT a thin film transistor
  • a-Si TFT a thin film transistor
  • a-Si amorphous silicon
  • an oxide semiconductor is used for the semiconductor layer of the thin film transistor 50 in each pixel formation portion in this embodiment.
  • the oxide semiconductor typically, InGaZnO x (hereinafter referred to as “IGZO”), which is an oxide semiconductor mainly containing indium, gallium, zinc, and oxygen, is used. It is not limited. For example, any oxide semiconductor containing at least one of indium, gallium, zinc, copper, silicon, tin, aluminum, calcium, germanium, and lead may be used.
  • FIG. 9 is a diagram showing drain current-gate voltage characteristics of a TFT using a-Si TFT and IGZO as a semiconductor layer (hereinafter referred to as “IGZOTFT”).
  • the horizontal axis represents the gate voltage Vg
  • the vertical axis represents the drain current Ids.
  • the leakage current of the IGZOTFT is 1/1000 or less of the leakage current of the a-Si TFT
  • the on-current of the IGZOTFT is about 20 times the on-current of the a-Si TFT.
  • the IGZOTFT has a small off-leakage current as described above, when the IGZOTFT is used as the thin film transistor 50 in this embodiment, the pixel potential can be maintained for a longer time than when the a-Si TFT is used as the thin film transistor 50. For this reason, when the IGZOTFT is used as the thin film transistor 50 in the present embodiment, the idle period T2 can be sufficiently provided.
  • the IGZOTFT has a large on-state current as described above, when the IGZOTFT is used as the thin film transistor 50 in this embodiment, the video signal is written to the pixel formation portion more than when the a-Si TFT is used as the thin film transistor 50. Can be speeded up. That is, the scanning period T1 can be shortened.
  • CS driving is performed in a liquid crystal display device that performs so-called low-frequency refresh driving in which a pause period T2 is provided after the scanning period T1.
  • a CS driver for driving a CS line is not provided in the frame portion of the display unit 500 (panel).
  • the display control circuit 200 is provided with an auxiliary capacitance signal generation circuit 201 that collectively changes the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the respective CS lines in the idle period T2.
  • this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved. Further, since the potentials of all the CS lines (auxiliary capacitance signals) change simultaneously, the scanning order of the gate lines is ascending (GL1 ⁇ GL2 ⁇ ... ⁇ GLm) or descending (GLm ⁇ ... ⁇ GL2 ⁇ GL1). ) CS driving can be performed regardless of whether or not.
  • the pause period T2 is provided longer than the scanning period T1, further power consumption can be achieved.
  • the pause period T2 is sufficiently provided, the influence of the difference in the 1st to mth rows of the timing at which the video signal is written in the scanning period T1 with respect to the 1 frame holding period is reduced. Therefore, the effective voltage drop for one frame in the 1st to m-th rows is sufficiently reduced.
  • the CS lines CL1 to CLm are provided along the gate lines GL1 to GLm, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered rows and It is given to the CS line of the even row.
  • the scanning period T1 the polarity of each video signal is inverted every horizontal scanning period, and the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2.
  • line inversion driving (“gate line inversion driving”) that inverts the polarity of the video signal every predetermined number of gate lines (in this embodiment, one) and every frame period. Say).
  • the cost can be reduced because the CS line can be formed in the same process as the gate line.
  • the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
  • the pixel potential can be held for a long time, so that the pause period T2 can be made sufficiently long.
  • the scanning period T1 can be sufficiently shortened. In this case, it is possible to suppress a decrease in the frame frequency (drive frequency in one frame period) while performing the low frequency refresh drive.
  • FIG. 10 is a circuit diagram showing a configuration of the display unit 500 according to the second embodiment of the present invention. Note that this embodiment is the same as the first embodiment except for the configuration of the display unit 500, the operation of the liquid crystal display device, and an implementation example of the pixel layout, and thus description of the same parts is omitted. .
  • the number of CS lines is n.
  • the n CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively.
  • the auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Yes.
  • the first auxiliary capacitance signal CSa is applied to the CS lines CL1, CL3,..., CLn ⁇ 1 of the odd-numbered columns (hereinafter simply referred to as “odd-numbered columns”) counted from the side where the gate driver 400 is disposed.
  • the second auxiliary capacitance signal CSb is applied to the CS lines CL2, CL4,... CLn of even-numbered columns (hereinafter simply referred to as “even-numbered columns”) counted from the side where the gate driver 400 is disposed.
  • FIG. 11 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment.
  • the description of the same parts as those in the first embodiment will be omitted as appropriate.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other, respectively. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh.
  • the video signals applied to the odd-numbered and even-numbered source lines are positive and negative in the scanning period T1 (in the scanning period T1 in the subsequent frame period), respectively. Negative polarity and positive polarity).
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (1,1) in the first row and the first column which is the pixel potential in the first row
  • the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig.
  • the pixel potentials of the odd-numbered and even-numbered columns in the first row are positive and negative, respectively. Become sex.
  • the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (2, 1) in the second row and the first column which is the pixel potential in the second row, becomes the write potential Vsig.
  • the odd-numbered and even-numbered video signals are positive and negative, respectively, the odd-numbered and even-numbered pixels in the second row are the same as in the first row. The potential becomes positive and negative, respectively.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (m, 1) in the m-th row and the first column which is the pixel potential in the m-th row, becomes the write potential Vsig.
  • the odd-numbered and even-numbered video signals are positive and negative, respectively, the odd-numbered and even-numbered pixels in the m-th row are the same as the first row. The potential becomes positive and negative, respectively.
  • the pixel potentials in the pixel forming portions adjacent in the Y direction have the same polarity.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
  • FIG. 12 is a plan view showing a first implementation example of the pixel layout in the present embodiment.
  • 13 is a cross-sectional view taken along the line CC ′ in FIG. Note that description of parts similar to those of the implementation examples in the first embodiment is omitted as appropriate.
  • the source line and the gate line are provided so as to cross each other, and the CS line is provided along the source line.
  • the CS line in this implementation example is a CS bus line Bcs along the source line and a narrow CS line Ecs along the gate line and having a width in the X direction smaller than the distance between adjacent source lines. (Hereinafter simply referred to as “CS line Ecs”).
  • the material of each component in this implementation example is the same as that in the first implementation example of the first embodiment.
  • the CS bus line Bcs and the CS line Ecs are formed of the same material (for example, a laminated film of an Al film and a Ti film).
  • a first insulating layer 51 is formed on the CS line Ecs (and the gate line).
  • a first contact hole CHa for connecting the CS line Ecs and the CS bus line Bcs to each other is formed.
  • a source line, a drain electrode Ed, and a CS bus line Bcs are formed on the first insulating layer 51.
  • the CS bus line Bcs is formed so as to cover the first contact hole CHa. For this reason, the CS line electrode Ecs and the CS bus line Bcs are connected to each other.
  • the first insulating layer 51 forms an auxiliary capacitor Ccs between the CS line Ecs and the drain electrode Ed (that is, the pixel electrode Ep).
  • a second insulating layer 52 is formed on the source line, the drain electrode Ed, and the CS bus line Bcs.
  • the contact hole CH described above for connecting the drain electrode Ed and the pixel electrode Ep to each other is formed.
  • the pixel electrode Ep is formed so as to cover the contact hole CH. For this reason, the drain electrode Ed and the pixel electrode Ep are connected to each other.
  • the CS line Ecs is made of the same material as the gate line, they can be formed in the same process. Further, since the CS bus line Bcs is made of the same material as the source line and the drain electrode Ed, they can be formed in the same process.
  • FIG. 14 is a plan view showing a second implementation example of the pixel layout in the present embodiment.
  • 15 is a cross-sectional view taken along the line DD ′ in FIG. Note that description of portions common to the first implementation example is omitted. Further, FIG. 15 (layer structure) is the same as that of the second example of realization in the first embodiment, and the description thereof is omitted.
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line in this implementation example is continuously formed across pixel forming portions adjacent in the Y direction. In FIG. 14, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
  • the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
  • the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the odd-numbered and even-numbered CS lines are applied during the idle period T2.
  • An auxiliary capacitance signal generation circuit 201 that changes all at once is provided in the display control circuit 200. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
  • CS driving can be performed regardless of whether or not.
  • the CS lines CL1 to CLn are provided along the source lines SL1 to SLn, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered columns and It is given to the CS line of the even column.
  • the odd-numbered and even-numbered video signals have different polarities, and the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2.
  • line inversion driving (“source line inversion driving") that changes the polarity of the video signal for each predetermined number of source lines (one in this embodiment) and for each frame period while performing CS driving. Say).
  • the CS line Ecs can be formed in the same process as the gate line, and the CS bus line Bcs is set as the source line and the drain line. It can be formed by the same process. For this reason, cost can be reduced.
  • the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
  • FIG. 16 is a circuit diagram showing a configuration of the display unit 500 according to the third embodiment of the present invention. Note that this embodiment is the same as the first embodiment except for the configuration of the display unit 500, the operation of the liquid crystal display device, and an implementation example of the pixel layout, and thus description of the same parts is omitted. .
  • CS lines CL1 to CLm are arranged along the gate lines GL1 to GLm, respectively, as in the first embodiment, while one CS line CL0 is further provided. It is provided as a CS line preceding the CS line CL1 in the first row.
  • the CS line CL0 may be referred to as a “0th CS line”.
  • the CS line CL0 is assumed to belong to the even-numbered CS line.
  • the auxiliary capacitance Ccs in the pixel formation portion in the odd-numbered column is between the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Is formed.
  • the auxiliary capacitance Ccs in the pixel formation portion in the even-numbered column includes the CS line preceding the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected, and It is formed between the pixel electrode Ep in the pixel formation portion.
  • the first auxiliary capacitance signal CSa is supplied to the odd-numbered CS lines CL1, CL3,... CLm-1.
  • the second auxiliary capacitance signal CSb is supplied to CL0, CL2, CL4,.
  • FIG. 17 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment.
  • the description of the same parts as those in the first embodiment will be omitted as appropriate.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other, respectively. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh.
  • the video signals SS (1) to SS (n) repeat the positive polarity and the negative polarity every horizontal scanning period, and the odd-numbered and even-numbered video signals have different polarities.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (1,1) in the first row and the first column which is the pixel potential in the first row
  • the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig.
  • the pixel potentials in the odd-numbered columns and the even-numbered columns in the first row Respectively have a positive polarity and a negative polarity.
  • the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potentials of the odd-numbered and even-numbered columns in the second row Respectively have negative polarity and positive polarity.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (m, 1) in the m-th row and the first column which is the pixel potential in the m-th row, becomes the write potential Vsig.
  • the pixel potentials of the odd-numbered and even-numbered columns in the m-th row Respectively have negative polarity and positive polarity.
  • the pixel potentials have different polarities not only in the pixel forming portion adjacent in the X direction but also in the pixel forming portion adjacent in the Y direction.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change in the same manner as in the first embodiment. Therefore, the odd-numbered CS lines change from the low potential Vl to the high potential Vh, and the even-numbered CS lines change from the high potential Vh to the low potential Vl at the same timing.
  • the pixel potential (pixel potential of the odd-numbered column) of the pixel electrode Ep of the odd-numbered column connected to the CS line of the odd-numbered row via the auxiliary capacitor Ccs has a positive polarity, and the pixel electrode of the even-numbered column The pixel potential of Ep (pixel potential in even-numbered columns) is negative.
  • the pixel potential of the odd-numbered pixel electrode Ep (pixel potential of the odd-numbered column) connected to the even-numbered CS line via the auxiliary capacitor Ccs has a negative polarity, and the pixels of the even-numbered pixel electrode Ep.
  • the potential (pixel potential in even-numbered columns) is positive. Note that the basic operation in the suspension period T2 is the same as that in the first embodiment, and a description thereof will be omitted.
  • FIG. 18 is a plan view showing an implementation example of the pixel layout in the present embodiment. Note that description of parts similar to those of the implementation examples in the first embodiment is omitted as appropriate. Further, the basic layer structure and the material of each component in the present implementation example are the same as those in the second implementation example (see FIG. 8) in the first embodiment. As shown in FIG. 18, in this implementation example, the source line and the gate line are provided so as to cross each other, and the CS line is provided along the gate line.
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line is continuously formed over pixel forming portions adjacent in the X direction. In FIG. 18, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
  • Each CS line in this implementation example is composed of two CS lines.
  • one of these two CS lines is referred to as a “first CS line”, and is denoted by a symbol CLa.
  • the other of these two CS lines is referred to as a “second CS line”, and is denoted by reference symbol CLb.
  • CLa potentials having the same polarity are applied to the first CS line and the second CS line (however, the polarity is inverted for each CS line).
  • the first CS line CLa and the second CS line constituting each CS line are arranged on both sides of the gate line along the CS line. In FIG.
  • the first CS line is opposed to the pixel electrode Ep of the pixel formation portion in the odd-numbered column (hereinafter simply referred to as “in the pixel formation portion” in the description of the pixel layout according to the present implementation example).
  • the area of CLa (the width in the Y direction) is larger than the area of the first CS line CLa in the pixel formation portion in the even-numbered column.
  • the area (width in the Y direction) of the second CS line CLb in the pixel formation portion in the odd-numbered column is smaller than the area of the second CS line CLb in the pixel formation portion in the even-numbered column. Note that the sum of the area of the first CS line CLa and the area of the second CS line CLb in each pixel formation portion is substantially equal.
  • the auxiliary capacitance Ccs of each pixel formation portion in this implementation example is specifically referred to as an auxiliary capacitance (hereinafter referred to as “first auxiliary capacitance”) formed between the first CS line CLa and the pixel electrode Ep in the pixel formation portion.
  • first auxiliary capacitance an auxiliary capacitance formed between the second CS line CLb and the pixel electrode Ep in the pixel formation portion.
  • second auxiliary capacitor an auxiliary capacitor formed between the second CS line CLb and the pixel electrode Ep in the pixel formation portion
  • the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
  • the second CS line CLb in the pixel formation portion in the even-numbered row is larger than the first CS line CLa in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially constituted by the second auxiliary capacitance Ccsb. ing.
  • the first CS line CLa and the second CS line CLb in each pixel forming portion constitute adjacent CS lines.
  • the first CS line CLa in the pixel formation portion in the i-th row and j-th column constitutes the i-th row CS line CLi
  • the second CS line CLb constitutes the i-th row CS line CLi-1.
  • different potentials are applied to the odd-numbered and even-numbered CS lines, that is, the first CS line CLa and the second CS line CLb in each pixel formation portion have different potentials (high potential Vh or A low potential Vl) is applied.
  • each pixel potential Vp after the potentials of all the CS lines simultaneously change in the rest period T2 is expressed by the following formula (2) obtained by modifying the above formula (1).
  • the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
  • the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the odd-numbered and even-numbered CS lines, respectively, are applied in the idle period T2.
  • An auxiliary capacitance signal generation circuit 201 that changes all at once is provided in the display control circuit 200. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
  • CS driving can be performed regardless of whether or not.
  • the CS lines CL1 to CLm are provided along the gate lines GL1 to GLm, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered rows and It is given to the CS line of the even column.
  • the scanning period T1 the polarity of each video signal is inverted every horizontal scanning period and every frame period, the video signals in the odd-numbered columns and the even-numbered columns have different polarities, and the first auxiliary The potentials of the capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2. For this reason, while performing CS driving, it is possible to perform dot inversion driving that changes the polarity of the video signal for each pixel forming portion adjacent in the X direction and the Y direction and for each frame period.
  • the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
  • FIG. 19 is a circuit diagram showing a configuration of the display unit 500 in the first modification of the third embodiment of the present invention. Since the present modification is the same as the first embodiment and the third embodiment except for the configuration of the display unit 500 and the pixel layout implementation example, the description of the same parts is omitted. .
  • CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively, as in the second embodiment, while one CS line CL0 is further provided. It is provided as a CS line preceding the CS line CL1 in the first column.
  • the CS line CL0 may be referred to as a “0th column CS line”.
  • the CS line CL0 is assumed to belong to the even-numbered CS line.
  • Each CS line corresponds to a source line along the CS line and a source line subsequent to the source line.
  • the auxiliary capacitance Ccs in the pixel formation portion in the odd-numbered rows includes a CS line (that is, a CS line corresponding to the source line) arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected, and It is formed between the pixel electrode Ep in the pixel formation portion.
  • the auxiliary capacitance Ccs in the pixel formation portion in the even-numbered row is the CS line preceding the CS line (that is, the source) arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected. The line is formed between the corresponding CS line) and the pixel electrode Ep in the pixel formation portion.
  • the first auxiliary capacitance signal CSa is supplied to the odd-numbered CS lines CL1, CL3,... CLn-1.
  • the second auxiliary capacitance signal CSb is applied to the CS lines CL0, CL2, CL4,. Since the operation of the liquid crystal display device is the same as that of the third embodiment, description thereof is omitted (see FIG. 17).
  • FIG. 20 is a plan view showing an implementation example of the pixel layout in this modification.
  • description is abbreviate
  • the basic layer structure and the material of each component in the present implementation example are the same as those in the second implementation example (see FIG. 15) in the second embodiment.
  • the source line and the gate line are provided so as to cross each other, and the CS line is provided along the source line (more specifically, so as to cover the source line).
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line is continuously formed over pixel forming portions adjacent in the Y direction. Although the CS line does not cover the thin film transistor 50 in FIG. 20, the present invention is not limited to this.
  • each CS line protrudes toward the pixel forming portion on the odd-numbered row corresponding to the source line covered by the CS line (the width in the X direction increases), and the pixel Opposite the pixel electrode Ep of the formation part.
  • each CS line protrudes to the pixel formation part side of the even-numbered row corresponding to the source line preceding the source line covered by the CS line, and faces the pixel electrode Ep of the pixel formation part.
  • the portion of the CS line that protrudes toward the pixel formation portion and faces the pixel electrode Ep of the pixel formation portion is referred to as a “main CS line”.
  • the opposite side of the main CS line of each CS line in the X direction also slightly faces the pixel forming portion as shown in FIG.
  • the portion of the CS line slightly facing the pixel forming portion is referred to as a “sub CS line”.
  • the main CS line (in each pixel formation portion) facing the pixel electrode Ep in each pixel formation portion has a larger area than the sub CS line in the pixel formation portion. Further, the sum of the area of the main CS line and the area of the sub CS line in each pixel forming portion is substantially equal.
  • the auxiliary capacitance Ccs of each pixel formation portion in this implementation example is more specifically the auxiliary capacitance formed between the main CS line and the pixel electrode Ep in the pixel formation portion (the implementation example of the third embodiment).
  • first auxiliary capacitor and is denoted by Ccsa
  • second auxiliary capacity and is denoted by a symbol Ccsb).
  • the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
  • each pixel potential Vp after the potentials of all the CS lines simultaneously change in the rest period T2 is expressed by the above equation (2) as in the implementation example of the third embodiment.
  • FIG. 21 is a circuit diagram showing a configuration of the display unit 500 in the second modification example of the third embodiment of the present invention.
  • description is abbreviate
  • CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively, as in the second embodiment, while one more source line SLn + 1 is provided. It is provided as a source line subsequent to the n-th source line SLn. This source line SLn + 1 belongs to the odd-numbered source line.
  • one CS line CLn + 1 is further provided as a CS line subsequent to the CS line CLn + 1 in the nth column. It is assumed that the CS line CLn + 1 belongs to the odd-numbered CS line.
  • the pixel forming portion (pixel electrode Ep) in the odd-numbered row and the pixel forming portion in the same column (aligned in the Y direction) and the even-numbered row as the pixel forming portion are respectively connected to the adjacent source lines. It corresponds. That is, the odd-numbered pixel forming portions and the even-numbered pixel forming portions in the same column respectively correspond to the adjacent source lines. More specifically, as shown in FIG. 21, the source terminal of the thin film transistor in the pixel formation portion in the odd-numbered rows is connected to the source line in the same column as the pixel formation portion. On the other hand, the source terminal of the thin film transistor in the pixel formation portion in the odd-numbered row is connected to the source line of the column immediately after the pixel formation portion.
  • auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion.
  • the video signal applied to the source line and the auxiliary capacitance signal applied to the CS line are the same as those in the second embodiment.
  • the operation is performed by the same video signal and auxiliary capacitance signal as in the second embodiment.
  • the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities
  • the pixel potentials in the pixel formation portions adjacent in the Y direction have different polarities. That is, dot inversion driving is performed as in the third embodiment and the first modification thereof.
  • FIG. 22 is a plan view showing an implementation example of the pixel layout in the present modification.
  • the pixel layout in this modification is basically the same as that in the first modification of the third embodiment except for the location of the thin film transistor (see FIG. 20).
  • the auxiliary capacitance Ccs of each pixel forming unit is configured by the first auxiliary capacitance Ccsa and the second auxiliary capacitance Ccsb described above.
  • the main CS line in each pixel formation portion has a larger area than the sub CS line in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
  • FIG. 23 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the fourth embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the operation of the liquid crystal display device, the description of the same portion is omitted. Of the operation of the liquid crystal display device, the description of the same parts as those in the first embodiment will be omitted as appropriate.
  • the length of the scanning period T1 is 8.3 msec, which is the same as that in the first embodiment, whereas the length of the pause period T2 is different from that in the first embodiment. It is 8.3 msec. That is, a pause period T2 having the same length as the scanning period T1 is provided.
  • the effective voltage for one frame can be wrinkled in the 1st to mth rows.
  • the amplitude of each video signal decreases from the first selection period to the mth selection period.
  • the write potential Vsig increases as the line is on the scanning start side (side with the smaller gate line code number), and the write potential Vsig becomes closer toward the scanning end side (side with the larger gate line code number). Get smaller.
  • the pixel potential Vp increases as the scanning start side row, and the pixel potential Vp decreases as the scanning end side row.
  • wrinkles are reduced in the effective voltage for one frame in the 1st to mth rows.
  • the auxiliary capacitance signal generation circuit 201 is provided in the display control circuit 200, but the present invention is not limited to this.
  • the auxiliary capacitance signal generation circuit 201 may be provided outside the display control circuit 200.
  • the polarity of the video signal is inverted for each gate line.
  • the polarity of the video signal may be inverted for a plurality of gate lines.
  • the polarity of the video signal is inverted for each source line.
  • the polarity of the video signal may be inverted for each of a plurality of source lines.
  • the CS line is formed as a transparent electrode.
  • the present invention is not limited to this.
  • the CS line is replaced with a gate line or the like, similar to the second implementation example in the first embodiment and the second implementation example in the second embodiment.
  • the same material may be used. However, in this case, it is desirable to pay sufficient attention to the decrease in aperture ratio.
  • the rest period T2 is the same as the scanning period T1, but may be shorter than the scanning period T1.
  • CS driving type liquid crystal display device that reduces power consumption while reducing the frame area, and a driving method thereof.
  • the present invention can be applied to a CS drive type liquid crystal display device.
  • Source driver (video signal line drive circuit) 400 Gate driver (scanning signal line driving circuit) P (i, j) ... pixel formation part Ep (i, j) ... pixel electrode Vp (i, j) ... pixel potential GLi ... gate line (scanning signal line) SLj ... Source line (video signal line) Ccs ... auxiliary capacitors CSa, CSb ... first and second auxiliary capacitance signals SS (j) ... video signal T1 ... scanning period T2 ... rest period

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Provided is a liquid-crystal display device that uses a storage-capacitance drive method and has reduced border area and power consumption. Said liquid-crystal display device uses a low-frequency refresh with an idle period after each scanning period, and a storage-capacitance line (CL1-CLm) is laid out along each gate line (GL1-GLm). In each pixel-formation unit, a storage capacitance (Ccs) is formed between the pixel electrode of said pixel-formation unit and the storage-capacitance line laid out along the gate line connected to the gate terminal of the thin-film transistor (50) of said pixel-formation unit. A display control circuit provides a first storage-capacitance signal (CSa) and a second storage-capacitance signal (CSb) to the odd- and even-numbered storage-capacitance lines, respectively. When an idle period begins, the first storage-capacitance signal (CSa) changes to a high potential from the low potential said signal exhibits during the scanning periods (T1), and the second storage-capacitance signal (CSb) changes to a low potential from the high potential said signal exhibits during the scanning periods (T1).

Description

液晶表示装置およびその駆動方法Liquid crystal display device and driving method thereof
　本発明は、液晶表示装置およびその駆動方法に関し、特に、所定のタイミングで液晶表示装置内の補助容量線の電位を変化させる液晶表示装置およびその駆動方法に関する。 The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device that changes the potential of an auxiliary capacitance line in a liquid crystal display device at a predetermined timing and a driving method thereof.
　従来から、アクティブマトリクス型の液晶表示装置に関して低消費電力化が求められている。この低消費電力化を図る方法の１つとして、各ゲートライン（走査信号線）の選択期間終了後に、対応する補助容量線の電位を変化させる駆動方法が知られている。以下では、このような駆動方式を「ＣＳ駆動方式」という。このＣＳ駆動方式は一般的に、液晶表示装置内に、各ＣＳライン（上記補助容量線）の電位を順次変化させるためのＣＳドライバ（補助容量線駆動回路）を表示部（パネル）の額縁部に設けることにより実現される。このＣＳドライバは、例えばシフトレジスタ等を用いて構成されている。このようなＣＳ駆動方式によれば、小さな映像信号振幅で液晶層に大きな電圧を加えることができるので、消費電力を低減することができる。このような駆動方法は、例えば特許文献１に開示されている。 Conventionally, low power consumption is required for active matrix liquid crystal display devices. As one method for reducing the power consumption, a driving method is known in which the potential of the corresponding auxiliary capacitance line is changed after the selection period of each gate line (scanning signal line) is completed. Hereinafter, such a driving method is referred to as a “CS driving method”. This CS driving method generally includes a CS driver (auxiliary capacitance line driving circuit) for sequentially changing the potential of each CS line (the auxiliary capacitance line) in a liquid crystal display device. It is realized by providing it. The CS driver is configured using, for example, a shift register. According to such a CS driving method, a large voltage can be applied to the liquid crystal layer with a small video signal amplitude, so that power consumption can be reduced. Such a driving method is disclosed in Patent Document 1, for example.
　また、特許文献２には、複数本のＣＳライン（補助容量配線）を複数（例えば４個）のグループにグループ化し、各グループに含まれるＣＳラインを複数本ずつまとめて駆動する液晶表示装置が開示されている。このような構成により、ＣＳドライバ（補助容量ドライバ）を簡易な構成にすることができる。 Patent Document 2 discloses a liquid crystal display device in which a plurality of CS lines (auxiliary capacitance lines) are grouped into a plurality (for example, four) groups, and a plurality of CS lines included in each group are collectively driven. It is disclosed. With this configuration, the CS driver (auxiliary capacitor driver) can be simplified.
日本の特開平５－１４３０２１号公報Japanese Unexamined Patent Publication No. 5-143021 日本の特開２００９－７５４１８号公報Japanese Unexamined Patent Publication No. 2009-75418 日本の特開２００１－３１２２５３号公報Japanese Unexamined Patent Publication No. 2001-31253
　しかし、特許文献１，２に記載の液晶表示装置のいずれにおいても、ＣＳラインを駆動するためのＣＳドライバが必要になる。このため、額縁面積が大きくなる。 However, in any of the liquid crystal display devices described in Patent Documents 1 and 2, a CS driver for driving the CS line is required. For this reason, a frame area becomes large.
　そこで、本発明は、額縁面積を縮小しつつ消費電力を低減したＣＳ駆動方式の液晶表示装置およびその駆動方法を提供することを目的とする。 Therefore, an object of the present invention is to provide a CS driving type liquid crystal display device that reduces power consumption while reducing the frame area, and a driving method thereof.
　本発明の第１の局面は、液晶表示装置であって、
　複数の映像信号線と、前記複数の映像信号線と交差する複数の走査信号線と、前記複数の映像信号線および前記複数の走査信号線に対応してマトリクス状に配置された複数の画素電極と、前記複数の映像信号線または前記複数の走査信号線のいずれかである複数の所定の信号線に沿って配置された複数の補助容量線と、各画素電極と前記複数の補助容量線のいずれかとの間に形成される補助容量とを含む表示部と、
　前記複数の走査信号線が順次選択される走査期間と前記複数の走査信号線のいずれもが非選択状態になる休止期間とが、前記走査期間と前記休止期間とからなるフレーム期間を周期として交互に現れるように、前記複数の走査信号線を駆動するための走査信号線駆動回路と、
　前記複数の映像信号線を介して前記複数の画素電極に映像信号を与えると共に、前記走査期間において、当該映像信号の極性を互いに異なる第１極性または第２極性のいずれかにする映像信号線駆動回路と、
　各補助容量線に与えるべき補助容量信号を生成し、前記第１極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位と、前記第２極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位とを互いに異ならせると共に、前記休止期間において各補助容量線に与えるべき補助容量信号の電位を、当該休止期間の直前の走査期間において当該補助容量線に与えるべき当該補助容量信号の電位と異ならせる補助容量信号生成回路を備えることを特徴とする。 A first aspect of the present invention is a liquid crystal display device,
A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of video signal lines and the plurality of scanning signal lines A plurality of auxiliary capacitance lines arranged along a plurality of predetermined signal lines which are either the plurality of video signal lines or the plurality of scanning signal lines, and each pixel electrode and the plurality of auxiliary capacitance lines. A display unit including an auxiliary capacitor formed between the two,
A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle. A scanning signal line driving circuit for driving the plurality of scanning signal lines, as shown in FIG.
A video signal line drive that applies a video signal to the plurality of pixel electrodes via the plurality of video signal lines and sets the video signal to have a first polarity or a second polarity different from each other in the scanning period. Circuit,
A storage capacitor signal to be applied to each storage capacitor line is generated, and a potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the first polarity video signal is applied. And the potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the video signal of the second polarity is applied and An auxiliary capacitance signal generation circuit is provided that makes the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period. .
　本発明の第２の局面は、本発明の第１の局面において、
　前記休止期間は前記走査期間よりも長いことを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The pause period is longer than the scanning period.
　本発明の第３の局面は、本発明の第１の局面において、
　前記所定の信号線は前記走査信号線であり、
　前記補助容量は、各走査信号線に対応する画素電極と、当該走査信号線に沿う補助容量線との間に形成され、
　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、所定数の前記走査信号線がそれぞれ選択状態になる当該所定数の選択期間毎に反転させることを特徴とする。 According to a third aspect of the present invention, in the first aspect of the present invention,
The predetermined signal line is the scanning signal line;
The auxiliary capacitance is formed between a pixel electrode corresponding to each scanning signal line and an auxiliary capacitance line along the scanning signal line,
In the scanning period, the video signal line driving circuit selects the predetermined number of the scanning signal lines to select the polarity of the plurality of video signals to be applied to the plurality of video signal lines, respectively. It is characterized by inversion every period.
　本発明の第４の局面は、本発明の第１の局面において、
　前記所定の信号線は前記映像信号線であり、
　前記補助容量は、各映像信号線に対応する画素電極と、当該映像信号線に沿う補助容量線との間に形成され、
　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、所定数の前記映像信号線毎に反転させることを特徴とする。 According to a fourth aspect of the present invention, in the first aspect of the present invention,
The predetermined signal line is the video signal line;
The auxiliary capacitance is formed between a pixel electrode corresponding to each video signal line and an auxiliary capacitance line along the video signal line,
The video signal line driving circuit reverses the polarity of the plurality of video signals to be given to the plurality of video signal lines for each of a predetermined number of the video signal lines in the scanning period.
　本発明の第５の局面は、本発明の第４の局面において、
　前記映像信号線駆動回路の配置位置側から数えて奇数番目の走査信号線に対応する画素電極と、当該画素電極に前記映像信号線の延伸する方向に並び、かつ、前記映像信号線駆動回路の配置位置側から数えて偶数番目の走査信号線に対応する画素電極とは、互いに隣接する映像信号線にそれぞれ対応することを特徴とする。 According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
A pixel electrode corresponding to an odd-numbered scanning signal line counted from the arrangement position side of the video signal line driving circuit, arranged in the direction in which the video signal line extends to the pixel electrode, and of the video signal line driving circuit The pixel electrodes corresponding to the even-numbered scanning signal lines counted from the arrangement position side correspond to the video signal lines adjacent to each other.
　本発明の第６の局面は、本発明の第１の局面において、
　前記所定の信号線は前記走査信号線であり、
　前記補助容量は、各走査信号線に対応する画素電極のうちの、前記走査信号線駆動回路の配置位置側から数えて奇数番目の映像信号線に対応する画素電極と、当該走査信号線に沿う補助容量線との間に形成されると共に、各走査信号線に対応する画素電極のうちの、前記走査信号線駆動回路の配置位置側から数えて偶数番目の映像信号線に対応する画素電極と、当該走査信号線の先行の走査信号線に沿う補助容量線との間に形成され、
　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、各走査信号線が選択状態になる選択期間毎に反転させると共に、映像信号線毎に反転させることを特徴とする。 According to a sixth aspect of the present invention, in the first aspect of the present invention,
The predetermined signal line is the scanning signal line;
The auxiliary capacitor includes a pixel electrode corresponding to an odd-numbered video signal line counted from an arrangement position side of the scanning signal line driving circuit among pixel electrodes corresponding to each scanning signal line, and along the scanning signal line. Among the pixel electrodes corresponding to each scanning signal line, the pixel electrodes corresponding to the even-numbered video signal lines counted from the arrangement position side of the scanning signal line driving circuit, , The auxiliary capacitance line along the scanning signal line preceding the scanning signal line,
The video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. It is characterized in that each signal line is inverted.
　本発明の第７の局面は、本発明の第１の局面において、
　前記所定の信号線は前記映像信号線であり、
　前記補助容量は、各映像信号線に対応する画素電極のうちの、前記映像信号線駆動回路の配置位置側から数えて奇数番目の走査信号線に対応する画素電極と、当該映像信号線に沿う補助容量線との間に形成されると共に、各映像信号線に対応する画素電極のうちの、前記映像信号線駆動回路の配置位置側から数えて偶数番目の走査信号線に対応する画素電極と、当該映像信号線の先行の映像信号線に沿う補助容量線との間に形成され、
　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、各走査信号線が選択状態になる選択期間毎に反転させると共に、映像信号線毎に反転させることを特徴とする。 According to a seventh aspect of the present invention, in the first aspect of the present invention,
The predetermined signal line is the video signal line;
The auxiliary capacitor includes pixel electrodes corresponding to odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit among pixel electrodes corresponding to the video signal lines, and along the video signal lines. Among the pixel electrodes corresponding to each video signal line, the pixel electrodes corresponding to even-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit, , Formed between the auxiliary capacitance line along the preceding video signal line of the video signal line,
The video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. It is characterized in that each signal line is inverted.
　本発明の第８の局面は、本発明の第１の局面において、
　前記映像信号線駆動回路は、各走査信号線が選択状態になる選択期間での前記複数の映像信号の振幅を前記走査期間の開始時点から終了時点にかけて小さくすることを特徴とする。 According to an eighth aspect of the present invention, in the first aspect of the present invention,
The video signal line driving circuit is characterized in that the amplitude of the plurality of video signals in a selection period in which each scanning signal line is in a selected state is reduced from the start time to the end time of the scanning period.
　本発明の第９の局面は、本発明の第１の局面から第８の局面までのいずれかにおいて、
　各補助容量線は、透明電極として形成されていることを特徴とする。 According to a ninth aspect of the present invention, in any one of the first to eighth aspects of the present invention,
Each auxiliary capacitance line is formed as a transparent electrode.
　本発明の第１０の局面は、本発明の第１の局面から第４の局面までのいずれかにおいて、
　各補助容量線は、当該補助容量線の沿う前記所定の信号線と同一材料の電極として形成されていることを特徴とする。 According to a tenth aspect of the present invention, in any one of the first to fourth aspects of the present invention,
Each auxiliary capacitance line is formed as an electrode of the same material as the predetermined signal line along the auxiliary capacitance line.
　本発明の第１１の局面は、本発明の第１の局面から第１０の局面までのいずれかにおいて、
　前記表示部は、各画素電極に対応する前記走査信号線がゲート端子に接続され、半導体層が酸化物半導体により形成された薄膜トランジスタをさらに含み、
　前記映像信号線と当該映像信号線に対応する前記画素電極とは、当該画素電極に対応する前記走査信号線が前記ゲート端子に接続された前記薄膜トランジスタを介して接続されていることを特徴とする。 An eleventh aspect of the present invention is any one of the first to tenth aspects of the present invention,
The display unit further includes a thin film transistor in which the scanning signal line corresponding to each pixel electrode is connected to a gate terminal, and a semiconductor layer is formed of an oxide semiconductor,
The video signal line and the pixel electrode corresponding to the video signal line are connected via the thin film transistor in which the scanning signal line corresponding to the pixel electrode is connected to the gate terminal. .
　本発明の第１２の局面は、複数の映像信号線、前記複数の映像信号線と交差する複数の走査信号線、前記複数の映像信号線および前記複数の走査信号線に対応してマトリクス状に配置された複数の画素電極、前記複数の映像信号線または前記複数の走査信号線のいずれかである複数の所定の信号線に沿って配置された複数の補助容量線、および各画素電極と前記複数の補助容量線のいずれかとの間に形成される補助容量を含む表示部と、前記複数の走査信号線を駆動するための走査信号線駆動回路と、前記複数の映像信号線を介して前記複数の画素電極に映像信号を与える映像信号線駆動回路と、各補助容量線に与えるべき補助容量信号を生成する補助容量信号生成回路とを備える表示装置の駆動方法であって、
　前記複数の走査信号線が順次選択される走査期間と前記複数の走査信号線のいずれもが非選択状態になる休止期間とが、前記走査期間と前記休止期間とからなるフレーム期間を周期として交互に現れるように、前記複数の走査信号線を駆動するステップと、
　前記走査期間において、前記映像信号の極性を互いに異なる第１極性または第２極性のいずれかにするステップと、
　前記第１極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位と、前記第２極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位とを互いに異ならせると共に、前記休止期間において各補助容量線に与えるべき補助容量信号の電位を、当該休止期間の直前の走査期間において当該補助容量線に与えるべき当該補助容量信号の電位と異ならせるステップとを備えることを特徴とする。 According to a twelfth aspect of the present invention, a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of scanning signal lines are arranged in a matrix. A plurality of pixel electrodes arranged, a plurality of auxiliary capacitance lines arranged along a plurality of predetermined signal lines which are any of the plurality of video signal lines or the plurality of scanning signal lines, and each pixel electrode and the A display unit including an auxiliary capacitance formed between any of the plurality of auxiliary capacitance lines; a scanning signal line driving circuit for driving the plurality of scanning signal lines; and the video signal lines through the video signal lines. A driving method for a display device, comprising: a video signal line driving circuit for supplying video signals to a plurality of pixel electrodes; and an auxiliary capacitance signal generating circuit for generating an auxiliary capacitance signal to be given to each auxiliary capacitance line,
A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle. Driving the plurality of scanning signal lines, as shown in FIG.
In the scanning period, the video signal has a polarity that is either a first polarity or a second polarity different from each other;
A potential of the auxiliary capacitance signal to be applied to the auxiliary capacitance line in which the auxiliary capacitance is formed between the pixel electrode to which the first polarity video signal is applied and a pixel to which the second polarity video signal is applied. The storage capacitor signal potential to be applied to the storage capacitor line in which the storage capacitor is formed between the electrodes is different from each other, and the storage capacitor signal potential to be applied to each storage capacitor line in the pause period is And a step of making the potential different from the potential of the auxiliary capacitance signal to be applied to the auxiliary capacitance line in the scanning period immediately before the pause period.
　本発明の第１３の局面は、本発明の第１２の局面において、前記休止期間は前記走査期間よりも長いことを特徴とする。 A thirteenth aspect of the present invention is the twelfth aspect of the present invention, wherein the pause period is longer than the scanning period.
　本発明の第１４の局面は、本発明の第１２の局面において、各走査信号線が選択状態になる選択期間での前記複数の映像信号の振幅を前記走査期間の開始時点から終了時点にかけて小さくするステップをさらに備えることを特徴とする。 According to a fourteenth aspect of the present invention, in the twelfth aspect of the present invention, the amplitude of the plurality of video signals in the selection period in which each scanning signal line is in a selected state is reduced from the start point to the end point of the scanning period. The method further comprises the step of:
　本発明の第１の局面によれば、走査期間の後に休止期間を設けたいわゆる低周波リフレッシュ駆動が行われる液晶表示装置において、ＣＳ駆動が行われる。このＣＳ駆動は従来と異なり、休止期間において各補助容量線に与えるべき補助容量信号の電位を、当該休止期間の直前の走査期間において当該補助容量線に与えるべき当該補助容量信号の電位と異ならせる補助容量信号生成回路により行われる。この補助容量信号生成回路は、従来のＣＳドライバのようには各補助容量線の電位を順次変化させずに、休止期間において各補助容量線（補助容量信号）の電位を一括で変化させるので、従来のＣＳドライバよりも回路規模が小さい。このため、額縁面積を縮小しつつ消費電力を低減することができる。また、低周波リフレッシュ駆動が行われるので、さらなる低消費電力化を図ることができる。 According to the first aspect of the present invention, CS driving is performed in a liquid crystal display device that performs so-called low-frequency refresh driving in which a rest period is provided after the scanning period. In the CS drive, unlike the prior art, the potential of the auxiliary capacitance signal to be given to each auxiliary capacitance line in the pause period is made different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period. This is performed by an auxiliary capacitance signal generation circuit. This auxiliary capacitance signal generation circuit changes the potential of each auxiliary capacitance line (auxiliary capacitance signal) in a pause period without sequentially changing the potential of each auxiliary capacitance line unlike the conventional CS driver. The circuit scale is smaller than that of a conventional CS driver. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
　本発明の第２の局面によれば、休止期間が走査期間よりも長く設けられるので、さらなる消費電力化を図ることができる。 According to the second aspect of the present invention, since the pause period is longer than the scanning period, further power consumption can be achieved.
　本発明の第３の局面によれば、補助容量が、各走査信号線に対応する画素電極と当該走査信号線に沿う補助容量線との間に形成される。また、走査期間において、複数の映像信号線にそれぞれ与えられるべき複数の映像信号の極性が所定数の走査信号線がそれぞれ選択状態になる所定数の選択期間毎に反転する。このため、所定数の走査信号線単位でライン反転駆動を行うことができる。 According to the third aspect of the present invention, the storage capacitor is formed between the pixel electrode corresponding to each scanning signal line and the storage capacitor line along the scanning signal line. In the scanning period, the polarities of the plurality of video signals to be applied to the plurality of video signal lines are inverted every predetermined number of selection periods in which the predetermined number of scanning signal lines are selected. Therefore, line inversion driving can be performed in units of a predetermined number of scanning signal lines.
　本発明の第４の局面によれば、補助容量が、各映像信号線に対応する画素電極と当該映像信号線に沿う補助容量線との間に形成される。また、走査期間において、複数の映像信号線にそれぞれ与えられるべき複数の映像信号の極性が所定数の映像信号線毎に反転する。このため、所定数の映像信号線単位でライン反転駆動を行うことができる。 According to the fourth aspect of the present invention, the storage capacitor is formed between the pixel electrode corresponding to each video signal line and the storage capacitor line along the video signal line. Further, in the scanning period, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted every predetermined number of video signal lines. Therefore, line inversion driving can be performed in units of a predetermined number of video signal lines.
　本発明の第５の局面によれば、映像信号線の延伸する方向に並んだ、映像信号線駆動回路の配置位置側から数えて奇数番目に対応する画素電極と、映像信号線駆動回路の配置位置側から数えて偶数番目に対応する画素電極とが互いに隣接する映像信号線にそれぞれ対応する。このため、複数の映像信号線にそれぞれ与えるべき複数の映像信号の極性が、各走査信号線が選択状態になる選択期間毎に反転する。これにより、いわゆるドット反転駆動を行うことができる。 According to the fifth aspect of the present invention, the pixel electrodes corresponding to the odd-numbered pixels counted from the arrangement position side of the video signal line driving circuit, arranged in the extending direction of the video signal line, and the arrangement of the video signal line driving circuit The pixel electrodes corresponding to the even-numbered pixels counted from the position side correspond to the video signal lines adjacent to each other. For this reason, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted every selection period in which each scanning signal line is selected. Thereby, so-called dot inversion driving can be performed.
　本発明の第６の局面によれば、補助容量が、各走査信号線に対応する画素電極のうちの、走査信号線駆動回路の配置位置側から数えて奇数番目の映像信号線に対応する画素電極と、当該走査信号線に沿う補助容量線との間に形成されると共に、各走査信号線に対応する画素電極のうちの、走査信号線駆動回路の配置位置側から数えて偶数番目の映像信号線に対応する画素電極と、当該走査信号線の先行の走査信号線に沿う補助容量線との間に形成される。また、走査期間において、複数の映像信号線にそれぞれ与えるべき複数の映像信号の極性が、各走査信号線が選択状態になる選択期間毎に反転すると共に、映像信号線毎に反転する。このため、いわゆるドット反転駆動を行うことができる。 According to the sixth aspect of the present invention, the auxiliary capacitor is a pixel corresponding to an odd-numbered video signal line counted from the arrangement position side of the scanning signal line driving circuit among the pixel electrodes corresponding to each scanning signal line. An even-numbered image that is formed between the electrode and the auxiliary capacitance line along the scanning signal line and counted from the arrangement position side of the scanning signal line driving circuit among the pixel electrodes corresponding to each scanning signal line It is formed between the pixel electrode corresponding to the signal line and the auxiliary capacitance line along the scanning signal line preceding the scanning signal line. Further, in the scanning period, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted for each selection period in which each scanning signal line is selected, and are inverted for each video signal line. For this reason, so-called dot inversion driving can be performed.
　本発明の第７の局面によれば、補助容量が、各映像信号線に対応する画素電極のうちの、映像信号線駆動回路の配置位置側から数えて奇数番目の走査信号線に対応する画素電極と、当該映像信号線に沿う補助容量線との間に形成されると共に、各映像信号線に対応する画素電極のうちの、映像信号線駆動回路の配置位置側から数えて偶数番目の走査信号線に対応する画素電極と、当該映像信号線の先行の映像信号線に沿う補助容量線との間に形成される。また、走査期間において、複数の映像信号線にそれぞれ与えるべき複数の映像信号の極性が、各走査信号線が選択状態になる選択期間毎に反転すると共に、映像信号線毎に反転する。このため、いわゆるドット反転駆動を行うことができる。 According to the seventh aspect of the present invention, among the pixel electrodes corresponding to the video signal lines, the auxiliary capacitors correspond to the odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit. An even-numbered scan of the pixel electrodes corresponding to each video signal line from the arrangement position side of the video signal line drive circuit, formed between the electrode and the auxiliary capacitance line along the video signal line. It is formed between the pixel electrode corresponding to the signal line and the auxiliary capacitance line along the video signal line preceding the video signal line. Further, in the scanning period, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted for each selection period in which each scanning signal line is selected, and are inverted for each video signal line. For this reason, so-called dot inversion driving can be performed.
　本発明の第８の局面によれば、各選択期間での前記複数の映像信号の振幅が走査期間の開始時点から終了時点にかけて小さくなる。最初の選択期間から最後の選択期間にかけて映像信号の振幅が小さくなる。このため、走査期間において選択状態になるタイミングが早い走査信号線であるほど、当該走査信号線に対応する画素形成部の画素電位が高くなり、走査期間において選択状態になるタイミングが遅い走査信号線であるほど、当該走査信号線に対応する画素形成部の画素電位が低くなる。これにより、各走査信号線に対応する画素電極における１フレーム分の実効電圧の齟齬が低減される。したがって、表示品位の低下を抑制することができる。 According to the eighth aspect of the present invention, the amplitude of the plurality of video signals in each selection period decreases from the start point to the end point of the scanning period. The amplitude of the video signal decreases from the first selection period to the last selection period. For this reason, the scanning signal line that is earlier in the selection state in the scanning period has a higher pixel potential in the pixel formation portion corresponding to the scanning signal line, and the scanning signal line that has the later timing in the selection period in the scanning period. The lower the pixel potential of the pixel formation portion corresponding to the scanning signal line is, Thereby, the effective voltage drop for one frame in the pixel electrode corresponding to each scanning signal line is reduced. Accordingly, it is possible to suppress a decrease in display quality.
　本発明の第９の局面によれば、各補助容量線が透明電極として形成される。このため、開口率の低下を抑制することができる。 According to the ninth aspect of the present invention, each auxiliary capacitance line is formed as a transparent electrode. For this reason, the fall of an aperture ratio can be suppressed.
　本発明の第１０の局面によれば、各補助容量線が所定の信号線と同一材料の電極として形成される。このため、補助容量線と当該所定の信号線とを同じ工程で形成できるので、コストを低減することができる。 According to the tenth aspect of the present invention, each auxiliary capacitance line is formed as an electrode made of the same material as a predetermined signal line. For this reason, since the auxiliary capacitance line and the predetermined signal line can be formed in the same process, the cost can be reduced.
　本発明の第１１の局面によれば、酸化物半導体により半導体層が形成された薄膜トランジスタが各画素電極に対応して設けられる。このため、画素電位を長時間保持できるので、休止期間を十分に長くできる。また、画素電極への映像信号の書き込みを高速化できるので、走査期間を十分に短くできる。これにより、低周波リフレッシュ駆動を行いつつ、フレーム周波数（１フレーム期間における駆動周波数）の低下を抑制することができる。 According to the eleventh aspect of the present invention, a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor is provided corresponding to each pixel electrode. For this reason, since the pixel potential can be held for a long time, the pause period can be made sufficiently long. In addition, since the writing of the video signal to the pixel electrode can be speeded up, the scanning period can be sufficiently shortened. Thereby, it is possible to suppress a decrease in the frame frequency (driving frequency in one frame period) while performing the low-frequency refresh driving.
　本発明の第１２の局面から第１４の局面までによれば、液晶表示装置の駆動方法において、本発明の第１の局面、第２の局面、および第８の局面とそれぞれ同様の効果を奏することができる。 According to the twelfth to fourteenth aspects of the present invention, the driving method of the liquid crystal display device has the same effects as the first aspect, the second aspect, and the eighth aspect of the present invention, respectively. be able to.
本発明の第１の実施形態に係る液晶表示装置の全体構成を示すブロック図である。1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. 上記第１の実施形態における画素形成部の構成を示す回路図である。FIG. 3 is a circuit diagram illustrating a configuration of a pixel formation unit in the first embodiment. 上記第１の実施形態における表示部の構成を示す回路図である。It is a circuit diagram which shows the structure of the display part in the said 1st Embodiment. 上記第１の実施形態に係る液晶表示装置の動作を示す信号波形図である。It is a signal waveform diagram which shows operation | movement of the liquid crystal display device which concerns on the said 1st Embodiment. 上記第１の実施形態における画素レイアウトの第１の実現例を示す平面図である。It is a top view which shows the 1st implementation example of the pixel layout in the said 1st Embodiment. 図５におけるＡ－Ａ’線断面図である。FIG. 6 is a cross-sectional view taken along line A-A ′ in FIG. 5. 上記第１の実施形態における画素レイアウトの第２の実現例を示す平面図である。It is a top view which shows the 2nd implementation example of the pixel layout in the said 1st Embodiment. 図７におけるＢ－Ｂ’線断面図である。FIG. 8 is a sectional view taken along line B-B ′ in FIG. 7. ａ－ＳｉＴＦＴおよびＩＧＺＯＴＦＴのドレイン電流－ゲート電圧特性を示す図である。It is a figure which shows the drain current-gate voltage characteristic of a-SiTFT and IGZOTFT. 本発明の第２の実施形態における表示部の構成を示す回路図である。It is a circuit diagram which shows the structure of the display part in the 2nd Embodiment of this invention. 上記第２の実施形態に係る液晶表示装置の動作を示す信号波形図である。It is a signal waveform diagram which shows operation | movement of the liquid crystal display device which concerns on the said 2nd Embodiment. 上記第２の実施形態における画素レイアウトの第１の実現例を示す平面図である。It is a top view which shows the 1st implementation example of the pixel layout in the said 2nd Embodiment. 図１２におけるＣ－Ｃ’線断面図である。FIG. 13 is a sectional view taken along line C-C ′ in FIG. 12. 上記第２の実施形態における画素レイアウトの第２の実現例を示す平面図である。It is a top view which shows the 2nd implementation example of the pixel layout in the said 2nd Embodiment. 図１４におけるＤ－Ｄ’線断面図である。FIG. 15 is a sectional view taken along line D-D ′ in FIG. 14. 本発明の第３の実施形態における表示部の構成を示す回路図である。It is a circuit diagram which shows the structure of the display part in the 3rd Embodiment of this invention. 上記第３の実施形態に係る液晶表示装置の動作を示す信号波形図である。It is a signal waveform diagram which shows operation | movement of the liquid crystal display device which concerns on the said 3rd Embodiment. 上記第３の実施形態における画素レイアウトの実現例を示す平面図である。It is a top view which shows the implementation example of the pixel layout in the said 3rd Embodiment. 上記第３の実施形態の第１の変形例における表示部の構成を示す回路図である。It is a circuit diagram which shows the structure of the display part in the 1st modification of the said 3rd Embodiment. 上記第３の実施形態の第１の変形例における画素レイアウトの実現例を示す平面図である。It is a top view which shows the implementation example of the pixel layout in the 1st modification of the said 3rd Embodiment. 上記第３の実施形態の第２の変形例における表示部の構成を示す回路図である。It is a circuit diagram which shows the structure of the display part in the 2nd modification of the said 3rd Embodiment. 上記第３の実施形態の第２の変形例における画素レイアウトの実現例を示す平面図である。It is a top view which shows the implementation example of the pixel layout in the 2nd modification of the said 3rd Embodiment. 本発明の第４の実施形態における液晶表示装置の動作を示す信号波形図である。It is a signal waveform diagram which shows the operation | movement of the liquid crystal display device in the 4th Embodiment of this invention.
　以下、添付図面を参照しながら、本発明の実施形態について説明する。
　＜１．第１の実施形態＞
　＜１．１　全体構成＞
　図１は、本発明の第１の実施形態に係る、ＣＳ駆動方式を採用したアクティブマトリクス型の液晶表示装置の全体構成を示すブロック図である。図１に示すように、この液晶表示装置は、電源１００、ＤＣ／ＤＣコンバータ１１０、表示制御回路２００、ソースドライバ（映像信号線駆動回路）３００、ゲートドライバ（走査信号線駆動回路）４００、表示部５００、および共通電極駆動回路６００を備えている。このように、本実施形態に係る液晶表示装置には、従来のＣＳ駆動方式の液晶表示装置と異なり、表示部５００（パネル）の額縁部にＣＳドライバが設けられていない。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall configuration>
FIG. 1 is a block diagram showing an overall configuration of an active matrix type liquid crystal display device adopting a CS driving method according to a first embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device includes a power supply 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a display. Part 500 and common electrode driving circuit 600. Thus, unlike the conventional CS driving type liquid crystal display device, the liquid crystal display device according to this embodiment does not include a CS driver in the frame portion of the display unit 500 (panel).
　表示部５００には、ｎ本のソースライン（映像信号線）ＳＬ１～ＳＬｎ、ｍ本のゲートライン（走査信号線）ＧＬ１～ＧＬｍ、ｍ本のゲートラインＧＬ１～ＧＬｍにそれぞれ沿って配置されたｍ本のＣＳライン（補助容量線）ＣＬ１～ＣＬｍ、およびこれらのソースラインＳＬ１～ＳＬｎとゲートラインＧＬ１～ＧＬｍとの交差点にそれぞれ対応して設けられた複数（ｍ×ｎ個）の画素形成部が形成されている。ここで、ｍおよびｎは偶数であるものとするが、本発明はこれに限定されるものではない。これらのｍ×ｎ個の画素形成部は、マトリクス状に配置されることにより画素アレイを構成している。 The display unit 500 includes m source lines (video signal lines) SL1 to SLn, m gate lines (scanning signal lines) GL1 to GLm, and m gate lines GL1 to GLm. A plurality of (m × n) pixel formation portions provided corresponding to the intersections of the CS lines (auxiliary capacitance lines) CL1 to CLm and the source lines SL1 to SLn and the gate lines GL1 to GLm, respectively. Is formed. Here, m and n are assumed to be even numbers, but the present invention is not limited to this. These m × n pixel forming portions are arranged in a matrix to form a pixel array.
　図２は、本実施形態における各画素形成部の構成を示す回路図である。この図２では、ｉ行ｊ列目の画素形成部を例示している（ｉ＝１～ｍ、ｊ＝１～ｎ）。以下では、ｉ行ｊ列目の画素形成部に符号Ｐ（ｉ，ｊ）を付す。また、画素形成部以外の構成要素についても、ｉ行目、ｊ列目、およびｉ行ｊ列目の構成要素をそれぞれ「ｉ行目の」、「ｊ列目の」、および「ｉ行ｊ列目の」の連体修飾語を用いて説明することがある。ｉ行ｊ列目の画素形成部Ｐ（ｉ，ｊ）は、対応する交差点を通過するｉ行目のゲートラインＧＬｉにゲート端子が接続されると共に当該交差点を通過するｊ行目のソースラインＳＬｊにソース端子が接続された薄膜トランジスタ５０、この薄膜トランジスタ５０のドレイン端子に接続された画素電極Ｅｐ、上記ｍ×ｎ個の画素形成部に共通的に設けられた共通電極Ｅｃ、および上記ｍ×ｎ個の画素形成部に共通的に設けられ画素電極Ｅｐと共通電極Ｅｃとの間に挟持された液晶層により構成されている。以下では、ｉ行ｊ列目の画素形成部Ｐ（ｉ，ｊ）における画素電極に符号Ｅｐ（ｉ，ｊ）を付す。また、この画素電極Ｅｐ（ｉ，ｊ）の電位を画素電位といい、符号Ｖｐ（ｉ，ｊ）を付す。画素電極Ｅｐおよび共通電極Ｅｃにより液晶容量Ｃｌｃが形成されている。また、ＣＳラインおよび画素電極Ｅｐにより補助容量Ｃｃｓが形成されている。これらの液晶容量Ｃｌｃおよび補助容量Ｃｃｓにより画素容量Ｃｐが形成されている。なお、表示部５００の構成についての詳しい説明は後述する。 FIG. 2 is a circuit diagram showing a configuration of each pixel forming portion in the present embodiment. FIG. 2 exemplifies a pixel formation portion in i-th row and j-th column (i = 1 to m, j = 1 to n). In the following, the symbol P (i, j) is given to the pixel formation portion in the i-th row and j-th column. Also, regarding the constituent elements other than the pixel formation portion, the constituent elements in the i-th row, the j-th column, and the i-th row and j-th column are respectively referred to as “i-th row”, “j-th column”, and “i-row j” The description may be made using the continuation modifier of the “column”. The pixel forming portion P (i, j) in the i-th row and j-th column has a gate terminal connected to the i-th gate line GLi passing through the corresponding intersection and the j-th source line SLj passing through the intersection. A thin film transistor 50 having a source terminal connected thereto, a pixel electrode Ep connected to a drain terminal of the thin film transistor 50, a common electrode Ec commonly provided in the m × n pixel forming portions, and the m × n number The liquid crystal layer is provided between the pixel electrode Ep and the common electrode Ec. Hereinafter, the symbol Ep (i, j) is attached to the pixel electrode in the pixel formation portion P (i, j) in the i-th row and j-th column. Further, the potential of the pixel electrode Ep (i, j) is referred to as a pixel potential, and is denoted by a reference symbol Vp (i, j). A liquid crystal capacitance Clc is formed by the pixel electrode Ep and the common electrode Ec. Further, an auxiliary capacitor Ccs is formed by the CS line and the pixel electrode Ep. A pixel capacitor Cp is formed by the liquid crystal capacitor Clc and the auxiliary capacitor Ccs. A detailed description of the configuration of the display unit 500 will be given later.
　本実施形態における薄膜トランジスタ５０の半導体層は、例えば酸化物半導体により形成されている。ただし、本発明はこれに限定されるものではなく、この半導体層は例えばアモルファスシリコン、多結晶シリコン、または微結晶シリコン等により形成されていても良い。なお、酸化物半導体を半導体層に用いた例については後述する。 The semiconductor layer of the thin film transistor 50 in this embodiment is formed of, for example, an oxide semiconductor. However, the present invention is not limited to this, and the semiconductor layer may be formed of, for example, amorphous silicon, polycrystalline silicon, or microcrystalline silicon. Note that an example in which an oxide semiconductor is used for a semiconductor layer will be described later.
　電源１００は、ＤＣ／ＤＣコンバータ１１０、表示制御回路２００、および共通電極駆動回路６００とに所定の電源電圧を供給する。ＤＣ／ＤＣコンバータ１１０は、ソースドライバ３００およびゲートドライバ４００を動作させるための所定の直流電圧を電源電圧から生成し、それを、ソースドライバ３００およびゲートドライバ４００に供給する。共通電極駆動回路６００は、共通電極Ｅｃに所定の電位Ｖｃｏｍを与える。この電位Ｖｃｏｍは典型的には固定電位である。 The power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 600. The DC / DC converter 110 generates a predetermined DC voltage for operating the source driver 300 and the gate driver 400 from the power supply voltage, and supplies it to the source driver 300 and the gate driver 400. The common electrode drive circuit 600 applies a predetermined potential Vcom to the common electrode Ec. This potential Vcom is typically a fixed potential.
　表示制御回路２００は、外部から送られる画像信号ＤＡＴおよび水平同期信号や垂直同期信号などのタイミング信号群ＴＧを受け取り、デジタル映像信号ＤＶ、表示部５００における画像表示を制御するためのソーススタートパルス信号ＳＳＰ、ソースクロック信号ＳＣＫ、ラッチストローブ信号ＬＳ、ゲートスタートパルス信号ＧＳＰ、ゲートクロック信号ＧＣＫを出力する。また、本実施形態における表示制御回路２００には補助容量信号生成回路２０１が設けられている。表示制御回路２００は、補助容量信号生成回路２０１により各画素形成部における画素電位にバイアスを掛けるための補助容量信号ＣＳを生成し出力する。この補助容量信号ＣＳは、２相の補助容量信号ＣＳａおよびＣＳｂからなっている。以下では、補助容量信号ＣＳａのことを「第１補助容量信号」といい、補助容量信号ＣＳｂのことを「第２補助容量信号」という。第１補助容量信号ＣＳａは奇数行目のＣＳラインに与えられ、第２補助容量信号ＣＳｂは偶数行目のＣＳラインに与えられる。これらの第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂはそれぞれ、補助容量信号生成回路２０１内部に設けられた２つの電源回路（図示しない）によって、例えば上述のタイミング信号群ＴＧに従ったタイミングで生成される。なお、本発明はこれに限定されるものではなく、３つ以上の電源回路を用いて第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂを生成しても良い。この場合、１つの電源回路あたりの付加が低減される。 The display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and controls a digital video signal DV and a source start pulse signal for controlling image display on the display unit 500. SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK are output. In addition, the display control circuit 200 in this embodiment is provided with an auxiliary capacitance signal generation circuit 201. The display control circuit 200 generates and outputs an auxiliary capacitance signal CS for applying a bias to the pixel potential in each pixel formation unit by the auxiliary capacitance signal generation circuit 201. This auxiliary capacitance signal CS is composed of two-phase auxiliary capacitance signals CSa and CSb. Hereinafter, the auxiliary capacitance signal CSa is referred to as a “first auxiliary capacitance signal”, and the auxiliary capacitance signal CSb is referred to as a “second auxiliary capacitance signal”. The first auxiliary capacitance signal CSa is applied to the odd-numbered CS lines, and the second auxiliary capacitance signal CSb is applied to the even-numbered CS lines. The first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb are respectively sent to two power supply circuits (not shown) provided in the auxiliary capacitance signal generation circuit 201, for example, according to the timing signal group TG described above. Is generated. The present invention is not limited to this, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb may be generated using three or more power supply circuits. In this case, the addition per power supply circuit is reduced.
　ソースドライバ３００は、表示制御回路２００から出力されるデジタル映像信号ＤＶ、ソーススタートパルス信号ＳＳＰ、ソースクロック信号ＳＣＫ、およびラッチストローブ信号ＬＳを受け取り、ソースラインＳＬ１～ＳＬｎにそれぞれ映像信号ＳＳ（１）～ＳＳ（ｎ）を印加する。 The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives the video signal SS (1) on the source lines SL1 to SLn, respectively. Apply ~ SS (n).
　ゲートドライバ４００は、表示制御回路２００から出力されるゲートスタートパルス信号ＧＳＰおよびゲートクロック信号ＧＣＫに基づいて、ハイレベル電位（各ゲートラインが選択状態になる電位）の走査信号ＧＳ（１）～ＧＳ（ｍ）のゲートラインＧＬ１～ＧＬｍそれぞれへの印加を１フレーム期間を周期として繰り返す。なお、このゲートドライバ４００の動作についての詳しい説明は後述する。 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 scans signals GS (1) to GS at a high level potential (potential at which each gate line is selected). The application of (m) to each of the gate lines GL1 to GLm is repeated with one frame period as a cycle. A detailed description of the operation of the gate driver 400 will be given later.
　以上のようにして、ソースラインＳＬ１～ＳＬｎに映像信号ＳＳ（１）～ＳＳ（ｎ）がそれぞれ印加され、ゲートラインＧＬ１～ＧＬｍに走査信号ＧＯＵＴ（１）～ＧＯＵＴ（ｍ）がそれぞれ印加されることにより、外部から送られた画像信号ＤＡＴに基づく画像が表示部５００に表示される。 As described above, the video signals SS (1) to SS (n) are applied to the source lines SL1 to SLn, respectively, and the scanning signals GOUT (1) to GOUT (m) are applied to the gate lines GL1 to GLm, respectively. As a result, an image based on the image signal DAT sent from the outside is displayed on the display unit 500.
　＜１．２　表示部の構成＞
　図３は、本実施形態における表示部５００の構成を示す回路図である。上述のように、本実施形態におけるＣＳラインＣＬ１～ＣＬｍはゲートラインＧＬ１～ＧＬｍにそれぞれ沿って配置されている。各画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタ５０のゲート端子が接続されたゲートラインに沿って配置されたＣＳラインと、当該画素形成部における画素電極Ｅｐとの間に形成されている。 <1.2 Configuration of display unit>
FIG. 3 is a circuit diagram showing a configuration of the display unit 500 in the present embodiment. As described above, the CS lines CL1 to CLm in this embodiment are arranged along the gate lines GL1 to GLm, respectively. The auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. ing.
　ソースドライバ３００が配置されている側から数えて奇数行目（以下単に「奇数行目」という）のＣＳラインＣＬ１、ＣＬ３、…ＣＬｍ－１には第１補助容量信号ＣＳａが与えられる。ソースドライバ３００が配置されている側から数えて偶数行目（以下単に「偶数行目」という）のＣＳラインＣＬ２、ＣＬ４、…ＣＬｍには第２補助容量信号ＣＳｂが与えられる。 The first auxiliary capacitance signal CSa is applied to the CS lines CL1, CL3,... CLm−1 in the odd-numbered rows (hereinafter simply referred to as “odd-numbered rows”) counted from the side where the source driver 300 is arranged. The second auxiliary capacitance signal CSb is applied to the CS lines CL2, CL4,... CLm of even-numbered rows (hereinafter simply referred to as “even-numbered rows”) counted from the side where the source driver 300 is disposed.
　＜１．３　液晶表示装置の動作＞
　図４は、本実施形態に係る液晶表示装置の動作を説明するための信号波形図である。なお、本図４、および以降の液晶表示装置の動作を説明するための信号波形図では、１行１列目の画素電位Ｖｐ（１，１）、１行２列目の画素電位Ｖｐ（１，２）、２行１列目の画素電位Ｖｐ（２，１）、およびｍ行１列目の画素電位Ｖｐ（ｍ，１）を例示している（ただし、図２３ではＶｐ（１，１）およびＶｐ（ｍ，１）のみである）。図４に示すように、本実施形態では、１フレーム期間が走査期間Ｔ１と、当該走査期間Ｔ１の後に設けられた休止期間Ｔ２とからなっている。すなわち、ゲートドライバ４００は、１フレーム期間を周期として走査期間Ｔ１および走査期間Ｔ２が交互に現れるようにｍ本のゲートラインＧＬ１～ＧＬｍを駆動する。走査期間Ｔ１では走査信号ＧＳ（１）～ＧＳ（ｍ）がゲートクロック信号ＧＣＫに基づいて順次にハイレベル電位になる。一方休止期間Ｔ２では、ｍ本のゲートラインＧＬ１～ＧＬｍ（走査信号ＧＳ（１）～ＧＳ（ｍ））のいずれもが非選択状態（ローレベル電位）になっている。このように走査期間Ｔ１の後に休止期間Ｔ２を設けることにより行う駆動は「低周波リフレッシュ駆動」と呼ばれ、例えば特許文献３に開示されている。本実施形態では、走査期間Ｔ１の長さは８．３ｍｓｅｃであり、休止期間Ｔ２の長さは９９１．７ｍｓｅｃである。すなわち、休止期間Ｔ２は走査期間Ｔ１よりも長い。 <1.3 Operation of liquid crystal display device>
FIG. 4 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment. In FIG. 4 and signal waveform diagrams for explaining the operation of the subsequent liquid crystal display device, the pixel potential Vp (1,1) in the first row and the first column, the pixel potential Vp (1 in the first row and the second column). , 2) The pixel potential Vp (2,1) in the second row and the first column and the pixel potential Vp (m, 1) in the mth row and the first column are illustrated (in FIG. 23, however, Vp (1,1) ) And Vp (m, 1) only). As shown in FIG. 4, in the present embodiment, one frame period is composed of a scanning period T1 and a pause period T2 provided after the scanning period T1. That is, the gate driver 400 drives the m gate lines GL1 to GLm so that the scanning period T1 and the scanning period T2 appear alternately with one frame period as a cycle. In the scanning period T1, the scanning signals GS (1) to GS (m) are sequentially set to the high level potential based on the gate clock signal GCK. On the other hand, in the suspension period T2, all of the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) are in a non-selected state (low level potential). The driving performed by providing the pause period T2 after the scanning period T1 is called “low frequency refresh driving”, and is disclosed in, for example, Patent Document 3. In the present embodiment, the length of the scanning period T1 is 8.3 msec, and the length of the pause period T2 is 991.7 msec. That is, the pause period T2 is longer than the scanning period T1.
　＜１．３．１　走査期間での動作＞
　図４に示すように、走査期間Ｔ１における第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂはそれぞれ、互いに異なる電位である低電位Ｖｌおよび高電位Ｖｈになっている。すなわち、奇数行目のＣＳラインは低電位Ｖｌに、偶数行目のＣＳラインは高電位Ｖｈになっている。映像信号ＳＳ（１）～ＳＳ（ｎ）は１水平走査期間毎に正極性（第１極性）と負極性（第２極性）とを繰り返すと共に、各水平走査期間において互いに同じ極性になっている。また、これらの映像信号ＳＳ（１）～ＳＳ（ｎ）の極性は、１フレーム期間毎に反転する。なお、この１フレーム期間毎の映像信号ＳＳ（１）～ＳＳ（ｎ）の極性の反転は以下の各実施形態および変形例でも同様に行われる。以下の説明では、１～ｍ行目のゲートラインＧＬ１～ＧＬｍが選択状態になる水平走査期間をそれぞれ「第１～ｍ選択期間」という。 <1.3.1 Operation in Scanning Period>
As shown in FIG. 4, the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh. The video signals SS (1) to SS (n) repeat positive polarity (first polarity) and negative polarity (second polarity) every horizontal scanning period, and have the same polarity in each horizontal scanning period. . The polarities of these video signals SS (1) to SS (n) are inverted every frame period. The polarity inversion of the video signals SS (1) to SS (n) for each frame period is similarly performed in the following embodiments and modifications. In the following description, the horizontal scanning periods in which the gate lines GL1 to GLm in the 1st to mth rows are selected are referred to as “first to m selection periods”, respectively.
　まず、第１選択期間になる（走査信号ＧＳ（１）がハイレベル電位になる）と、ゲートラインＧＬ１にゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、１行目の画素電位である１行１列目の画素電位Ｖｐ（１，１）および１行２列目の画素電位Ｖｐ（１，２）が書き込み電位Ｖｓｉｇになる。図４に示すように、この第１選択期間では各映像信号が正極性になっているので、１行目の画素電位は正極性になる。このように本実施形態では、ゲートラインの延伸する方向（以下「Ｘ方向」という）に隣接する画素形成部における画素電位が互いに同じ極性になる。その後、１行目のゲートラインＧＬ１が非選択状態になると、１行目のゲートラインＧＬ１にゲート端子が接続された薄膜トランジスタ５０はオフ状態になるので、１行目の画素電位は書き込み電位Ｖｓｉｇに保持される。この書き込み電位Ｖｓｉｇは走査期間Ｔ１の終了時点まで保持される。 First, in the first selection period (when the scanning signal GS (1) becomes a high level potential), the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on. The pixel capacitor Cp is charged by the video signal that is output. As a result, the pixel potential Vp (1,1) in the first row and the first column, which is the pixel potential in the first row, and the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig. As shown in FIG. 4, since each video signal has a positive polarity in the first selection period, the pixel potential in the first row has a positive polarity. As described above, in the present embodiment, the pixel potentials in the pixel forming portions adjacent to the extending direction of the gate line (hereinafter referred to as “X direction”) have the same polarity. After that, when the gate line GL1 in the first row becomes a non-selected state, the thin film transistor 50 whose gate terminal is connected to the gate line GL1 in the first row is turned off, so that the pixel potential in the first row becomes the write potential Vsig. Retained. This write potential Vsig is held until the end of the scanning period T1.
　次に、第２選択期間になると、ゲートラインＧＬ２にゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、２行目の画素電位である２行１列目の画素電位Ｖｐ（２，１）が書き込み電位Ｖｓｉｇになる。図４に示すように、この第２選択期間では各映像信号が負極性になっているので、２行目の画素電位は負極性になる。２行目のゲートラインＧＬ２が非選択状態になった後の画素電位については１行目に関するものと同様である。 Next, in the second selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (2, 1) in the second row and the first column, which is the pixel potential in the second row, becomes the write potential Vsig. As shown in FIG. 4, since each video signal has a negative polarity in the second selection period, the pixel potential in the second row has a negative polarity. The pixel potential after the second-row gate line GL2 is not selected is the same as that for the first row.
　以降、奇数行目および偶数行目に関して、それぞれ第１選択期間および第２選択期間と同様の動作が行われる。 Thereafter, operations similar to those in the first selection period and the second selection period are performed for the odd-numbered rows and the even-numbered rows, respectively.
　最後に、第ｍ選択期間になると、ゲートラインＧＬｍにゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、ｍ行目の画素電位であるｍ行１列目の画素電位Ｖｐ（ｍ，１）が書き込み電位Ｖｓｉｇになる。図４に示すように、この第ｍ選択期間では各映像信号が負極性になっているので、ｍ行目の画素電位は負極性になる。その後、ｍ行目のゲートラインＧＬｍが非選択状態になった後の画素電位については１行目に関するものと同様である。 Finally, in the m-th selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (m, 1) in the m-th row and the first column, which is the pixel potential in the m-th row, becomes the write potential Vsig. As shown in FIG. 4, since each video signal has a negative polarity in the m-th selection period, the pixel potential in the m-th row has a negative polarity. Thereafter, the pixel potential after the m-th gate line GLm is not selected is the same as that for the first row.
　このように本実施形態では、ソースラインの延伸する方向（以下「Ｙ方向」という）に隣接する画素形成部における画素電位が互いに異なる極性になる。 As described above, in this embodiment, pixel potentials in pixel forming portions adjacent to the extending direction of the source line (hereinafter referred to as “Y direction”) have different polarities.
　また、正極性の映像信号が書き込まれている画素電極Ｅｐとの間に補助容量Ｃｃｓを形成している奇数行目のＣＳライン、および負極性の映像信号が書き込まれている画素電極Ｅｐとの間に補助容量Ｃｃｓを形成している偶数行目のＣＳラインにそれぞれ与えられる第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂは、互いに電位が異なっている。 Also, the odd-numbered CS line forming the auxiliary capacitance Ccs between the pixel electrode Ep in which the positive video signal is written and the pixel electrode Ep in which the negative video signal is written. The first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
　＜１．３．２　休止期間での動作＞
　図４に示すように、休止期間Ｔ２が開始すると、第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂの電位が変化する。より詳細には、第１補助容量信号ＣＳａは直前の走査期間Ｔ１における低電位Ｖｌから高電位Ｖｈに変化し、第２補助容量信号ＣＳｂは直前の走査期間Ｔ１における高電位Ｖｈから低電位Ｖｌに変化する。このため、奇数行目のＣＳラインは低電位Ｖｌから高電位Ｖｈに、偶数行目のＣＳラインは高電位Ｖｈから低電位Ｖｌに互いに同じタイミングで変化する。なお、これらの第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂの電位は、後続のフレーム期間における走査期間Ｔ１の終了時点まで維持される。また、休止期間Ｔ２では上述のようにゲートラインＧＬ１～ＧＬｍはいずれも非選択状態になっており、また、各映像信号はＶｃｏｍ電位（これに限らず、他の固定電位でも良い）になっている。なお、この映像信号は、ゲートラインＧＬ１～ＧＬｍがいずれも非選択状態になっているので、画素電極に与えられない。 <1.3.2 Operation during idle periods>
As shown in FIG. 4, when the pause period T2 starts, the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change. More specifically, the first auxiliary capacitance signal CSa changes from the low potential Vl in the immediately preceding scanning period T1 to the high potential Vh, and the second auxiliary capacitance signal CSb changes from the high potential Vh in the immediately preceding scanning period T1 to the low potential Vl. Change. Therefore, the odd-numbered CS lines change from the low potential Vl to the high potential Vh, and the even-numbered CS lines change from the high potential Vh to the low potential Vl at the same timing. Note that the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb are maintained until the end of the scanning period T1 in the subsequent frame period. Further, as described above, all of the gate lines GL1 to GLm are in a non-selected state during the suspension period T2, and each video signal is at a Vcom potential (not limited to this, but may be another fixed potential). Yes. Note that this video signal is not applied to the pixel electrode because the gate lines GL1 to GLm are all in a non-selected state.
　各ＣＳラインの電位が変化することにより、当該ＣＳラインに補助容量Ｃｃｓを介して接続された画素電極の画素電位が変化することになる。ここでは、この画素電位の変化について１行１列目の画素電位Ｖｐ（１，１）に着目して説明し、他の画素電位については同様であるので説明を省略する。 When the potential of each CS line changes, the pixel potential of the pixel electrode connected to the CS line via the auxiliary capacitor Ccs changes. Here, the change in the pixel potential will be described by paying attention to the pixel potential Vp (1, 1) in the first row and the first column, and the other pixel potentials are the same, and the description thereof will be omitted.
　休止期間Ｔ２において第１補助容量信号ＣＳａ（１行目のＣＳラインＣＬ１）の電位が低電位Ｖｌから高電位Ｖｈに変化すると、１行１列目の画素電位Ｖｐ（１，１）に、第１補助容量信号ＣＳａの変化分に応じたバイアス電圧ΔＶｃｓが加わることになる。その結果、１行１列目の画素電位Ｖｐ（１，１）は下記の式（１）で示される（ただし、左辺は各画素電位Ｖｐとして示している）。
　Ｖｐ＝Ｖｓｉｇ＋ΔＶｃｓ
　　　＝Ｖｓｉｇ＋（Ｃｃｓ／（Ｃｌｃ＋Ｃｃｓ＋Ｃｐａ））
　　　　×（Ｖｈ－Ｖｌ）…（１）
ここで、Ｃｐａは画素内の寄生容量を表す。 When the potential of the first auxiliary capacitance signal CSa (CS line CL1 in the first row) changes from the low potential Vl to the high potential Vh in the pause period T2, the pixel potential Vp (1, 1) in the first row and first column is changed to the first potential. The bias voltage ΔVcs corresponding to the change in the one auxiliary capacitance signal CSa is applied. As a result, the pixel potential Vp (1, 1) in the first row and the first column is expressed by the following formula (1) (however, the left side is shown as each pixel potential Vp).
Vp = Vsig + ΔVcs
= Vsig + (Ccs / (Clc + Ccs + Cpa))
× (Vh−Vl) (1)
Here, Cpa represents a parasitic capacitance in the pixel.
　このように、１行１列目の画素電位Ｖｐ（１，１）は、映像信号の振幅に相当する書き込み電位Ｖｓｉｇよりも（Ｃｃｓ／（Ｃｌｃ＋Ｃｃｓ＋Ｃｐａ））×（Ｖｈ－Ｖｌ）だけ大きくなる。このようにして、ソースラインに与えるべき映像信号の振幅を小さくしつつ、液晶層に大きな電圧を印加することができる。これにより、低消費電力化を図ることができる。この１行１列目の画素電位Ｖｐ（１，１）は、本フレーム期間の後続のフレーム期間の走査期間Ｔ１において薄膜トランジスタ５０が再度オン状態になるまで保持される。なお、この後続のフレーム期間では、１行１列目の画素電位Ｖｐ（１，１）が逆極性になるので、上記式（１）における（Ｖｈ－Ｖｌ）が（Ｖｌ－Ｖｈ）となる。また、本フレーム期間における偶数行目の画素電位についても、１行１列目の画素電位Ｖｐ（１，１）の逆極性になるので、上記式（１）における（Ｖｈ－Ｖｌ）が（Ｖｌ－Ｖｈ）となる。 Thus, the pixel potential Vp (1, 1) in the first row and the first column is larger than the write potential Vsig corresponding to the amplitude of the video signal by (Ccs / (Clc + Ccs + Cpa)) × (Vh−Vl). In this manner, a large voltage can be applied to the liquid crystal layer while reducing the amplitude of the video signal to be applied to the source line. Thereby, low power consumption can be achieved. The pixel potential Vp (1, 1) in the first row and first column is held until the thin film transistor 50 is turned on again in the scanning period T1 of the frame period subsequent to the present frame period. In this subsequent frame period, the pixel potential Vp (1, 1) in the first row and the first column has a reverse polarity, so (Vh−Vl) in the above equation (1) becomes (Vl−Vh). In addition, since the pixel potential in the even-numbered row in this frame period also has the opposite polarity to the pixel potential Vp (1, 1) in the first row and the first column, (Vh−Vl) in the above equation (1) is (Vl). −Vh).
　本実施形態では、走査期間Ｔ１において映像信号が書き込まれるタイミングが１～ｍ行目で互いに異なる一方で、休止期間Ｔ２において補助容量信号が１～ｍ行目で同時に変化する。このため、１～ｍ行目で１フレーム分の実効電圧に齟齬が生じ得る。このような齟齬は、図４に示すように、休止期間Ｔ２において画素電位Ｖｐにバイアス電圧ΔＶｃｓが加わってから、直後の走査期間Ｔ１において映像信号の書き込みが行われるまでの期間が、各行で異なるために生じる。ここで、「１フレーム分の実効電圧」とは、任意のフレーム期間における走査期間Ｔ１での映像信号の書き込み時点（以下単に「書き込み時点」という）から当該フレーム期間の後続のフレーム期間における走査期間Ｔ１での書き込み時点までの期間（以下「１フレーム保持期間」という）に画素容量Ｃｐに印加される実効電圧をいう。例えば、１行１列目の画素形成部Ｐ（１，１）の画素容量Ｃｐに印加される電圧は、図４に示す画素電位Ｖｐ（１，１）とＶｃｏｍ電位との差に相当する。このような１フレーム分の実効電圧の齟齬は特に、休止期間Ｔ２において画素電位Ｖｐにバイアス電圧ΔＶｃｓが加わってから、直後の走査期間Ｔ１において映像信号の書き込みが行われるまでの期間の差が大きい１行目とｍ行目との間で大きくなる。 In this embodiment, the timing at which the video signal is written in the scanning period T1 is different in the 1st to mth rows, while the auxiliary capacitance signal is simultaneously changed in the 1st to mth rows in the rest period T2. For this reason, wrinkles may occur in the effective voltage for one frame in the first to mth rows. As shown in FIG. 4, each row has a different period from when the bias voltage ΔVcs is added to the pixel potential Vp in the pause period T2 until the video signal is written in the immediately following scanning period T1. Because of. Here, “effective voltage for one frame” refers to a scanning period in a frame period subsequent to a video signal writing point (hereinafter simply referred to as “writing point”) in a scanning period T1 in an arbitrary frame period. The effective voltage applied to the pixel capacitor Cp in the period up to the writing time at T1 (hereinafter referred to as “one frame holding period”). For example, the voltage applied to the pixel capacitor Cp of the pixel formation portion P (1,1) in the first row and first column corresponds to the difference between the pixel potential Vp (1,1) and the Vcom potential shown in FIG. Such a difference in effective voltage for one frame is particularly large in a difference in period from when the bias voltage ΔVcs is added to the pixel potential Vp in the pause period T2 to when the video signal is written in the immediately following scanning period T1. It becomes large between the 1st line and the m-th line.
　しかし、本実施形態では、上述のように休止期間Ｔ２（９９１．７ｍｓｅｃ）が走査期間Ｔ１（８．３ｍｓｅｃ）よりも長く設けられている。このように休止期間Ｔ２が走査期間Ｔ１よりも十分に長くなることにより、１フレーム保持期間に対する、走査期間Ｔ１において映像信号が書き込まれるタイミングの１～ｍ行目での差の影響が小さくなる。このため、１～ｍ行目での１フレーム分の実効電圧の齟齬が低減される。 However, in this embodiment, as described above, the pause period T2 (991.7 msec) is set longer than the scanning period T1 (8.3 msec). As described above, since the pause period T2 is sufficiently longer than the scanning period T1, the influence of the difference in the 1st to mth rows of the timing at which the video signal is written in the scanning period T1 with respect to the one frame holding period is reduced. Therefore, the effective voltage drop for one frame in the 1st to mth rows is reduced.
　＜１．４　画素レイアウト＞
　次に、本実施形態における画素レイアウトの第１の実現例および第２の実現例について説明する。 <1.4 Pixel layout>
Next, a first implementation example and a second implementation example of the pixel layout in the present embodiment will be described.
　＜１．４．１　第１の実現例＞
　図５は、本実施形態における画素レイアウトの第１の実現例を示す平面図である。図６は、図５におけるＡ－Ａ’線断面図である。なお、図５、図６、および以降の画素レイアウトに関する図では画素形成部Ｐ（ｉ，ｊ）に相当する部分を中心に示している。また、ソースライン、ゲートライン、およびＣＳライン（ただし、透明電極として形成されたＣＳラインを除く）部分についてはハッチングを施しているが、透明電極部分についてはハッチングを省略している。さらに、絶縁基板等の図示は省略している。 <1.4.1 First Implementation Example>
FIG. 5 is a plan view showing a first implementation example of the pixel layout in the present embodiment. 6 is a cross-sectional view taken along line AA ′ in FIG. 5 and 6 and the subsequent drawings relating to the pixel layout, the portion corresponding to the pixel formation portion P (i, j) is mainly shown. In addition, the source line, the gate line, and the CS line (except for the CS line formed as a transparent electrode) are hatched, but the transparent electrode is not hatched. Furthermore, illustration of an insulating substrate etc. is omitted.
　図５に示すように、本実現例では、ソースラインとゲートラインとが互いに交差するように設けられ、当該ゲートラインに沿ってＣＳラインが設けられている。薄膜トランジスタ５０は、ソースラインに接続され（より詳細にはこのソースラインの一部をソース電極とし）、ゲートラインに接続され（より詳細にはこのゲートラインの一部をゲート電極とし）、ドレイン電極Ｅｄに接続されている。ドレイン電極Ｅｄと画素電極ＥｐとはコンタクトホールＣＨを介して互いに接続されている。 As shown in FIG. 5, in this implementation example, the source line and the gate line are provided so as to cross each other, and the CS line is provided along the gate line. The thin film transistor 50 is connected to a source line (more specifically, a part of the source line is a source electrode), is connected to a gate line (more specifically, a part of the gate line is a gate electrode), and is connected to a drain electrode. Connected to Ed. The drain electrode Ed and the pixel electrode Ep are connected to each other through a contact hole CH.
　ソースラインおよびゲートラインは例えばＡｌ膜とＴｉ膜との積層膜等により形成される。また、本実施形態ではＣＳラインもＡｌ膜とＴｉ膜との積層膜等により形成される。 The source line and the gate line are formed by a laminated film of an Al film and a Ti film, for example. In the present embodiment, the CS line is also formed by a laminated film of an Al film and a Ti film.
　図６に示すように、ＣＳライン（およびゲートライン）上には第１絶縁層５１が形成されている。この第１絶縁層５１は例えばＳｉＮx等からなる。この第１絶縁層５１上にはソースラインおよびドレイン電極Ｅｄが形成されている。第１絶縁層５１により、ＣＳラインとドレイン電極Ｅｄ（すなわち画素電極Ｅｐ）との間で補助容量Ｃｃｓが形成されている。また、これらのソースラインおよびドレイン電極Ｅｄ上には第２絶縁層５２が形成されている。この第２絶縁層５２は例えばＳｉＮx等からなる。この第２絶縁層５２には、ドレイン電極Ｅｄと画素電極Ｅｐとを互いに接続するための上述のコンタクトホールＣＨが形成されている。このコンタクトホールＣＨが形成された第２絶縁層５２上には、当該コンタクトホールＣＨを覆うように画素電極Ｅｐが形成されている。このため、ドレイン電極Ｅｄと画素電極Ｅｐとが互いに接続される。画素電極ＥｐはＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ：酸化インジウムスズ）等からなる透明電極である。この画素電極Ｅｐと、これに対向する、ＩＴＯ等からなる透明電極である共通電極Ｅｃとの間には液晶が充填されることにより液晶層６０が形成されている。この液晶層６０により、画素電極Ｅｐと共通電極Ｅｃとの間で液晶容量Ｃｌｃ（図示しない）が形成されている。 As shown in FIG. 6, a first insulating layer 51 is formed on the CS line (and the gate line). The first insulating layer 51 is made of, for example, SiN x . A source line and drain electrode Ed are formed on the first insulating layer 51. The first insulating layer 51 forms an auxiliary capacitor Ccs between the CS line and the drain electrode Ed (that is, the pixel electrode Ep). A second insulating layer 52 is formed on the source line and drain electrode Ed. The second insulating layer 52 is made of, for example, SiN x . In the second insulating layer 52, the contact hole CH described above for connecting the drain electrode Ed and the pixel electrode Ep to each other is formed. On the second insulating layer 52 in which the contact hole CH is formed, the pixel electrode Ep is formed so as to cover the contact hole CH. For this reason, the drain electrode Ed and the pixel electrode Ep are connected to each other. The pixel electrode Ep is a transparent electrode made of ITO (Indium Tin Oxide) or the like. A liquid crystal layer 60 is formed by filling liquid crystal between the pixel electrode Ep and the common electrode Ec which is a transparent electrode made of ITO or the like facing the pixel electrode Ep. The liquid crystal layer 60 forms a liquid crystal capacitance Clc (not shown) between the pixel electrode Ep and the common electrode Ec.
　本実現例では、ＣＳラインがゲートラインと同じ材料からなるので、これらを同じ工程で形成することができる。 In this example, since the CS line is made of the same material as the gate line, these can be formed in the same process.
　＜１．４．２　第２の実現例＞
　図７は、本実施形態における画素レイアウトの第２の実現例を示す平面図である。図８は、図７におけるＢ－Ｂ’線断面図である。なお、上記第１の実現例と共通する部分については説明を省略する。本実現例では、上記第１の実現例と異なり、ＣＳラインがＩＴＯ等からなる透明電極として形成されている。本実現例におけるＣＳラインは、Ｘ方向に隣接する画素形成部にわたって連続に形成されている。本実現例では、ドレイン電極Ｅｄは画素電極ＥｐにのみコンタクトホールＣＨを介して接続され、ＣＳラインには接続されていない。なお、図８ではＣＳラインが薄膜トランジスタ５０を覆わない構成となっているが、本発明はこれに限定されるものではない。 <1.4.2 Second Implementation Example>
FIG. 7 is a plan view showing a second implementation example of the pixel layout in the present embodiment. 8 is a cross-sectional view taken along the line BB ′ in FIG. Note that description of portions common to the first implementation example is omitted. In this implementation example, unlike the first implementation example, the CS line is formed as a transparent electrode made of ITO or the like. The CS line in this implementation example is continuously formed across pixel forming portions adjacent in the X direction. In this implementation example, the drain electrode Ed is connected only to the pixel electrode Ep via the contact hole CH, and is not connected to the CS line. In FIG. 8, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
　図８に示すように、ソースライン上には第１絶縁層５１が形成されている。この第１絶縁層５１上にはＩＴＯ等からなる透明電極であるＣＳラインが形成されている。このＣＳライン上には第２絶縁層５２が形成されている。この第２絶縁層５２上には画素電極Ｅｐが形成されている。この第２絶縁層５２により、ＣＳラインと画素電極Ｅｐとの間で補助容量Ｃｃｓが形成されている。 As shown in FIG. 8, a first insulating layer 51 is formed on the source line. A CS line, which is a transparent electrode made of ITO or the like, is formed on the first insulating layer 51. A second insulating layer 52 is formed on the CS line. A pixel electrode Ep is formed on the second insulating layer 52. The second insulating layer 52 forms an auxiliary capacitor Ccs between the CS line and the pixel electrode Ep.
　本実現例では、ＣＳラインが透明電極として形成されているので、開口率を低下させることなくＣＳラインを形成することができる。 In this realization example, since the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
　＜１．５　酸化物半導体を半導体層に用いた例＞
　従来から、アモルファスシリコン（ａ－Ｓｉ）を半導体層に用いた薄膜トランジスタ（以下「ａ－ＳｉＴＦＴ」という）が液晶表示装置の各画素形成部内の薄膜トランジスタとして用いられていた。しかし、本実施形態における各画素形成部内の薄膜トランジスタ５０の半導体層には酸化物半導体が用いられる。なお、酸化物半導体としては、典型的には、インジウム、ガリウム、亜鉛、および酸素を主成分とする酸化物半導体であるＩｎＧａＺｎＯx（以下、「ＩＧＺＯ」という）が用いられるが本発明はこれに限定されるものではない。例えば、インジウム、ガリウム、亜鉛、銅、珪素、錫、アルミニウム、カルシウム、ゲルマニウム、および鉛のうち少なくとも１つを含む酸化物半導体であれば良い。 <1.5 Example of using oxide semiconductor for semiconductor layer>
Conventionally, a thin film transistor (hereinafter referred to as “a-Si TFT”) using amorphous silicon (a-Si) as a semiconductor layer has been used as a thin film transistor in each pixel formation portion of a liquid crystal display device. However, an oxide semiconductor is used for the semiconductor layer of the thin film transistor 50 in each pixel formation portion in this embodiment. Note that as the oxide semiconductor, typically, InGaZnO x (hereinafter referred to as “IGZO”), which is an oxide semiconductor mainly containing indium, gallium, zinc, and oxygen, is used. It is not limited. For example, any oxide semiconductor containing at least one of indium, gallium, zinc, copper, silicon, tin, aluminum, calcium, germanium, and lead may be used.
　図９は、ａ－ＳｉＴＦＴおよびＩＧＺＯを半導体層に用いたＴＦＴ（以下「ＩＧＺＯＴＦＴ」という）のドレイン電流－ゲート電圧特性を示す図である。図９において、横軸はゲート電圧Ｖｇを表し、縦軸はドレイン電流Ｉｄｓを表している。図９に示すように、ＩＧＺＯＴＦＴのリーク電流はａ－ＳｉＴＦＴのリーク電流の１／１０００以下であると共に、ＩＧＺＯＴＦＴのオン電流はａ－ＳｉＴＦＴのオン電流の約２０倍である。 FIG. 9 is a diagram showing drain current-gate voltage characteristics of a TFT using a-Si TFT and IGZO as a semiconductor layer (hereinafter referred to as “IGZOTFT”). In FIG. 9, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Ids. As shown in FIG. 9, the leakage current of the IGZOTFT is 1/1000 or less of the leakage current of the a-Si TFT, and the on-current of the IGZOTFT is about 20 times the on-current of the a-Si TFT.
　ＩＧＺＯＴＦＴは上述のようにオフリーク電流が小さいので、ＩＧＺＯＴＦＴを本実施形態における薄膜トランジスタ５０として用いた場合、ａ－ＳｉＴＦＴをこの薄膜トランジスタ５０として用いた場合よりも、画素電位を長時間保持することができる。このため、ＩＧＺＯＴＦＴを本実施形態における薄膜トランジスタ５０として用いた場合には、休止期間Ｔ２を十分に設けることができる。 Since the IGZOTFT has a small off-leakage current as described above, when the IGZOTFT is used as the thin film transistor 50 in this embodiment, the pixel potential can be maintained for a longer time than when the a-Si TFT is used as the thin film transistor 50. For this reason, when the IGZOTFT is used as the thin film transistor 50 in the present embodiment, the idle period T2 can be sufficiently provided.
　また、ＩＧＺＯＴＦＴは上述のようにオン電流が大きいので、ＩＧＺＯＴＦＴを本実施形態における薄膜トランジスタ５０として用いた場合、ａ－ＳｉＴＦＴをこの薄膜トランジスタ５０として用いた場合よりも、画素形成部への映像信号の書き込みを高速化できる。すなわち、走査期間Ｔ１を短くすることができる。 Further, since the IGZOTFT has a large on-state current as described above, when the IGZOTFT is used as the thin film transistor 50 in this embodiment, the video signal is written to the pixel formation portion more than when the a-Si TFT is used as the thin film transistor 50. Can be speeded up. That is, the scanning period T1 can be shortened.
　＜１．６　効果＞
　本実施形態によれば、走査期間Ｔ１の後に休止期間Ｔ２を設けたいわゆる低周波リフレッシュ駆動が行われる液晶表示装置において、ＣＳ駆動が行われる。本実施形態では、ＣＳ駆動を採用した従来の液晶表示装置と異なりＣＳラインを駆動するためのＣＳドライバが表示部５００（パネル）の額縁部に設けられておらず、奇数行目および偶数行目のＣＳラインにそれぞれ与える第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂの電位を休止期間Ｔ２において一括で変化させる補助容量信号生成回路２０１が表示制御回路２００内に設けられている。この補助容量信号生成回路２０１は、従来のＣＳドライバのようには各ＣＳラインの電位を順次変化させずに、各ＣＳラインの電位を一括で変化させるので、当該従来のＣＳドライバよりも回路規模が小さい。このため、額縁面積を縮小しつつ消費電力を低減することができる。また、低周波リフレッシュ駆動が行われるので、さらなる低消費電力化を図ることができる。さらに、全ＣＳライン（補助容量信号）の電位が同時に変化するので、ゲートラインの走査順が昇順（ＧＬ１→ＧＬ２→…→ＧＬｍの順）であるか降順（ＧＬｍ→…→ＧＬ２→ＧＬ１の順）であるかに関わらずＣＳ駆動を行うことができる。 <1.6 Effect>
According to the present embodiment, CS driving is performed in a liquid crystal display device that performs so-called low-frequency refresh driving in which a pause period T2 is provided after the scanning period T1. In the present embodiment, unlike a conventional liquid crystal display device that employs CS driving, a CS driver for driving a CS line is not provided in the frame portion of the display unit 500 (panel). The display control circuit 200 is provided with an auxiliary capacitance signal generation circuit 201 that collectively changes the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the respective CS lines in the idle period T2. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved. Further, since the potentials of all the CS lines (auxiliary capacitance signals) change simultaneously, the scanning order of the gate lines is ascending (GL1 → GL2 → ... → GLm) or descending (GLm → ... → GL2 → GL1). ) CS driving can be performed regardless of whether or not.
　また、本実施形態によれば、休止期間Ｔ２が走査期間Ｔ１よりも長く設けられているので、さらなる消費電力化を図ることができる。また、この休止期間Ｔ２が十分に設けられることにより、１フレーム保持期間に対する、走査期間Ｔ１において映像信号が書き込まれるタイミングの１～ｍ行目での差の影響が小さくなる。このため、１～ｍ行目での１フレーム分の実効電圧の齟齬が十分に低減される。 Further, according to the present embodiment, since the pause period T2 is provided longer than the scanning period T1, further power consumption can be achieved. In addition, since the pause period T2 is sufficiently provided, the influence of the difference in the 1st to mth rows of the timing at which the video signal is written in the scanning period T1 with respect to the 1 frame holding period is reduced. Therefore, the effective voltage drop for one frame in the 1st to m-th rows is sufficiently reduced.
　また、本実施形態によれば、ＣＳラインＣＬ１～ＣＬｍがゲートラインＧＬ１～ＧＬｍにそれぞれ沿って設けられ、互いに電位の異なる第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂがそれぞれ奇数行目および偶数行目のＣＳラインに与えられる。そして、走査期間Ｔ１において各映像信号の極性が１水平走査期間毎に反転すると共に、第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂが休止期間Ｔ２において電位が同時に変化する。このため、ＣＳ駆動を行いつつ、所定本数（本実施形態では１本）のゲートライン毎に、かつ、１フレーム期間毎に映像信号の極性を反転させるライン反転駆動（「ゲートライン反転駆動」ともいう）を行うことができる。 Further, according to the present embodiment, the CS lines CL1 to CLm are provided along the gate lines GL1 to GLm, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered rows and It is given to the CS line of the even row. In the scanning period T1, the polarity of each video signal is inverted every horizontal scanning period, and the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2. For this reason, while performing CS driving, line inversion driving (“gate line inversion driving”) that inverts the polarity of the video signal every predetermined number of gate lines (in this embodiment, one) and every frame period. Say).
　また、ＣＳラインをゲートラインと同じ材料で形成した場合には、ＣＳラインをゲートラインと同じ工程で形成することができるのでコストを低減することができる。 Also, when the CS line is formed of the same material as the gate line, the cost can be reduced because the CS line can be formed in the same process as the gate line.
　また、ＣＳラインを透明電極として形成した場合には、ＣＳラインを形成することによる開口率の低下を抑制することができる。 Moreover, when the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
　また、各画素形成部内の薄膜トランジスタ５０にＩＧＺＯＴＦＴを用いた場合には、画素電位を長時間保持できるので、休止期間Ｔ２を十分に長くできる。また、画素形成部への映像信号の書き込みを高速化できるので、走査期間Ｔ１を十分に短くできる。この場合、低周波リフレッシュ駆動を行いつつ、フレーム周波数（１フレーム期間における駆動周波数）の低下を抑制することができる。 Further, when an IGZOTFT is used for the thin film transistor 50 in each pixel formation portion, the pixel potential can be held for a long time, so that the pause period T2 can be made sufficiently long. In addition, since the writing of the video signal to the pixel formation portion can be speeded up, the scanning period T1 can be sufficiently shortened. In this case, it is possible to suppress a decrease in the frame frequency (drive frequency in one frame period) while performing the low frequency refresh drive.
　＜２．第２の実施形態＞
　＜２．１　表示部の構成＞
　図１０は、本発明の第２の実施形態における表示部５００の構成を示す回路図である。なお、本実施形態は、表示部５００の構成、液晶表示装置の動作、および画素レイアウトの実現例以外については上記第１の実施形態と同様であるので、当該同様の部分についての説明を省略する。図１０に示すように、本実施形態では上記第１の実施形態と異なり、ＣＳラインの本数がｎ本になっている。ｎ本のＣＳラインＣＬ１～ＣＬｎはソースラインＳＬ１～ＳＬｎにそれぞれ沿って配置されている。各画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタのソース端子が接続されたソースラインに沿って配置されたＣＳラインと、当該画素形成部における画素電極Ｅｐとの間に形成されている。 <2. Second Embodiment>
<2.1 Display configuration>
FIG. 10 is a circuit diagram showing a configuration of the display unit 500 according to the second embodiment of the present invention. Note that this embodiment is the same as the first embodiment except for the configuration of the display unit 500, the operation of the liquid crystal display device, and an implementation example of the pixel layout, and thus description of the same parts is omitted. . As shown in FIG. 10, in this embodiment, unlike the first embodiment, the number of CS lines is n. The n CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively. The auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Yes.
　ゲートドライバ４００が配置されている側から数えて奇数列目（以下単に「奇数列目」という）のＣＳラインＣＬ１、ＣＬ３、…ＣＬｎ－１には第１補助容量信号ＣＳａが与えられる。ゲートドライバ４００が配置されている側から数えて偶数列目（以下単に「偶数列目」という）のＣＳラインＣＬ２、ＣＬ４、…ＣＬｎには第２補助容量信号ＣＳｂが与えられる。 The first auxiliary capacitance signal CSa is applied to the CS lines CL1, CL3,..., CLn−1 of the odd-numbered columns (hereinafter simply referred to as “odd-numbered columns”) counted from the side where the gate driver 400 is disposed. The second auxiliary capacitance signal CSb is applied to the CS lines CL2, CL4,... CLn of even-numbered columns (hereinafter simply referred to as “even-numbered columns”) counted from the side where the gate driver 400 is disposed.
　＜２．２　液晶表示装置の動作＞
　図１１は、本実施形態に係る液晶表示装置の動作を説明するための信号波形図である。なお、この液晶表示装置の動作のうち、上記第１の実施形態におけるものと同様の部分については適宜説明を省略する。 <2.2 Operation of liquid crystal display device>
FIG. 11 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment. Of the operation of the liquid crystal display device, the description of the same parts as those in the first embodiment will be omitted as appropriate.
　＜２．２．１　走査期間での動作＞
　図１１に示すように、走査期間Ｔ１における第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂはそれぞれ、互いに異なる電位である低電位Ｖｌおよび高電位Ｖｈになっている。すなわち、奇数列目のＣＳラインは低電位Ｖｌに、偶数列目のＣＳラインは高電位Ｖｈになっている。本実施形態では上記第１の実施形態と異なり、奇数列目および偶数列目のソースラインに与えられる映像信号はそれぞれ、走査期間Ｔ１において正極性および負極性（後続のフレーム期間における走査期間Ｔ１では負極性および正極性）になっている。以下では、ｊ列目のソースラインに与えられる映像信号のことを「ｊ列目の映像信号」という（ｊ＝１～ｎ）。 <2.2.1 Operation during scanning period>
As shown in FIG. 11, the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other, respectively. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh. In the present embodiment, unlike the first embodiment, the video signals applied to the odd-numbered and even-numbered source lines are positive and negative in the scanning period T1 (in the scanning period T1 in the subsequent frame period), respectively. Negative polarity and positive polarity). Hereinafter, the video signal applied to the source line of the jth column is referred to as “jth column video signal” (j = 1 to n).
　まず、第１選択期間になると、ゲートラインＧＬ１にゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、１行目の画素電位である１行１列目の画素電位Ｖｐ（１，１）および１行２列目の画素電位Ｖｐ（１，２）が書き込み電位Ｖｓｉｇになる。図１１に示すように、奇数列目および偶数列目の映像信号がそれぞれ正極性および負極性になっているので、１行目における奇数列目および偶数列目の画素電位はそれぞれ正極性および負極性になる。このように本実施形態では、Ｘ方向に隣接する画素形成部における画素電位が互いに異なる極性になる。 First, in the first selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (1,1) in the first row and the first column, which is the pixel potential in the first row, and the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig. As shown in FIG. 11, since the odd-numbered and even-numbered video signals are positive and negative, respectively, the pixel potentials of the odd-numbered and even-numbered columns in the first row are positive and negative, respectively. Become sex. As described above, in the present embodiment, the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities.
　次に、第２選択期間になると、当該ゲートラインＧＬ２にゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、２行目の画素電位である２行１列目の画素電位Ｖｐ（２，１）が書き込み電位Ｖｓｉｇになる。図１１に示すように、奇数列目および偶数列目の映像信号がそれぞれ正極性および負極性になっているので、１行目と同様に、２行目における奇数列目および偶数列目の画素電位のそれぞれ正極性および負極性になる。 Next, in the second selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (2, 1) in the second row and the first column, which is the pixel potential in the second row, becomes the write potential Vsig. As shown in FIG. 11, since the odd-numbered and even-numbered video signals are positive and negative, respectively, the odd-numbered and even-numbered pixels in the second row are the same as in the first row. The potential becomes positive and negative, respectively.
　以降、奇数行目および偶数行目に関して、それぞれ第１選択期間および第２選択期間と同様の動作が行われる。 Thereafter, operations similar to those in the first selection period and the second selection period are performed for the odd-numbered rows and the even-numbered rows, respectively.
　最後に、第ｍ選択期間になると、当該ゲートラインＧＬｍにゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、ｍ行目の画素電位であるｍ行１列目の画素電位Ｖｐ（ｍ，１）が書き込み電位Ｖｓｉｇになる。図１１に示すように、奇数列目および偶数列目の映像信号がそれぞれ正極性および負極性になっているので、１行目と同様に、ｍ行目における奇数列目および偶数列目の画素電位のそれぞれ正極性および負極性になる。 Finally, in the m-th selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (m, 1) in the m-th row and the first column, which is the pixel potential in the m-th row, becomes the write potential Vsig. As shown in FIG. 11, since the odd-numbered and even-numbered video signals are positive and negative, respectively, the odd-numbered and even-numbered pixels in the m-th row are the same as the first row. The potential becomes positive and negative, respectively.
　このように本実施形態では、Ｙ方向に隣接する画素形成部における画素電位が互いに同じ極性になる。 Thus, in the present embodiment, the pixel potentials in the pixel forming portions adjacent in the Y direction have the same polarity.
　また、正極性の映像信号が書き込まれている画素電極Ｅｐとの間に補助容量Ｃｃｓを形成している奇数列目のＣＳライン、および負極性の映像信号が書き込まれている画素電極Ｅｐとの間に補助容量Ｃｃｓを形成している偶数列目のＣＳラインにそれぞれ与えられる第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂは、互いに電位が異なっている。 In addition, the odd-numbered CS line forming the auxiliary capacitance Ccs between the pixel electrode Ep to which the positive video signal is written and the pixel electrode Ep to which the negative video signal is written. The first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
　＜２．２．２　休止期間での動作＞
　休止期間Ｔ２が開始すると、第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂは第１の実施形態と同様の変化をする。このため、奇数列目のＣＳラインは低電位Ｖｌから高電位Ｖｈに、偶数列目のＣＳラインは高電位Ｖｈから低電位Ｖｌに互いに同じタイミングで変化する。なお、この休止期間Ｔ２での基本的な動作は上記第１の実施形態と同様であるので、その説明を省略する。 <2.2.2 Operation during idle period>
When the suspension period T2 starts, the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change in the same manner as in the first embodiment. Thus, the odd-numbered CS lines change from the low potential Vl to the high potential Vh, and the even-numbered CS lines change from the high potential Vh to the low potential Vl at the same timing. Note that the basic operation in the suspension period T2 is the same as that in the first embodiment, and a description thereof will be omitted.
　＜２．３　画素レイアウト＞
　次に、本実施形態における画素レイアウトの第１の実現例および第２の実現例について説明する。 <2.3 Pixel layout>
Next, a first implementation example and a second implementation example of the pixel layout in the present embodiment will be described.
　＜２．３．１　第１の実現例＞
　図１２は、本実施形態における画素レイアウトの第１の実現例を示す平面図である。図１３は、図１２におけるＣ－Ｃ’線断面図である。なお、上記第１の実施形態における各実現例と同様の部分については適宜説明を省略する。 <2.3.1 First Implementation Example>
FIG. 12 is a plan view showing a first implementation example of the pixel layout in the present embodiment. 13 is a cross-sectional view taken along the line CC ′ in FIG. Note that description of parts similar to those of the implementation examples in the first embodiment is omitted as appropriate.
　図１２に示すように、本実現例では、ソースラインとゲートラインとが互いに交差するように設けられ、当該ソースラインに沿ってＣＳラインが設けられている。本実現例におけるＣＳラインは、詳細には、ソースラインに沿ったＣＳバスラインＢｃｓと、ゲートラインに沿い、かつ、隣接するソースライン間の距離よりもＸ方向の幅が小さい狭義のＣＳラインＥｃｓ（以下単に「ＣＳラインＥｃｓ」という）とからなっている。本実現例における各構成要素の材料は上記第１の実施形態の第１の実現例におけるものと同様である。なお、ＣＳバスラインＢｃｓおよびＣＳラインＥｃｓは互いに同じ材料（例えばＡｌ膜とＴｉ膜との積層膜等）により形成される。 As shown in FIG. 12, in this implementation example, the source line and the gate line are provided so as to cross each other, and the CS line is provided along the source line. Specifically, the CS line in this implementation example is a CS bus line Bcs along the source line and a narrow CS line Ecs along the gate line and having a width in the X direction smaller than the distance between adjacent source lines. (Hereinafter simply referred to as “CS line Ecs”). The material of each component in this implementation example is the same as that in the first implementation example of the first embodiment. Note that the CS bus line Bcs and the CS line Ecs are formed of the same material (for example, a laminated film of an Al film and a Ti film).
　図１３に示すように、ＣＳラインＥｃｓ（およびゲートライン）上には第１絶縁層５１が形成されている。この第１絶縁層５１には、ＣＳラインＥｃｓとＣＳバスラインＢｃｓとを互いに接続するための第１コンタクトホールＣＨａが形成されている。第１絶縁層５１上にはソースライン、ドレイン電極Ｅｄ、およびＣＳバスラインＢｃｓが形成されている。なお、ＣＳバスラインＢｃｓは第１コンタクトホールＣＨａを覆うように形成されている。このため、ＣＳライン電極ＥｃｓとＣＳバスラインＢｃｓとが互いに接続される。また、第１絶縁層５１により、ＣＳラインＥｃｓとドレイン電極Ｅｄ（すなわち画素電極Ｅｐ）との間で補助容量Ｃｃｓが形成されている。ソースライン、ドレイン電極Ｅｄ、およびＣＳバスラインＢｃｓ上には第２絶縁層５２が形成されている。この第２絶縁層５２には、ドレイン電極Ｅｄと画素電極Ｅｐとを互いに接続するための上述のコンタクトホールＣＨが形成されている。このコンタクトホールＣＨが形成された第２絶縁層５２上には、当該コンタクトホールＣＨを覆うように画素電極Ｅｐが形成されている。このため、ドレイン電極Ｅｄと画素電極Ｅｐとが互いに接続される。 As shown in FIG. 13, a first insulating layer 51 is formed on the CS line Ecs (and the gate line). In the first insulating layer 51, a first contact hole CHa for connecting the CS line Ecs and the CS bus line Bcs to each other is formed. On the first insulating layer 51, a source line, a drain electrode Ed, and a CS bus line Bcs are formed. The CS bus line Bcs is formed so as to cover the first contact hole CHa. For this reason, the CS line electrode Ecs and the CS bus line Bcs are connected to each other. Further, the first insulating layer 51 forms an auxiliary capacitor Ccs between the CS line Ecs and the drain electrode Ed (that is, the pixel electrode Ep). A second insulating layer 52 is formed on the source line, the drain electrode Ed, and the CS bus line Bcs. In the second insulating layer 52, the contact hole CH described above for connecting the drain electrode Ed and the pixel electrode Ep to each other is formed. On the second insulating layer 52 in which the contact hole CH is formed, the pixel electrode Ep is formed so as to cover the contact hole CH. For this reason, the drain electrode Ed and the pixel electrode Ep are connected to each other.
　本実現例では、ＣＳラインＥｃｓがゲートラインと同じ材料からなるので、これらを同じ工程で形成することができる。また、ＣＳバスラインＢｃｓがソースラインおよびドレイン電極Ｅｄと同じ材料からなるので、これらを同じ工程で形成することができる。 In this example, since the CS line Ecs is made of the same material as the gate line, they can be formed in the same process. Further, since the CS bus line Bcs is made of the same material as the source line and the drain electrode Ed, they can be formed in the same process.
　＜２．３．２　第２の実現例＞
　図１４は、本実施形態における画素レイアウトの第２の実現例を示す平面図である。図１５は、図１４におけるＤ－Ｄ’線断面図である。なお、上記第１の実現例と共通する部分については説明を省略する。また、図１５（層構造）については上記第１の実施形態における第２の実現例と同様であるのでその説明を省略する。本実現例では、上記第１の実現例と異なり、ＣＳラインがＩＴＯ等からなる透明電極として形成されている。本実現例におけるＣＳラインは、Ｙ方向に隣接する画素形成部にわたって連続に形成されている。なお、図１４ではＣＳラインが薄膜トランジスタ５０を覆わない構成となっているが、本発明はこれに限定されるものではない。 <2.3.2 Second Implementation Example>
FIG. 14 is a plan view showing a second implementation example of the pixel layout in the present embodiment. 15 is a cross-sectional view taken along the line DD ′ in FIG. Note that description of portions common to the first implementation example is omitted. Further, FIG. 15 (layer structure) is the same as that of the second example of realization in the first embodiment, and the description thereof is omitted. In this implementation example, unlike the first implementation example, the CS line is formed as a transparent electrode made of ITO or the like. The CS line in this implementation example is continuously formed across pixel forming portions adjacent in the Y direction. In FIG. 14, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
　本実現例では、ＣＳラインが透明電極として形成されているので、開口率を低下させることなくＣＳラインを形成することができる。 In this realization example, since the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
　＜２．４　効果＞
　本実施形態によれば、上記第１の実施形態と同様に、奇数列目および偶数列目のＣＳラインにそれぞれ与える第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂの電位を休止期間Ｔ２において一括で変化させる補助容量信号生成回路２０１が表示制御回路２００内に設けられている。この補助容量信号生成回路２０１は、従来のＣＳドライバのようには各ＣＳラインの電位を順次変化させずに、各ＣＳラインの電位を一括で変化させるので、当該従来のＣＳドライバよりも回路規模が小さい。このため、額縁面積を縮小しつつ消費電力を低減することができる。また、低周波リフレッシュ駆動が行われるので、さらなる低消費電力化を図ることができる。さらに、全ＣＳライン（補助容量信号）の電位が同時に変化するので、ゲートラインの走査順が昇順（ＧＬ１→ＧＬ２→…→ＧＬｍの順）であるか降順（ＧＬｍ→…→ＧＬ２→ＧＬ１の順）であるかに関わらずＣＳ駆動を行うことができる。 <2.4 Effect>
According to the present embodiment, as in the first embodiment, the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the odd-numbered and even-numbered CS lines are applied during the idle period T2. An auxiliary capacitance signal generation circuit 201 that changes all at once is provided in the display control circuit 200. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved. Further, since the potentials of all the CS lines (auxiliary capacitance signals) change simultaneously, the scanning order of the gate lines is ascending (GL1 → GL2 → ... → GLm) or descending (GLm → ... → GL2 → GL1). ) CS driving can be performed regardless of whether or not.
　また、本実施形態によれば、ＣＳラインＣＬ１～ＣＬｎがソースラインＳＬ１～ＳＬｎにそれぞれ沿って設けられ、互いに電位の異なる第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂがそれぞれ奇数列目および偶数列目のＣＳラインに与えられる。そして、走査期間Ｔ１において、奇数列目および偶数列目の映像信号が互いに異なる極性になると共に、第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂが休止期間Ｔ２において電位が同時に変化する。このため、ＣＳ駆動を行いつつ、所定本数（本実施形態では１本）のソースライン毎に、かつ、１フレーム期間毎に映像信号の極性を変化させるライン反転駆動（「ソースライン反転駆動」ともいう）を行うことができる。 Further, according to the present embodiment, the CS lines CL1 to CLn are provided along the source lines SL1 to SLn, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered columns and It is given to the CS line of the even column. In the scanning period T1, the odd-numbered and even-numbered video signals have different polarities, and the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2. For this reason, line inversion driving ("source line inversion driving") that changes the polarity of the video signal for each predetermined number of source lines (one in this embodiment) and for each frame period while performing CS driving. Say).
　また、ＣＳラインをゲートライン、ソースライン、およびドレイン電極と同じ材料で形成した場合には、ＣＳラインＥｃｓをゲートラインと同じ工程で形成することができ、ＣＳバスラインＢｃｓをソースラインおよびドレインラインと同じ工程で形成することができる。このため、コストを低減することができる。 When the CS line is formed of the same material as the gate line, the source line, and the drain electrode, the CS line Ecs can be formed in the same process as the gate line, and the CS bus line Bcs is set as the source line and the drain line. It can be formed by the same process. For this reason, cost can be reduced.
　また、ＣＳラインを透明電極として形成した場合には、ＣＳラインを形成することによる開口率の低下を抑制することができる。 Moreover, when the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
　＜３．第３の実施形態＞
　＜３．１　表示部の構成＞
　図１６は、本発明の第３の実施形態における表示部５００の構成を示す回路図である。なお、本実施形態は、表示部５００の構成、液晶表示装置の動作、および画素レイアウトの実現例以外については上記第１の実施形態と同様であるので、当該同様の部分についての説明を省略する。図１６に示すように、本実施形態では上記第１の実施形態と同様にＣＳラインＣＬ１～ＣＬｍがゲートラインＧＬ１～ＧＬｍにそれぞれ沿って配置されている一方で、さらに１本のＣＳラインＣＬ０が１行目のＣＳラインＣＬ１の先行のＣＳラインとして設けられている。以下では、このＣＳラインＣＬ０を「０行目のＣＳライン」ということがある。また、このＣＳラインＣＬ０は偶数行目のＣＳラインに属するものとする。 <3. Third Embodiment>
<3.1 Configuration of display unit>
FIG. 16 is a circuit diagram showing a configuration of the display unit 500 according to the third embodiment of the present invention. Note that this embodiment is the same as the first embodiment except for the configuration of the display unit 500, the operation of the liquid crystal display device, and an implementation example of the pixel layout, and thus description of the same parts is omitted. . As shown in FIG. 16, in the present embodiment, CS lines CL1 to CLm are arranged along the gate lines GL1 to GLm, respectively, as in the first embodiment, while one CS line CL0 is further provided. It is provided as a CS line preceding the CS line CL1 in the first row. Hereinafter, the CS line CL0 may be referred to as a “0th CS line”. The CS line CL0 is assumed to belong to the even-numbered CS line.
　奇数列目の画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタ５０のゲート端子が接続されたゲートラインに沿って配置されたＣＳラインと、当該画素形成部における画素電極Ｅｐとの間に形成されている。これに対して、偶数列目の画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタ５０のゲート端子が接続されたゲートラインに沿って配置されたＣＳラインの先行のＣＳラインと、当該画素形成部における画素電極Ｅｐとの間に形成されている。 The auxiliary capacitance Ccs in the pixel formation portion in the odd-numbered column is between the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Is formed. On the other hand, the auxiliary capacitance Ccs in the pixel formation portion in the even-numbered column includes the CS line preceding the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected, and It is formed between the pixel electrode Ep in the pixel formation portion.
　奇数行目のＣＳラインＣＬ１、ＣＬ３、…ＣＬｍ－１には第１補助容量信号ＣＳａが与えられる。偶数行目のＣＬ０、ＣＬ２、ＣＬ４、…ＣＬｍには第２補助容量信号ＣＳｂが与えられる。 The first auxiliary capacitance signal CSa is supplied to the odd-numbered CS lines CL1, CL3,... CLm-1. The second auxiliary capacitance signal CSb is supplied to CL0, CL2, CL4,.
　＜３．２　液晶表示装置の動作＞
　図１７は、本実施形態に係る液晶表示装置の動作を説明するための信号波形図である。なお、この液晶表示装置の動作のうち、上記第１の実施形態におけるものと同様の部分については適宜説明を省略する。 <3.2 Operation of liquid crystal display device>
FIG. 17 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment. Of the operation of the liquid crystal display device, the description of the same parts as those in the first embodiment will be omitted as appropriate.
　＜３．２．１　走査期間での動作＞
　図１７に示すように、走査期間Ｔ１における第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂはそれぞれ、互いに異なる電位である低電位Ｖｌおよび高電位Ｖｈになっている。すなわち、奇数行目のＣＳラインは低電位Ｖｌに、偶数行目のＣＳラインは高電位Ｖｈになっている。映像信号ＳＳ（１）～ＳＳ（ｎ）が１水平走査期間毎に正極性と負極性とを繰り返し、かつ、奇数列目および偶数列目の映像信号が互いに異なる極性になっている。 <3.2.1 Operation during scanning period>
As shown in FIG. 17, the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other, respectively. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh. The video signals SS (1) to SS (n) repeat the positive polarity and the negative polarity every horizontal scanning period, and the odd-numbered and even-numbered video signals have different polarities.
　まず、第１選択期間になると、当該ゲートラインＧＬ１にゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、１行目の画素電位である１行１列目の画素電位Ｖｐ（１，１）および１行２列目の画素電位Ｖｐ（１，２）が書き込み電位Ｖｓｉｇになる。図１７に示すように、この第１選択期間では奇数列目および偶数列目の映像信号がそれぞれ正極性および負極性になっているので、１行目における奇数列目および偶数列目の画素電位はそれぞれ正極性および負極性になる。このように本実施形態では、Ｘ方向に隣接する画素形成部における画素電位が互いに異なる極性になる。 First, in the first selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (1,1) in the first row and the first column, which is the pixel potential in the first row, and the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig. As shown in FIG. 17, since the video signals in the odd-numbered columns and the even-numbered columns have the positive polarity and the negative polarity in the first selection period, respectively, the pixel potentials in the odd-numbered columns and the even-numbered columns in the first row Respectively have a positive polarity and a negative polarity. As described above, in the present embodiment, the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities.
　次に、第２選択期間になると、当該ゲートラインＧＬ２にゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、２行目の画素電位である２行１列目の画素電位Ｖｐ（２，１）が書き込み電位Ｖｓｉｇになる。図１７に示すように、この第２選択期間では奇数列目および偶数列目の映像信号がそれぞれ負極性および正極性になっているので、２行目における奇数列目および偶数列目の画素電位はそれぞれ負極性および正極性になる。 Next, in the second selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (2, 1) in the second row and the first column, which is the pixel potential in the second row, becomes the write potential Vsig. As shown in FIG. 17, in the second selection period, since the odd-numbered and even-numbered video signals are negative and positive, respectively, the pixel potentials of the odd-numbered and even-numbered columns in the second row Respectively have negative polarity and positive polarity.
　以降、奇数行目および偶数行目に関して、それぞれ第１選択期間および第２選択期間と同様の動作が行われる。 Thereafter, operations similar to those in the first selection period and the second selection period are performed for the odd-numbered rows and the even-numbered rows, respectively.
　最後に、第ｍ選択期間になると、当該ゲートラインＧＬｍにゲート端子が接続された薄膜トランジスタ５０がオン状態になるので、当該薄膜トランジスタ５０を介して与えられる映像信号により画素容量Ｃｐが充電される。その結果、ｍ行目の画素電位であるｍ行１列目の画素電位Ｖｐ（ｍ，１）が書き込み電位Ｖｓｉｇになる。図１７に示すように、この第ｍ選択期間では奇数列目および偶数列目の映像信号がそれぞれ負極性および正極性になっているので、ｍ行目における奇数列目および偶数列目の画素電位はそれぞれ負極性および正極性になる。 Finally, in the m-th selection period, the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50. As a result, the pixel potential Vp (m, 1) in the m-th row and the first column, which is the pixel potential in the m-th row, becomes the write potential Vsig. As shown in FIG. 17, since the odd-numbered and even-numbered video signals are negative and positive in the m-th selection period, respectively, the pixel potentials of the odd-numbered and even-numbered columns in the m-th row Respectively have negative polarity and positive polarity.
　このように本実施形態では、Ｘ方向に隣接する画素形成部のみならずＹ方向に隣接する画素形成部についても、画素電位が互いに異なる極性になる。 As described above, in this embodiment, the pixel potentials have different polarities not only in the pixel forming portion adjacent in the X direction but also in the pixel forming portion adjacent in the Y direction.
　また、正極性の映像信号が書き込まれている画素電極Ｅｐとの間に補助容量Ｃｃｓを形成している奇数行目のＣＳライン、および負極性の映像信号が書き込まれている画素電極Ｅｐとの間に補助容量Ｃｃｓを形成している偶数行目のＣＳラインにそれぞれ与えられる第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂは、互いに電位が異なっている。 Also, the odd-numbered CS line forming the auxiliary capacitance Ccs between the pixel electrode Ep in which the positive video signal is written and the pixel electrode Ep in which the negative video signal is written. The first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
　＜３．２．２　休止期間での動作＞
　休止期間Ｔ２が開始すると、第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂは第１の実施形態と同様の変化をする。このため、奇数行目のＣＳラインは低電位Ｖｌから高電位Ｖｈに、偶数行目のＣＳラインは高電位Ｖｈから低電位Ｖｌに互いに同じタイミングで変化する。上述のように、奇数行目のＣＳラインに補助容量Ｃｃｓを介して接続された奇数列目の画素電極Ｅｐの画素電位（奇数列目の画素電位）は正極性に、偶数列目の画素電極Ｅｐの画素電位（偶数列目の画素電位）は負極性になっている。また、偶数行目のＣＳラインに補助容量Ｃｃｓを介して接続された奇数列目の画素電極Ｅｐの画素電位（奇数列目の画素電位）は負極性に、偶数列目の画素電極Ｅｐの画素電位（偶数列目の画素電位）は正極性になっている。なお、この休止期間Ｔ２での基本的な動作は上記第１の実施形態と同様であるので、その説明を省略する。 <3.2.2 Operation during idle period>
When the suspension period T2 starts, the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change in the same manner as in the first embodiment. Therefore, the odd-numbered CS lines change from the low potential Vl to the high potential Vh, and the even-numbered CS lines change from the high potential Vh to the low potential Vl at the same timing. As described above, the pixel potential (pixel potential of the odd-numbered column) of the pixel electrode Ep of the odd-numbered column connected to the CS line of the odd-numbered row via the auxiliary capacitor Ccs has a positive polarity, and the pixel electrode of the even-numbered column The pixel potential of Ep (pixel potential in even-numbered columns) is negative. Further, the pixel potential of the odd-numbered pixel electrode Ep (pixel potential of the odd-numbered column) connected to the even-numbered CS line via the auxiliary capacitor Ccs has a negative polarity, and the pixels of the even-numbered pixel electrode Ep. The potential (pixel potential in even-numbered columns) is positive. Note that the basic operation in the suspension period T2 is the same as that in the first embodiment, and a description thereof will be omitted.
　＜３．３　画素レイアウト＞
　図１８は、本実施形態における画素レイアウトの実現例を示す平面図である。なお、上記第１の実施形態における各実現例と同様の部分については適宜説明を省略する。また、本実現例の基本的な層構造および各構成要素の材料は上記第１の実施形態における第２の実現例（図８を参照）におけるものと同様である。図１８に示すように、本実現例では、ソースラインとゲートラインとが互いに交差するように設けられ、ＣＳラインがゲートラインに沿って設けられている。このＣＳラインはＩＴＯ等からなる透明電極として形成されている。このＣＳラインは、Ｘ方向に隣接する画素形成部にわたって連続に形成されている。図１８では、ＣＳラインが薄膜トランジスタ５０を覆わない構成となっているが、本発明はこれに限定されるものではない。 <3.3 Pixel layout>
FIG. 18 is a plan view showing an implementation example of the pixel layout in the present embodiment. Note that description of parts similar to those of the implementation examples in the first embodiment is omitted as appropriate. Further, the basic layer structure and the material of each component in the present implementation example are the same as those in the second implementation example (see FIG. 8) in the first embodiment. As shown in FIG. 18, in this implementation example, the source line and the gate line are provided so as to cross each other, and the CS line is provided along the gate line. The CS line is formed as a transparent electrode made of ITO or the like. The CS line is continuously formed over pixel forming portions adjacent in the X direction. In FIG. 18, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
　本実現例における各ＣＳラインは、２本のＣＳラインにより構成されている。以下では、これらの２本のＣＳラインのうちの一方を「第１ＣＳライン」といい、符号ＣＬａを付す。また、これらの２本のＣＳラインのうちの他方を「第２ＣＳライン」といい、符号ＣＬｂを付す。ここで、各ＣＳラインにおいて、第１ＣＳラインおよび第２ＣＳラインには互いに同じ極性の電位が与えられる（ただし、ＣＳライン毎には極性が反転する）。各ＣＳラインを構成する第１ＣＳラインＣＬａおよび第２ＣＳラインは当該ＣＳラインの沿うゲートラインを挟んで両側に配置されている。図１８においてｊが奇数であるとすると、奇数列目の画素形成部の画素電極Ｅｐに対向する（以下の本実現例に係る画素レイアウトの説明では単に「画素形成部における」という）第１ＣＳラインＣＬａの面積（Ｙ方向の幅）は偶数列目の画素形成部における第１ＣＳラインＣＬａの面積よりも大きい。また、奇数列目の画素形成部における第２ＣＳラインＣＬｂの面積（Ｙ方向の幅）は偶数列目の画素形成部における第２ＣＳラインＣＬｂの面積よりも小さい。なお、各画素形成部における第１ＣＳラインＣＬａの面積と第２ＣＳラインＣＬｂの面積との和は略等しい。 Each CS line in this implementation example is composed of two CS lines. Hereinafter, one of these two CS lines is referred to as a “first CS line”, and is denoted by a symbol CLa. Further, the other of these two CS lines is referred to as a “second CS line”, and is denoted by reference symbol CLb. Here, in each CS line, potentials having the same polarity are applied to the first CS line and the second CS line (however, the polarity is inverted for each CS line). The first CS line CLa and the second CS line constituting each CS line are arranged on both sides of the gate line along the CS line. In FIG. 18, when j is an odd number, the first CS line is opposed to the pixel electrode Ep of the pixel formation portion in the odd-numbered column (hereinafter simply referred to as “in the pixel formation portion” in the description of the pixel layout according to the present implementation example). The area of CLa (the width in the Y direction) is larger than the area of the first CS line CLa in the pixel formation portion in the even-numbered column. In addition, the area (width in the Y direction) of the second CS line CLb in the pixel formation portion in the odd-numbered column is smaller than the area of the second CS line CLb in the pixel formation portion in the even-numbered column. Note that the sum of the area of the first CS line CLa and the area of the second CS line CLb in each pixel formation portion is substantially equal.
　本実現例における各画素形成部の補助容量Ｃｃｓは、詳細には、当該画素形成部における第１ＣＳラインＣＬａと画素電極Ｅｐとの間に形成される補助容量（以下「第１補助容量」といい、符号Ｃｃｓａを付す）、および当該画素形成部における第２ＣＳラインＣＬｂと画素電極Ｅｐとの間に形成される補助容量（以下「第２補助容量」といい、符号Ｃｃｓｂを付す）により構成されている。ただし、奇数行目の画素形成部における第１ＣＳラインＣＬａは当該画素形成部における第２ＣＳラインＣＬｂよりも面積が大きいので、当該画素形成部における補助容量Ｃｃｓは実質的には第１補助容量Ｃｃｓａにより構成されている。また、偶数行目の画素形成部における第２ＣＳラインＣＬｂは当該画素形成部における第１ＣＳラインＣＬａよりも大きいので、当該画素形成部における補助容量Ｃｃｓは実質的には第２補助容量Ｃｃｓｂにより構成されている。 The auxiliary capacitance Ccs of each pixel formation portion in this implementation example is specifically referred to as an auxiliary capacitance (hereinafter referred to as “first auxiliary capacitance”) formed between the first CS line CLa and the pixel electrode Ep in the pixel formation portion. , And an auxiliary capacitor formed between the second CS line CLb and the pixel electrode Ep in the pixel formation portion (hereinafter referred to as “second auxiliary capacitor”, and attached with a symbol Ccsb). Yes. However, since the first CS line CLa in the pixel formation portion in the odd-numbered row has a larger area than the second CS line CLb in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured. In addition, since the second CS line CLb in the pixel formation portion in the even-numbered row is larger than the first CS line CLa in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially constituted by the second auxiliary capacitance Ccsb. ing.
　各画素形成部における第１ＣＳラインＣＬａおよび第２ＣＳラインＣＬｂは互いに隣接するＣＳラインを構成している。例えば、ｉ行ｊ列目の画素形成部における第１ＣＳラインＣＬａはｉ行目のＣＳラインＣＬｉを構成し、第２ＣＳラインＣＬｂはｉ－１行目のＣＳラインＣＬｉ－１を構成している。本実施形態では、奇数行目および偶数行目のＣＳラインには互いに異なる電位が与えられる、すなわち、各画素形成部における第１ＣＳラインＣＬａおよび第２ＣＳラインＣＬｂには互いに異なる電位（高電位Ｖｈまたは低電位Ｖｌ）が与えられる。このため、休止期間Ｔ２において全ＣＳラインの電位が同時に変化した後の各画素電位Ｖｐは、上記式（１）を変形した下記の式（２）で示される。
　Ｖｐ＝Ｖｓｉｇ＋ΔＶｃｓ
　　　＝Ｖｓｉｇ
＋（（Ｃｃｓａ－Ｃｃｓｂ）／（Ｃｌｃ＋Ｃｃｓａ＋Ｃｃｓｂ＋Ｃｐａ））
×（Ｖｈ－Ｖｌ）…（２）
ただし、偶数行目の画素電位Ｖｐでは第１補助容量Ｃｃｓａと第２補助容量Ｃｃｓｂとの大小関係が上記式（２）におけるものと逆になるので、当該偶数行目の画素電位ＶｐについてはＣｃｓａ＝Ｃｃｓｂ、Ｃｃｓｂ＝Ｃｃｓａとなる。 The first CS line CLa and the second CS line CLb in each pixel forming portion constitute adjacent CS lines. For example, the first CS line CLa in the pixel formation portion in the i-th row and j-th column constitutes the i-th row CS line CLi, and the second CS line CLb constitutes the i-th row CS line CLi-1. In the present embodiment, different potentials are applied to the odd-numbered and even-numbered CS lines, that is, the first CS line CLa and the second CS line CLb in each pixel formation portion have different potentials (high potential Vh or A low potential Vl) is applied. For this reason, each pixel potential Vp after the potentials of all the CS lines simultaneously change in the rest period T2 is expressed by the following formula (2) obtained by modifying the above formula (1).
Vp = Vsig + ΔVcs
= Vsig
+ ((Ccsa-Ccsb) / (Clc + Ccsa + Ccsb + Cpa))
× (Vh−Vl) (2)
However, since the magnitude relationship between the first auxiliary capacitor Ccsa and the second auxiliary capacitor Ccsb is opposite to that in the above formula (2) at the pixel potential Vp in the even-numbered row, the pixel potential Vp in the even-numbered row is Ccsa. = Ccsb, Ccsb = Ccsa.
　本実現例では、ＣＳラインが透明電極として形成されているので、開口率を低下させることなくＣＳラインを形成することができる。 In this realization example, since the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
　＜３．４　効果＞
　本実施形態によれば、上記第１の実施形態と同様に、奇数行目および偶数行目のＣＳラインにそれぞれ与える第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂの電位を休止期間Ｔ２において一括で変化させる補助容量信号生成回路２０１が表示制御回路２００内に設けられている。この補助容量信号生成回路２０１は、従来のＣＳドライバのようには各ＣＳラインの電位を順次変化させずに、各ＣＳラインの電位を一括で変化させるので、当該従来のＣＳドライバよりも回路規模が小さい。このため、額縁面積を縮小しつつ消費電力を低減することができる。また、低周波リフレッシュ駆動が行われるので、さらなる低消費電力化を図ることができる。さらに、全ＣＳライン（補助容量信号）の電位が同時に変化するので、ゲートラインの走査順が昇順（ＧＬ１→ＧＬ２→…→ＧＬｍの順）であるか降順（ＧＬｍ→…→ＧＬ２→ＧＬ１の順）であるかに関わらずＣＳ駆動を行うことができる。 <3.4 Effects>
According to the present embodiment, as in the first embodiment, the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the odd-numbered and even-numbered CS lines, respectively, are applied in the idle period T2. An auxiliary capacitance signal generation circuit 201 that changes all at once is provided in the display control circuit 200. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved. Further, since the potentials of all the CS lines (auxiliary capacitance signals) change simultaneously, the scanning order of the gate lines is ascending (GL1 → GL2 → ... → GLm) or descending (GLm → ... → GL2 → GL1). ) CS driving can be performed regardless of whether or not.
　また、本実施形態によれば、ＣＳラインＣＬ１～ＣＬｍがゲートラインＧＬ１～ＧＬｍにそれぞれ沿って設けられ、互いに電位の異なる第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂがそれぞれ奇数行目および偶数列目のＣＳラインに与えられる。そして、走査期間Ｔ１において各映像信号の極性が１水平走査期間毎に、かつ１フレーム期間毎に反転し、奇数列目および偶数列目の映像信号が互いに異なる極性になり、さらに、第１補助容量信号ＣＳａおよび第２補助容量信号ＣＳｂが休止期間Ｔ２において電位が同時に変化する。このため、ＣＳ駆動を行いつつ、Ｘ方向およびＹ方向に隣接する画素形成部毎に、かつ、１フレーム期間毎に映像信号の極性を変化させるドット反転駆動を行うことができる。 Further, according to the present embodiment, the CS lines CL1 to CLm are provided along the gate lines GL1 to GLm, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered rows and It is given to the CS line of the even column. Then, in the scanning period T1, the polarity of each video signal is inverted every horizontal scanning period and every frame period, the video signals in the odd-numbered columns and the even-numbered columns have different polarities, and the first auxiliary The potentials of the capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2. For this reason, while performing CS driving, it is possible to perform dot inversion driving that changes the polarity of the video signal for each pixel forming portion adjacent in the X direction and the Y direction and for each frame period.
　また、ＣＳラインを透明電極として形成した場合には、ＣＳラインを形成することによる開口率の低下を抑制することができる。 Moreover, when the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
　＜３．５　第１の変形例＞
　図１９は、本発明の第３の実施形態の第１の変形例における表示部５００の構成を示す回路図である。なお、本変形例は、表示部５００の構成、および画素レイアウトの実現例以外については上記第１の実施形態および第３の実施形態と同様であるので、当該同様の部分についての説明を省略する。図１９に示すように、本実施形態では上記第２の実施形態と同様にＣＳラインＣＬ１～ＣＬｎがソースラインＳＬ１～ＳＬｎにそれぞれ沿って配置されている一方で、さらに１本のＣＳラインＣＬ０が１列目のＣＳラインＣＬ１の先行のＣＳラインとして設けられている。以下では、このＣＳラインＣＬ０を「０列目のＣＳライン」ということがある。また、このＣＳラインＣＬ０は偶数列目のＣＳラインに属するものとする。 <3.5 First Modification>
FIG. 19 is a circuit diagram showing a configuration of the display unit 500 in the first modification of the third embodiment of the present invention. Since the present modification is the same as the first embodiment and the third embodiment except for the configuration of the display unit 500 and the pixel layout implementation example, the description of the same parts is omitted. . As shown in FIG. 19, in the present embodiment, CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively, as in the second embodiment, while one CS line CL0 is further provided. It is provided as a CS line preceding the CS line CL1 in the first column. Hereinafter, the CS line CL0 may be referred to as a “0th column CS line”. The CS line CL0 is assumed to belong to the even-numbered CS line.
　各ＣＳラインは、当該ＣＳラインに沿うソースラインと当該ソースラインの後続のソースラインとに対応している。奇数行目の画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタのソース端子が接続されたソースラインに沿って配置されたＣＳライン（すなわち当該ソースラインが対応するＣＳライン）と、当該画素形成部における画素電極Ｅｐとの間に形成されている。これに対して、偶数行目の画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタのソース端子が接続されたソースラインに沿って配置されたＣＳラインの先行のＣＳライン（すなわち当該ソースラインが対応するＣＳライン）と、当該画素形成部における画素電極Ｅｐとの間に形成されている。 Each CS line corresponds to a source line along the CS line and a source line subsequent to the source line. The auxiliary capacitance Ccs in the pixel formation portion in the odd-numbered rows includes a CS line (that is, a CS line corresponding to the source line) arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected, and It is formed between the pixel electrode Ep in the pixel formation portion. On the other hand, the auxiliary capacitance Ccs in the pixel formation portion in the even-numbered row is the CS line preceding the CS line (that is, the source) arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected. The line is formed between the corresponding CS line) and the pixel electrode Ep in the pixel formation portion.
　奇数列目のＣＳラインＣＬ１、ＣＬ３、…ＣＬｎ－１には第１補助容量信号ＣＳａが与えられる。偶数列目のＣＳラインＣＬ０、ＣＬ２、ＣＬ４、…ＣＬｎには第２補助容量信号ＣＳｂが与えられる。なお、液晶表示装置の動作については上記第３の実施形態と同様であるので説明を省略する（図１７を参照）。 The first auxiliary capacitance signal CSa is supplied to the odd-numbered CS lines CL1, CL3,... CLn-1. The second auxiliary capacitance signal CSb is applied to the CS lines CL0, CL2, CL4,. Since the operation of the liquid crystal display device is the same as that of the third embodiment, description thereof is omitted (see FIG. 17).
　図２０は、本変形例における画素レイアウトの実現例を示す平面図である。なお、上記第１の実施形態および第３の実施形態における各実現例と同様の部分については適宜説明を省略する。また、本実現例の基本的な層構造および各構成要素の材料は上記第２の実施形態における第２の実現例（図１５を参照）におけるものと同様である。図２０に示すように、本実現例では、ソースラインとゲートラインとが互いに交差するように設けられ、ＣＳラインがソースラインに沿って（より詳細にはソースラインを覆うように）設けられている。このＣＳラインはＩＴＯ等からなる透明電極として形成されている。このＣＳラインは、Ｙ方向に隣接する画素形成部にわたって連続に形成されている。図２０では、ＣＳラインが薄膜トランジスタ５０を覆わない構成となっているが、本発明はこれに限定されるものではない。 FIG. 20 is a plan view showing an implementation example of the pixel layout in this modification. In addition, description is abbreviate | omitted suitably about the part similar to each implementation example in the said 1st Embodiment and 3rd Embodiment. Further, the basic layer structure and the material of each component in the present implementation example are the same as those in the second implementation example (see FIG. 15) in the second embodiment. As shown in FIG. 20, in this implementation example, the source line and the gate line are provided so as to cross each other, and the CS line is provided along the source line (more specifically, so as to cover the source line). Yes. The CS line is formed as a transparent electrode made of ITO or the like. The CS line is continuously formed over pixel forming portions adjacent in the Y direction. Although the CS line does not cover the thin film transistor 50 in FIG. 20, the present invention is not limited to this.
　図２０においてｉが奇数であるとすると、各ＣＳラインは、当該ＣＳラインが覆うソースラインに対応する奇数行目の画素形成部側に突出し（Ｘ方向の幅が大きくなり）、かつ、当該画素形成部の画素電極Ｅｐに対向している。また、各ＣＳラインは、当該ＣＳラインが覆うソースラインの先行のソースラインに対応する偶数行目の画素形成部側に突出し、かつ、当該画素形成部の画素電極Ｅｐに対向している。以下では、このように画素形成部側に突出し、当該画素形成部の画素電極Ｅｐに対向したＣＳラインの部分を「メインＣＳライン」という。なお、各ＣＳラインのメインＣＳラインのＸ方向の反対側についても、図２０に示すように僅かに画素形成部に対向している。以下では、このように僅かに画素形成部に対向したＣＳラインの部分を「サブＣＳライン」という。なお、各画素形成部の画素電極Ｅｐに対向した（各画素形成部における）メインＣＳラインは、当該画素形成部におけるサブＣＳラインよりも面積が大きい。また、各画素形成部におけるメインＣＳラインの面積とサブＣＳラインの面積との和は略等しい。 If i is an odd number in FIG. 20, each CS line protrudes toward the pixel forming portion on the odd-numbered row corresponding to the source line covered by the CS line (the width in the X direction increases), and the pixel Opposite the pixel electrode Ep of the formation part. In addition, each CS line protrudes to the pixel formation part side of the even-numbered row corresponding to the source line preceding the source line covered by the CS line, and faces the pixel electrode Ep of the pixel formation part. Hereinafter, the portion of the CS line that protrudes toward the pixel formation portion and faces the pixel electrode Ep of the pixel formation portion is referred to as a “main CS line”. Note that the opposite side of the main CS line of each CS line in the X direction also slightly faces the pixel forming portion as shown in FIG. Hereinafter, the portion of the CS line slightly facing the pixel forming portion is referred to as a “sub CS line”. Note that the main CS line (in each pixel formation portion) facing the pixel electrode Ep in each pixel formation portion has a larger area than the sub CS line in the pixel formation portion. Further, the sum of the area of the main CS line and the area of the sub CS line in each pixel forming portion is substantially equal.
　本実現例における各画素形成部の補助容量Ｃｃｓは、詳細には、当該画素形成部におけるメインＣＳラインと画素電極Ｅｐとの間に形成される補助容量（上記第３の実施形態の実現例と同様に「第１補助容量」といい、符号Ｃｃｓａを付す）、および当該画素形成部におけるサブＣＳラインと画素電極Ｅｐとの間に形成される補助容量（上記第３の実施形態の実現例と同様に「第２補助容量」といい、符号Ｃｃｓｂを付す）により構成されている。ただし、上述のように、各画素形成部におけるメインＣＳラインは当該画素形成部におけるサブＣＳラインよりも面積が大きいので、当該画素形成部における補助容量Ｃｃｓは実質的には第１補助容量Ｃｃｓａにより構成されている。 In detail, the auxiliary capacitance Ccs of each pixel formation portion in this implementation example is more specifically the auxiliary capacitance formed between the main CS line and the pixel electrode Ep in the pixel formation portion (the implementation example of the third embodiment). Similarly, it is referred to as “first auxiliary capacitor”, and is denoted by Ccsa), and an auxiliary capacitor formed between the sub-CS line and the pixel electrode Ep in the pixel formation portion (an implementation example of the third embodiment) Similarly, it is referred to as a “second auxiliary capacity” and is denoted by a symbol Ccsb). However, as described above, since the main CS line in each pixel formation portion has a larger area than the sub-CS line in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
　なお、休止期間Ｔ２において全ＣＳラインの電位が同時に変化した後の各画素電位Ｖｐについては、上記第３の実施形態の実現例と同様に上記式（２）により示される。 Note that each pixel potential Vp after the potentials of all the CS lines simultaneously change in the rest period T2 is expressed by the above equation (2) as in the implementation example of the third embodiment.
　本変形例によっても、上記第３の実施形態と同様にドット反転駆動を行うことができる。 Also according to this modification, it is possible to perform dot inversion driving as in the third embodiment.
　＜３．６　第２の変形例＞
　図２１は、本発明の第３の実施形態の第２の変形例における表示部５００の構成を示す回路図である。なお、上記各実施形態と共通する部分については適宜説明を省略する。図２１に示すように、本実施形態では上記第２の実施形態と同様にＣＳラインＣＬ１～ＣＬｎがソースラインＳＬ１～ＳＬｎにそれぞれ沿って配置されている一方で、さらに１本のソースラインＳＬｎ＋１がｎ列目のソースラインＳＬｎの後続のソースラインとして設けられている。このソースラインＳＬｎ＋１は奇数列目のソースラインに属するものとする。本実施形態ではまた、さらに１本のＣＳラインＣＬｎ＋１がｎ列目のＣＳラインＣＬｎ＋１の後続のＣＳラインとして設けられている。このＣＳラインＣＬｎ＋１は奇数列目のＣＳラインに属するものとする。 <3.6 Second Modification>
FIG. 21 is a circuit diagram showing a configuration of the display unit 500 in the second modification example of the third embodiment of the present invention. In addition, description is abbreviate | omitted suitably about the part which is common in said each embodiment. As shown in FIG. 21, in the present embodiment, CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively, as in the second embodiment, while one more source line SLn + 1 is provided. It is provided as a source line subsequent to the n-th source line SLn. This source line SLn + 1 belongs to the odd-numbered source line. In this embodiment, one CS line CLn + 1 is further provided as a CS line subsequent to the CS line CLn + 1 in the nth column. It is assumed that the CS line CLn + 1 belongs to the odd-numbered CS line.
　本変形例では、奇数行目の画素形成部（画素電極Ｅｐ）と、当該画素形成部と同一列（Ｙ方向に並び）かつ偶数行目の画素形成部とは、互いに隣接するソースラインにそれぞれ対応している。すなわち、同一列における奇数行目の画素形成部と偶数行目の画素形成部とは互いに隣接するソースラインにそれぞれ対応している。より詳細には、図２１に示すように、奇数行目の画素形成部における薄膜トランジスタのソース端子は当該画素形成部と同一列のソースラインに接続されている。一方、奇数行目の画素形成部における薄膜トランジスタのソース端子は当該画素形成部の直後の列のソースラインに接続されている。また、各画素形成部における補助容量Ｃｃｓは、当該画素形成部における薄膜トランジスタのソース端子が接続されたソースラインに沿って配置されたＣＳラインと、当該画素形成部における画素電極Ｅｐとの間に形成されている。なお、ソースラインに与えられる映像信号およびＣＳラインに与えられる補助容量信号は上記第２の実施形態と同様のものである。 In the present modification, the pixel forming portion (pixel electrode Ep) in the odd-numbered row and the pixel forming portion in the same column (aligned in the Y direction) and the even-numbered row as the pixel forming portion are respectively connected to the adjacent source lines. It corresponds. That is, the odd-numbered pixel forming portions and the even-numbered pixel forming portions in the same column respectively correspond to the adjacent source lines. More specifically, as shown in FIG. 21, the source terminal of the thin film transistor in the pixel formation portion in the odd-numbered rows is connected to the source line in the same column as the pixel formation portion. On the other hand, the source terminal of the thin film transistor in the pixel formation portion in the odd-numbered row is connected to the source line of the column immediately after the pixel formation portion. Further, the auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Has been. The video signal applied to the source line and the auxiliary capacitance signal applied to the CS line are the same as those in the second embodiment.
　同一列における奇数行目の画素形成部と偶数行目の画素形成部とが互いに隣接するソースラインにそれぞれ対応した構成において上記第２の実施形態と同様の映像信号および補助容量信号によって動作が行われることにより、Ｘ方向に隣接する画素形成部における画素電位が互いに異なる極性になるのみならず、Ｙ方向に隣接する画素形成部における画素電位も互いに異なる極性になる。すなわち、上記第３の実施形態およびその第１の変形例と同様に、ドット反転駆動が行われることになる。 In the configuration in which the odd-numbered pixel forming portions and the even-numbered pixel forming portions in the same column respectively correspond to the adjacent source lines, the operation is performed by the same video signal and auxiliary capacitance signal as in the second embodiment. As a result, the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities, and the pixel potentials in the pixel formation portions adjacent in the Y direction have different polarities. That is, dot inversion driving is performed as in the third embodiment and the first modification thereof.
　図２２は、本変形例における画素レイアウトの実現例を示す平面図である。図２２に示すように、本変形例における画素レイアウトは、薄膜トランジスタの配置箇所等を除き、上記第３の実施形態の第１の変形例におけるものと基本的に同様である（図２０を参照）。すなわち、各画素形成部の補助容量Ｃｃｓは、上述の第１補助容量Ｃｃｓａおよび第２補助容量Ｃｃｓｂにより構成されている。ただし、上述のように、各画素形成部におけるメインＣＳラインは当該画素形成部におけるサブＣＳラインよりも面積が大きいので、当該画素形成部における補助容量Ｃｃｓは実質的には第１補助容量Ｃｃｓａにより構成されている。 FIG. 22 is a plan view showing an implementation example of the pixel layout in the present modification. As shown in FIG. 22, the pixel layout in this modification is basically the same as that in the first modification of the third embodiment except for the location of the thin film transistor (see FIG. 20). . In other words, the auxiliary capacitance Ccs of each pixel forming unit is configured by the first auxiliary capacitance Ccsa and the second auxiliary capacitance Ccsb described above. However, as described above, since the main CS line in each pixel formation portion has a larger area than the sub CS line in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
　以上により、本変形例によっても、上記第３の実施形態およびその第１の変形例と同様にドット反転駆動を行うことができる。 As described above, according to the present modification, it is possible to perform dot inversion driving as in the third embodiment and the first modification.
　＜４．第４の実施形態＞
　＜４．１　液晶表示装置の動作＞
　図２３は、本発明の第４の実施形態に係る液晶表示装置の動作を説明するための信号波形図である。なお、本実施形態は、液晶表示装置の動作以外については上記第１の実施形態と同様であるので、当該同様の部分についての説明を省略する。また、この液晶表示装置の動作のうち、上記第１の実施形態におけるものと同様の部分についても適宜説明を省略する。本実施形態では、走査期間Ｔ１の長さは上記第１の実施形態におけるものと同じ８．３ｍｓｅｃであるのに対して、休止期間Ｔ２の長さは、上記第１の実施形態におけるものと異なり８．３ｍｓｅｃである。すなわち、走査期間Ｔ１と同じ長さの休止期間Ｔ２が設けられている。 <4. Fourth Embodiment>
<4.1 Operation of liquid crystal display device>
FIG. 23 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the fourth embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the operation of the liquid crystal display device, the description of the same portion is omitted. Of the operation of the liquid crystal display device, the description of the same parts as those in the first embodiment will be omitted as appropriate. In the present embodiment, the length of the scanning period T1 is 8.3 msec, which is the same as that in the first embodiment, whereas the length of the pause period T2 is different from that in the first embodiment. It is 8.3 msec. That is, a pause period T2 having the same length as the scanning period T1 is provided.
　このように、走査期間Ｔ１の長さに対して休止期間Ｔ２の長さが十分に確保されていない場合、上述のように１～ｍ行目で１フレーム分の実効電圧に齟齬が生じ得る。しかし、本実施形態では、図２３に示すように、第１選択期間から第ｍ選択期間にかけて、各映像信号の振幅が小さくなっている。このため、走査開始側（ゲートラインの符号番号が小さい側）の行であるほど書き込み電位Ｖｓｉｇが大きくなり、走査終了側（ゲートラインの符号番号が大きい側）の行であるほど書き込み電位Ｖｓｉｇが小さくなる。これに応じて、走査開始側の行であるほど画素電位Ｖｐが大きくなり、走査終了側の行であるほど画素電位Ｖｐが小さくなる。その結果、１～ｍ行目での１フレーム分の実効電圧に齟齬が低減される。 As described above, when the length of the pause period T2 is not sufficiently secured with respect to the length of the scanning period T1, as described above, the effective voltage for one frame can be wrinkled in the 1st to mth rows. However, in the present embodiment, as shown in FIG. 23, the amplitude of each video signal decreases from the first selection period to the mth selection period. For this reason, the write potential Vsig increases as the line is on the scanning start side (side with the smaller gate line code number), and the write potential Vsig becomes closer toward the scanning end side (side with the larger gate line code number). Get smaller. In response to this, the pixel potential Vp increases as the scanning start side row, and the pixel potential Vp decreases as the scanning end side row. As a result, wrinkles are reduced in the effective voltage for one frame in the 1st to mth rows.
　なお、液晶表示装置の他の動作については上記第１の実施形態と同様であるのでその説明を省略する。 Since other operations of the liquid crystal display device are the same as those in the first embodiment, description thereof is omitted.
　＜４．２　効果＞
　本実施形態では、休止期間Ｔ２を走査期間Ｔ１と同じ長さにした場合において、第１選択期間から第ｍ選択期間にかけて各映像信号の振幅が小さくなる。このため、走査開始側の行であるほど画素電位Ｖｐが大きくなり、走査終了側の行であるほど画素電位Ｖｐが小さくなるので、１～ｍ行目での１フレーム分の実効電圧の齟齬が低減される。これにより、特に、十分な長さの休止期間Ｔ２を設けることができない場合（例えば６０Ｈｚの動画表示を行う場合等）の、表示品位の低下を抑制することができる。 <4.2 Effects>
In the present embodiment, when the pause period T2 is set to the same length as the scanning period T1, the amplitude of each video signal decreases from the first selection period to the mth selection period. For this reason, the pixel potential Vp increases as the row on the scanning start side becomes smaller, and the pixel potential Vp decreases toward the row on the scanning end side. Reduced. As a result, it is possible to suppress deterioration in display quality particularly when it is not possible to provide a sufficiently long pause period T2 (for example, when displaying a moving image at 60 Hz).
　＜５．その他＞
　上記各実施形態では、表示制御回路２００内に補助容量信号生成回路２０１が設けられるものとしたが、本発明はこれに限定されるものではない。この補助容量信号生成回路２０１は、表示制御回路２００の外部に設けられていても良い。 <5. Other>
In each of the above embodiments, the auxiliary capacitance signal generation circuit 201 is provided in the display control circuit 200, but the present invention is not limited to this. The auxiliary capacitance signal generation circuit 201 may be provided outside the display control circuit 200.
　上記第１の実施形態では１本のゲートライン毎に映像信号の極性を反転させているが、複数本のゲートライン毎に映像信号の極性を反転させても良い。また、上記第２の実施形態でも同様に、１本のソースライン毎に映像信号の極性を反転させているが、複数本のソースライン毎に映像信号の極性を反転させても良い。 In the first embodiment, the polarity of the video signal is inverted for each gate line. However, the polarity of the video signal may be inverted for a plurality of gate lines. Similarly, in the second embodiment, the polarity of the video signal is inverted for each source line. However, the polarity of the video signal may be inverted for each of a plurality of source lines.
　上記第３の実施形態および変形例における実現例では、ＣＳラインを透明電極として形成する例を挙げたが、本発明はこれに限定されるものではない。上記第３の実施形態および変形例における実現例においても、上記第１の実施形態の第２の実現例および上記第２の実施形態の第２の実現例と同様に、ＣＳラインをゲートライン等と同じ材料により形成して良い。ただしこの場合、開口率の低下に十分に留意することが望ましい。 In the implementation example in the third embodiment and the modification example, the CS line is formed as a transparent electrode. However, the present invention is not limited to this. Also in the implementation example in the third embodiment and the modified example, the CS line is replaced with a gate line or the like, similar to the second implementation example in the first embodiment and the second implementation example in the second embodiment. The same material may be used. However, in this case, it is desirable to pay sufficient attention to the decrease in aperture ratio.
　上記第４の実施形態では、休止期間Ｔ２を走査期間Ｔ１と同じ長さにしたが、走査期間Ｔ１よりも短くしても良い。 In the fourth embodiment, the rest period T2 is the same as the scanning period T1, but may be shorter than the scanning period T1.
　その他、本発明の趣旨を逸脱しない範囲で上記各実施形態を種々変形して実施することができる。 In addition, the above embodiments can be variously modified and implemented without departing from the spirit of the present invention.
　以上のように、本発明によれば、額縁面積を縮小しつつ消費電力を低減したＣＳ駆動方式の液晶表示装置およびその駆動方法を提供することができる。 As described above, according to the present invention, it is possible to provide a CS driving type liquid crystal display device that reduces power consumption while reducing the frame area, and a driving method thereof.
　本発明は、ＣＳ駆動方式の液晶表示装置に適用できる。 The present invention can be applied to a CS drive type liquid crystal display device.
５０…薄膜トランジスタ
２００…表示制御回路
３００…ソースドライバ（映像信号線駆動回路）
４００…ゲートドライバ（走査信号線駆動回路）
Ｐ（ｉ，ｊ）…画素形成部
Ｅｐ（ｉ，ｊ）…画素電極
Ｖｐ（ｉ，ｊ）…画素電位
ＧＬｉ…ゲートライン（走査信号線）
ＳＬｊ…ソースライン（映像信号線）
Ｃｃｓ…補助容量
ＣＳａ、ＣＳｂ…第１、２補助容量信号
ＳＳ（ｊ）…映像信号
Ｔ１…走査期間
Ｔ２…休止期間 50 ... Thin film transistor 200 ... Display control circuit 300 ... Source driver (video signal line drive circuit)
400: Gate driver (scanning signal line driving circuit)
P (i, j) ... pixel formation part Ep (i, j) ... pixel electrode Vp (i, j) ... pixel potential GLi ... gate line (scanning signal line)
SLj ... Source line (video signal line)
Ccs ... auxiliary capacitors CSa, CSb ... first and second auxiliary capacitance signals SS (j) ... video signal T1 ... scanning period T2 ... rest period

Claims (14)

  1. 　複数の映像信号線と、前記複数の映像信号線と交差する複数の走査信号線と、前記複数の映像信号線および前記複数の走査信号線に対応してマトリクス状に配置された複数の画素電極と、前記複数の映像信号線または前記複数の走査信号線のいずれかである複数の所定の信号線に沿って配置された複数の補助容量線と、各画素電極と前記複数の補助容量線のいずれかとの間に形成される補助容量とを含む表示部と、
    　前記複数の走査信号線が順次選択される走査期間と前記複数の走査信号線のいずれもが非選択状態になる休止期間とが、前記走査期間と前記休止期間とからなるフレーム期間を周期として交互に現れるように、前記複数の走査信号線を駆動するための走査信号線駆動回路と、
    　前記複数の映像信号線を介して前記複数の画素電極に映像信号を与えると共に、前記走査期間において、当該映像信号の極性を互いに異なる第１極性または第２極性のいずれかにする映像信号線駆動回路と、
    　各補助容量線に与えるべき補助容量信号を生成し、前記第１極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位と、前記第２極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位とを互いに異ならせると共に、前記休止期間において各補助容量線に与えるべき補助容量信号の電位を、当該休止期間の直前の走査期間において当該補助容量線に与えるべき当該補助容量信号の電位と異ならせる補助容量信号生成回路を備えることを特徴とする、液晶表示装置。     A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of video signal lines and the plurality of scanning signal lines A plurality of auxiliary capacitance lines arranged along a plurality of predetermined signal lines which are either the plurality of video signal lines or the plurality of scanning signal lines, and each pixel electrode and the plurality of auxiliary capacitance lines. A display unit including an auxiliary capacitor formed between the two,
    A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle. A scanning signal line driving circuit for driving the plurality of scanning signal lines, as shown in FIG.
    A video signal line drive that applies a video signal to the plurality of pixel electrodes via the plurality of video signal lines and sets the video signal to have a first polarity or a second polarity different from each other in the scanning period. Circuit,
    A storage capacitor signal to be applied to each storage capacitor line is generated, and a potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the first polarity video signal is applied. And the potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the video signal of the second polarity is applied and An auxiliary capacitance signal generation circuit is provided that makes the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period. Liquid crystal display device.
  2. 　前記休止期間は前記走査期間よりも長いことを特徴とする、請求項１に記載の液晶表示装置。 The liquid crystal display device according to claim 1, wherein the pause period is longer than the scanning period.
  3. 　前記所定の信号線は前記走査信号線であり、
    　前記補助容量は、各走査信号線に対応する画素電極と、当該走査信号線に沿う補助容量線との間に形成され、
    　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、所定数の前記走査信号線がそれぞれ選択状態になる当該所定数の選択期間毎に反転させることを特徴とする、請求項１に記載の液晶表示装置。     The predetermined signal line is the scanning signal line;
    The auxiliary capacitance is formed between a pixel electrode corresponding to each scanning signal line and an auxiliary capacitance line along the scanning signal line,
    In the scanning period, the video signal line driving circuit selects the predetermined number of the scanning signal lines to select the polarity of the plurality of video signals to be applied to the plurality of video signal lines, respectively. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is inverted every period.
  4. 　前記所定の信号線は前記映像信号線であり、
    　前記補助容量は、各映像信号線に対応する画素電極と、当該映像信号線に沿う補助容量線との間に形成され、
    　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、所定数の前記映像信号線毎に反転させることを特徴とする、請求項１に記載の液晶表示装置。     The predetermined signal line is the video signal line;
    The auxiliary capacitance is formed between a pixel electrode corresponding to each video signal line and an auxiliary capacitance line along the video signal line,
    The video signal line driving circuit reverses the polarity of the plurality of video signals to be given to the plurality of video signal lines for each of a predetermined number of the video signal lines in the scanning period. Item 2. A liquid crystal display device according to item 1.
  5. 　前記映像信号線駆動回路の配置位置側から数えて奇数番目の走査信号線に対応する画素電極と、当該画素電極に前記映像信号線の延伸する方向に並び、かつ、前記映像信号線駆動回路の配置位置側から数えて偶数番目の走査信号線に対応する画素電極とは、互いに隣接する映像信号線にそれぞれ対応することを特徴とする、請求項４に記載の液晶表示装置。 A pixel electrode corresponding to an odd-numbered scanning signal line counted from the arrangement position side of the video signal line driving circuit, arranged in the direction in which the video signal line extends to the pixel electrode, and of the video signal line driving circuit 5. The liquid crystal display device according to claim 4, wherein the pixel electrodes corresponding to the even-numbered scanning signal lines counted from the arrangement position side correspond to the video signal lines adjacent to each other.
  6. 　前記所定の信号線は前記走査信号線であり、
    　前記補助容量は、各走査信号線に対応する画素電極のうちの、前記走査信号線駆動回路の配置位置側から数えて奇数番目の映像信号線に対応する画素電極と、当該走査信号線に沿う補助容量線との間に形成されると共に、各走査信号線に対応する画素電極のうちの、前記走査信号線駆動回路の配置位置側から数えて偶数番目の映像信号線に対応する画素電極と、当該走査信号線の先行の走査信号線に沿う補助容量線との間に形成され、
    　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、各走査信号線が選択状態になる選択期間毎に反転させると共に、映像信号線毎に反転させることを特徴とする、請求項１に記載の液晶表示装置。     The predetermined signal line is the scanning signal line;
    The auxiliary capacitor includes a pixel electrode corresponding to an odd-numbered video signal line counted from an arrangement position side of the scanning signal line driving circuit among pixel electrodes corresponding to each scanning signal line, and along the scanning signal line. Among the pixel electrodes corresponding to each scanning signal line, the pixel electrodes corresponding to the even-numbered video signal lines counted from the arrangement position side of the scanning signal line driving circuit, , The auxiliary capacitance line along the scanning signal line preceding the scanning signal line,
    The video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is inverted for each signal line.
  7. 　前記所定の信号線は前記映像信号線であり、
    　前記補助容量は、各映像信号線に対応する画素電極のうちの、前記映像信号線駆動回路の配置位置側から数えて奇数番目の走査信号線に対応する画素電極と、当該映像信号線に沿う補助容量線との間に形成されると共に、各映像信号線に対応する画素電極のうちの、前記映像信号線駆動回路の配置位置側から数えて偶数番目の走査信号線に対応する画素電極と、当該映像信号線の先行の映像信号線に沿う補助容量線との間に形成され、
    　前記映像信号線駆動回路は、前記走査期間において、前記複数の映像信号線にそれぞれ与えるべき前記複数の映像信号の極性を、各走査信号線が選択状態になる選択期間毎に反転させると共に、映像信号線毎に反転させることを特徴とする、請求項１に記載の液晶表示装置。     The predetermined signal line is the video signal line;
    The auxiliary capacitor includes pixel electrodes corresponding to odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit among pixel electrodes corresponding to the video signal lines, and along the video signal lines. Among the pixel electrodes corresponding to each video signal line, the pixel electrodes corresponding to even-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit, , Formed between the auxiliary capacitance line along the preceding video signal line of the video signal line,
    The video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is inverted for each signal line.
  8. 　前記映像信号線駆動回路は、各走査信号線が選択状態になる選択期間での前記複数の映像信号の振幅を前記走査期間の開始時点から終了時点にかけて小さくすることを特徴とする、請求項１に記載の液晶表示装置。 The video signal line driving circuit reduces the amplitude of the plurality of video signals in a selection period in which each scanning signal line is in a selected state from the start time to the end time of the scanning period. A liquid crystal display device according to 1.
  9. 　各補助容量線は、透明電極として形成されていることを特徴とする、請求項１から８までのいずれか１項に記載の液晶表示装置。 The liquid crystal display device according to any one of claims 1 to 8, wherein each auxiliary capacitance line is formed as a transparent electrode.
  10. 　各補助容量線は、当該補助容量線の沿う前記所定の信号線と同一材料の電極として形成されていることを特徴とする、請求項１から４までのいずれか１項に記載の液晶表示装置。 5. The liquid crystal display device according to claim 1, wherein each auxiliary capacitance line is formed as an electrode made of the same material as that of the predetermined signal line along the auxiliary capacitance line. 6. .
  11. 　前記表示部は、各画素電極に対応する前記走査信号線がゲート端子に接続され、半導体層が酸化物半導体により形成された薄膜トランジスタをさらに含み、
    　前記映像信号線と当該映像信号線に対応する前記画素電極とは、当該画素電極に対応する前記走査信号線が前記ゲート端子に接続された前記薄膜トランジスタを介して接続されていることを特徴とする、請求項１から１０までのいずれか１項に記載の液晶表示装置。     The display unit further includes a thin film transistor in which the scanning signal line corresponding to each pixel electrode is connected to a gate terminal, and a semiconductor layer is formed of an oxide semiconductor,
    The video signal line and the pixel electrode corresponding to the video signal line are connected via the thin film transistor in which the scanning signal line corresponding to the pixel electrode is connected to the gate terminal. The liquid crystal display device according to any one of claims 1 to 10.
  12. 　複数の映像信号線、前記複数の映像信号線と交差する複数の走査信号線、前記複数の映像信号線および前記複数の走査信号線に対応してマトリクス状に配置された複数の画素電極、前記複数の映像信号線または前記複数の走査信号線のいずれかである複数の所定の信号線に沿って配置された複数の補助容量線、および各画素電極と前記複数の補助容量線のいずれかとの間に形成される補助容量を含む表示部と、前記複数の走査信号線を駆動するための走査信号線駆動回路と、前記複数の映像信号線を介して前記複数の画素電極に映像信号を与える映像信号線駆動回路と、各補助容量線に与えるべき補助容量信号を生成する補助容量信号生成回路とを備える表示装置の駆動方法であって、
    　前記複数の走査信号線が順次選択される走査期間と前記複数の走査信号線のいずれもが非選択状態になる休止期間とが、前記走査期間と前記休止期間とからなるフレーム期間を周期として交互に現れるように、前記複数の走査信号線を駆動するステップと、
    　前記走査期間において、前記映像信号の極性を互いに異なる第１極性または第２極性のいずれかにするステップと、
    　前記第１極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位と、前記第２極性の映像信号が与えられた画素電極との間に前記補助容量が形成された補助容量線に与えるべき当該補助容量信号の電位とを互いに異ならせると共に、前記休止期間において各補助容量線に与えるべき補助容量信号の電位を、当該休止期間の直前の走査期間において当該補助容量線に与えるべき当該補助容量信号の電位と異ならせるステップとを備えることを特徴とする、駆動方法。     A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of video signal lines and the plurality of scanning signal lines, A plurality of auxiliary capacitance lines arranged along a plurality of predetermined signal lines which are either a plurality of video signal lines or the plurality of scanning signal lines, and each pixel electrode and any of the plurality of auxiliary capacitance lines A display unit including an auxiliary capacitor formed therebetween, a scanning signal line driving circuit for driving the plurality of scanning signal lines, and a video signal to the plurality of pixel electrodes via the plurality of video signal lines A display device driving method comprising: a video signal line driving circuit; and an auxiliary capacitance signal generating circuit for generating an auxiliary capacitance signal to be given to each auxiliary capacitance line,
    A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle. Driving the plurality of scanning signal lines, as shown in FIG.
    In the scanning period, the video signal has a polarity that is either a first polarity or a second polarity different from each other;
    A potential of the auxiliary capacitance signal to be applied to the auxiliary capacitance line in which the auxiliary capacitance is formed between the pixel electrode to which the first polarity video signal is applied and a pixel to which the second polarity video signal is applied. The storage capacitor signal potential to be applied to the storage capacitor line in which the storage capacitor is formed between the electrodes is different from each other, and the storage capacitor signal potential to be applied to each storage capacitor line in the pause period is And a step of making the potential different from the potential of the auxiliary capacitance signal to be applied to the auxiliary capacitance line in the scanning period immediately before the pause period.
  13. 　前記休止期間は前記走査期間よりも長いことを特徴とする、請求項１２に記載の駆動方法。 The driving method according to claim 12, wherein the pause period is longer than the scanning period.
  14. 　各走査信号線が選択状態になる選択期間での前記複数の映像信号の振幅を前記走査期間の開始時点から終了時点にかけて小さくするステップをさらに備えることを特徴とする、請求項１２に記載の駆動方法。 The drive according to claim 12, further comprising a step of reducing the amplitude of the plurality of video signals in a selection period in which each scanning signal line is in a selected state from the start time to the end time of the scanning period. Method.
PCT/JP2012/070883 2011-08-26 2012-08-17 Liquid-crystal display device and method for driving same WO2013031552A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-184288 2011-08-26
JP2011184288 2011-08-26

Publications (1)

Publication Number Publication Date
WO2013031552A1 true WO2013031552A1 (en) 2013-03-07

Family

ID=47756046

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/070883 WO2013031552A1 (en) 2011-08-26 2012-08-17 Liquid-crystal display device and method for driving same

Country Status (1)

Country Link
WO (1) WO2013031552A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104464675A (en) * 2014-10-24 2015-03-25 友达光电股份有限公司 Power management method and power management device
WO2017170069A1 (en) * 2016-03-30 2017-10-05 シャープ株式会社 Liquid crystal display device
US11837149B2 (en) 2020-12-21 2023-12-05 Boe Technology Group Co., Ltd. Driving method for display panel, display panel and display apparatus

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09138421A (en) * 1995-11-13 1997-05-27 Sharp Corp Active matrix liquid crystal image display device
JP2002182619A (en) * 2000-10-05 2002-06-26 Sharp Corp Method for driving display device, and display device using the method
JP2003150127A (en) * 2001-11-15 2003-05-23 Sanyo Electric Co Ltd Method for driving active matrix type display device
JP2007140192A (en) * 2005-11-18 2007-06-07 Epson Imaging Devices Corp Active matrix type liquid crystal display device
JP2009042664A (en) * 2007-08-10 2009-02-26 Canon Inc Thin film transistor circuit, light emitting display device, and driving method therefor
JP2009244287A (en) * 2008-03-28 2009-10-22 Toshiba Mobile Display Co Ltd Liquid crystal display and method of driving liquid crystal display

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09138421A (en) * 1995-11-13 1997-05-27 Sharp Corp Active matrix liquid crystal image display device
JP2002182619A (en) * 2000-10-05 2002-06-26 Sharp Corp Method for driving display device, and display device using the method
JP2003150127A (en) * 2001-11-15 2003-05-23 Sanyo Electric Co Ltd Method for driving active matrix type display device
JP2007140192A (en) * 2005-11-18 2007-06-07 Epson Imaging Devices Corp Active matrix type liquid crystal display device
JP2009042664A (en) * 2007-08-10 2009-02-26 Canon Inc Thin film transistor circuit, light emitting display device, and driving method therefor
JP2009244287A (en) * 2008-03-28 2009-10-22 Toshiba Mobile Display Co Ltd Liquid crystal display and method of driving liquid crystal display

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104464675A (en) * 2014-10-24 2015-03-25 友达光电股份有限公司 Power management method and power management device
WO2017170069A1 (en) * 2016-03-30 2017-10-05 シャープ株式会社 Liquid crystal display device
US20190121208A1 (en) * 2016-03-30 2019-04-25 Sharp Kabushiki Kaisha Liquid crystal display device
US10754207B2 (en) 2016-03-30 2020-08-25 Sharp Kabushiki Kaisha Liquid crystal display device
US11837149B2 (en) 2020-12-21 2023-12-05 Boe Technology Group Co., Ltd. Driving method for display panel, display panel and display apparatus

Similar Documents

Publication Publication Date Title
US9978323B2 (en) Liquid crystal display panel and display device
US8400390B2 (en) Gate driving device and liquid crystal display having the same
KR101563265B1 (en) Display device and method for driving the same
JP4277894B2 (en) Electro-optical device, drive circuit, and electronic device
JP5955098B2 (en) Liquid crystal display device, data line driving circuit, and liquid crystal display device driving method
US20050253829A1 (en) Display device and display device driving method
JP5972267B2 (en) Liquid crystal display device and driving method of auxiliary capacitance line
JP5248717B1 (en) Display device and driving method thereof
TWI277944B (en) Liquid crystal display driving methodology with improved power consumption
JP4969043B2 (en) Active matrix display device and scanning side drive circuit thereof
JP2001282205A (en) Active matrix type liquid crystal display device and method for driving the same
US20090262059A1 (en) Timing controller, liquid crystal display, and method for driving the same
JP5805795B2 (en) Display device and driving method thereof
JP2006154545A (en) Liquid crystal display device
JP4597939B2 (en) Liquid crystal display device and driving method thereof
JP4241858B2 (en) Liquid crystal device and electronic device
KR20070039759A (en) Liquid crystal display
US9147372B2 (en) Display device
WO2013031552A1 (en) Liquid-crystal display device and method for driving same
WO2013179787A1 (en) Method for driving liquid crystal display device, liquid crystal display device, and mobile instrument provided with same
WO2013129239A1 (en) Drive device and display device
WO2013024776A1 (en) Display device and drive method for same
JP5328555B2 (en) Display device
WO2013069559A1 (en) Display device and drive method for same
JP2008233283A (en) Liquid crystal display device and driving method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12826942

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12826942

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP