JP2007219048A - Electrooptical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrooptical device which is reduced in power consumption in a partial display mode, and also to provide electronic equipment. <P>SOLUTION: The electrooptical device 1 includes: a first scanning line driving circuit 10 and a second scanning line driving circuit 60 which supply select voltages to scanning lines YA in a first display area A1 and scanning lines YB in a second display area A2 respectively; a first data line driving circuit 20 and a second data line driving circuit 70 which supply image signals to data lines XA in the first display area A1 and data lines XB in the second display area A2 respectively; and a converting circuit 80 which converts image signals in serial format into image signals in parallel format and outputs them. When a pixel 90 in the second display area A2 is rewritten, the image signal which is input from outside and corresponds to the second display area A2 is input in the serial format to the first scanning line driving circuit 10 and transferred in the serial format to the converting circuit 80, which converts the image signal into an image signal in the parallel format and supplies it to the second data line converting circuit 80. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  2. Description of the Related Art Conventionally, electro-optical devices such as liquid crystal display devices that display images are known. Such an electro-optical device has the following configuration, for example.

  The electro-optical device includes a liquid crystal panel and a liquid crystal driving circuit that drives the liquid crystal panel. The liquid crystal driving circuit includes a scanning line driving circuit and a data line driving circuit.

  The liquid crystal panel is provided between an element substrate on which a thin film transistor (hereinafter referred to as TFT) as a switching element (hereinafter referred to as TFT), which will be described later, is arranged in a matrix, a counter substrate disposed opposite to the element substrate, and the element substrate and the counter substrate. And a liquid crystal as an electro-optical material.

  The element substrate is provided with a plurality of scanning lines provided at predetermined intervals, a plurality of data lines provided substantially orthogonally to the scanning lines and at predetermined intervals, and substantially parallel and alternately with the plurality of scanning lines. A capacitor line.

The display area of the liquid crystal panel is composed of a plurality of pixels arranged in a matrix. Each pixel corresponds to an intersection between each scanning line and each data line, and includes a plurality of TFTs and a plurality of pixel electrodes electrically connected to the plurality of TFTs.
A scanning line is connected to the gate of the TFT, a data line is connected to the source of the TFT, and a pixel electrode and a storage capacitor are connected to the drain of the TFT.

  The counter substrate is provided with a plurality of common lines substantially parallel to the plurality of scanning lines. Further, common electrodes are formed on the counter substrate so as to face the pixel electrodes, and these common electrodes are connected to a common line.

  The above electro-optical device operates as follows. That is, all the pixels related to a certain scanning line are selected by supplying a selection voltage from the scanning line driving circuit to the scanning line in a line sequential manner. Then, in synchronization with the selection of these pixels, an image signal is supplied from the data line driving circuit to the data line. Thereby, an image signal is supplied from the data line to the selected pixel via the switching element, and the image data is written into the pixel electrode.

  When image data is written to the pixel electrode, a driving voltage is applied to the liquid crystal due to the potential difference between the voltages applied to the pixel electrode and the common electrode. Therefore, by changing the voltage level of the image signal, the orientation and order of the liquid crystal are changed, and gradation display is performed by light modulation of each pixel.

  By the way, the electro-optical device as described above is used in, for example, a portable device. In the portable device, in recent years, reduction of power consumption is required. Therefore, an electro-optical device in which a memory circuit is provided in a pixel has been proposed (see, for example, Patent Document 1).

In the electro-optical device of Patent Document 1, a memory circuit is provided in a pixel, and the memory circuit stores an image signal supplied to a data line when a scanning line is selected. As a result, it is not necessary to rewrite the image data in the pixels whose display contents are not changed, so that power consumption can be reduced.
Further, the electro-optical device of Patent Document 1 does not display on the entire screen of the display screen (hereinafter, this case is referred to as a full screen display mode), but displays only on a part of the display screen (hereinafter, this The case is referred to as a partial (partial) display mode) to further reduce power consumption.
Japanese Patent Application No. 2004-270193

  Incidentally, capacitive coupling occurs at the intersection of the scanning line and the data line. For this reason, even if the electro-optical device of Patent Document 1 writes image data only to some of the pixels of the display screen in the partial display mode, the non-display area causes non-coupling due to capacitive coupling at the intersection of the scanning lines and the data lines. Power is consumed in the display area. For this reason, there exists a subject that power consumption cannot fully be reduced.

  An object of the present invention is to provide an electro-optical device and an electronic apparatus that can reduce power consumption in a partial display mode.

  The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a display unit including a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, The display unit is divided into a first display area and a second display area, and the data lines in the first display area and the data lines in the second display area are insulated from each other. A first scanning line driving circuit for supplying a selection voltage for selecting in a predetermined order to the scanning lines in the first display area; and when the scanning lines in the first display area are selected. A first data line driving circuit for supplying an image signal to the data lines in one display region; and a second scanning line driving circuit for supplying a selection voltage for selecting the scanning lines in the second display region in a predetermined order. And when the scanning line of the second display area is selected, the second display A second data line driving circuit that supplies an image signal to a data line in the area, and a conversion circuit that converts the serial image signal into a parallel image signal and outputs the converted image signal. , The image signal corresponding to the second display area input from the outside is input to the first scanning line driving circuit in a serial format and transferred to the conversion circuit in a serial format. The serial image signal transferred from the first scanning line driving circuit is converted into a parallel image signal and supplied to the second data line driving circuit.

According to this invention, the display unit of the electro-optical device is configured by the first and second display areas. In addition, when the first scanning line driving circuit for supplying the electro-optical device with a selection voltage for selecting the scanning lines in the first display area in a predetermined order and the scanning lines in the first display area are selected. A first data line driving circuit for supplying an image signal to the data lines in the first display area, and a second scanning line drive for supplying a selection voltage for selecting in a predetermined order to the scanning lines in the second display area. A circuit and a second data line driving circuit for supplying an image signal to a data line in the second display area when a scanning line in the second display area is selected are provided.
Therefore, in the partial display mode, for example, image data can be written only to the pixels of the first display area, or image data can be written only to the pixels of the second display area. , Power consumption can be reduced.

Further, according to the present invention, the data lines in the first display area and the data lines in the second display area are insulated.
For this reason, in the partial display mode, for example, when image data is written only to the pixels in the first display area, it is not affected by capacitive coupling at the intersection of the scanning lines and data lines in the second display area. Further, when image data is written only to the pixels in the second display area, it is not affected by capacitive coupling at the intersection of the scanning lines and data lines in the first display area. Therefore, power consumption in the partial display mode can be further reduced.

In addition, according to the present invention, there is provided a conversion circuit for converting a serial image signal into a parallel image signal and outputting it. When rewriting the pixels in the second display area, the image signal corresponding to the second display area input from the outside is input to the first scanning line driving circuit in the serial format and transferred to the conversion circuit in the serial format. Next, the serial format image signal transferred from the first scanning line driving circuit was converted into a parallel format image signal by the conversion circuit, and supplied to the second data line driving circuit.
For this reason, the number of wirings for supplying an image signal corresponding to the second display area inputted from the outside to the conversion circuit via the first scanning line driving circuit can be reduced, and the electro-optical device can be downsized. .

  In the electro-optical device according to the aspect of the invention, the first and second display regions are formed by partitioning the display unit in parallel with one side of the display unit, and the first and second scanning line driving circuits are configured as described above. The first and second data line driving circuits are provided along one side intersecting with one side, and the first and second data line driving circuits are provided on two sides facing each other across the partition of the display unit among the four sides of the display unit. preferable.

According to this invention, the 1st and 2nd display area was formed by partitioning the said display part in parallel with one side of a display part. Further, the first and second scanning line driving circuits are provided along one side intersecting with the one side described above, and the first and second data line driving circuits are provided for partitioning the display unit among the four sides of the display unit. It was provided on two sides facing each other.
For this reason, by providing the first scanning line driving circuit and the first data line driving circuit on two adjacent sides of the first display area among the four sides of the display portion, the first scanning line driving circuit is provided. Wiring for supplying a selection voltage to the scanning lines in the first display area and wiring for supplying an image signal from the first data line driving circuit to the data lines in the first display area can be shortened. In addition, the second scanning line driving circuit and the second data line driving circuit are provided on two adjacent sides of the second display region among the four sides of the display portion, so that the second scanning line driving circuit is changed from the second scanning line driving circuit. The wiring for supplying the selection voltage to the scanning lines in the two display areas and the wiring for supplying the image signals from the second data line driving circuit to the data lines in the second display area can be shortened. Accordingly, since the area occupied by the wiring can be reduced, the electro-optical device can be further downsized.

  In the electro-optical device according to the aspect of the invention, the pixel includes a pixel electrode and a common electrode facing the pixel electrode, and the common electrode is insulated between the first display region and the second display region. Is preferred.

According to the present invention, the common electrode of the pixel is insulated between the first display area and the second display area.
That is, the common electrode in the first display region and the common electrode in the second display region were insulated. For this reason, when writing image data only to the pixels in the first display area, power consumption due to the load capacity of the common electrode in the second display area can be prevented. Further, when image data is written only to the pixels in the second display area, power consumption due to the load capacity of the common electrode in the first display area can be prevented. Therefore, power consumption in the partial display mode can be further reduced.

  In the electro-optical device according to the aspect of the invention, it is preferable that the pixels in the second display area include a memory circuit capable of storing an image signal supplied to the data line in synchronization with the selection of the scanning line.

According to the present invention, the memory circuit capable of storing the image signal supplied to the data line in synchronization with the selection of the scanning line is provided in the pixel of the second display region.
Therefore, by storing the image signal in the memory circuit, the image signal can be written to the pixel without supplying the image signal from the second data line driver circuit to the data line, so that power consumption can be further reduced. .

  In the electro-optical device according to the aspect of the invention, the first scanning line driving circuit includes a shift register having the number of stages equal to the number of scanning lines in the first display area, and the clock signal and the image signal are input thereto. It is preferable to sequentially shift and output the image signal in synchronization with the signal.

According to the present invention, the first scanning line driving circuit is provided with the shift register having the number of stages equal to the number of scanning lines in the first display area, and the clock signal and the image signal are input thereto. The first scanning line driving circuit sequentially shifts and outputs the image signal in synchronization with the clock signal.
For this reason, the image signal corresponding to the second display area inputted from the outside can be sequentially shifted in serial form and transferred to the conversion circuit by the first scanning line driving circuit.

  In the electro-optical device according to the aspect of the invention, it is preferable that supply of the selection voltage to the scanning lines in the first display area is stopped when the image signals are sequentially shifted in the first scanning line driving circuit.

According to the present invention, the supply of the selection voltage to the scanning lines in the first display area is stopped when the image signals are sequentially shifted in the first scanning line driving circuit.
Therefore, it is possible to prevent the first scanning line driving circuit from supplying the selection voltage to the scanning lines in the first display area based on the image signal corresponding to the second display area input from the outside. Therefore, in the partial display mode, when image data is written only to the pixels in the second display area, it is possible to prevent the image data from being written to the pixels in the first display area.

An electronic apparatus according to an aspect of the invention includes the above-described electro-optical device.
According to the present invention, there are effects similar to those described above.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of embodiments and modifications, the same constituent elements are denoted by the same reference numerals, and the description thereof is omitted or simplified.
<First Embodiment>
FIG. 1 is a block diagram showing a configuration of an electro-optical device 1 according to the first embodiment of the present invention.
The electro-optical device 1 includes a rectangular liquid crystal panel AA and a liquid crystal driving circuit 100 that drives the liquid crystal panel AA.

The liquid crystal panel AA includes an element substrate 200 in which thin film transistors (hereinafter referred to as TFTs) 41, 92, and 93 as switching elements, which will be described later, are arranged in a matrix, and a counter substrate 300 arranged to face the element substrate 200. And a liquid crystal as an electro-optical material provided between the element substrate 200 and the counter substrate 300.
In the liquid crystal panel AA, a first display area A1 and a second display area A2 are formed so as to partition the liquid crystal panel AA in parallel with one side extending in the horizontal direction (X direction) of the liquid crystal panel AA in FIG. . In the present embodiment, the first display area A1 is formed on the upper side in FIG. 1 of the liquid crystal panel AA, and the second display area A2 is formed on the lower side in FIG.

On the element substrate 200 in the first display area A1, scanning lines YA extending in the horizontal direction (X direction) in FIG. 1 and capacitance lines Z extending in the horizontal direction (X direction) in FIG. Are provided alternately. Further, a data line XA extending in the vertical direction (Y direction) in FIG. 1 is provided so as to intersect the scanning line YA and the capacitance line Z.
A common electrode 462 described later is provided on the counter substrate 300 in the first display area A1.
Pixels 40 are provided corresponding to the intersections between the data lines XA and the scanning lines YA.

On the element substrate 200 in the second display area A2, the scanning lines YB extending in the horizontal direction (X direction) in FIG. 1 and the first driving lines M and the second driving, which also extend in the horizontal direction (X direction) in FIG. A pair of wirings composed of lines N are alternately provided at predetermined intervals. Further, the first data line XB and the second data line XC extending in the vertical direction (Y direction) in FIG. 1 intersecting the scanning line YB, the first drive line M, and the second drive line N are spaced at predetermined intervals. Are provided alternately. The first data line XB and the second data line XC are insulated from the data line XA.
A common electrode 962 described later is provided on the counter substrate 300 in the second display region A2. The common electrode 962 is insulated from the common electrode 462 described above.
Pixels 90 are provided corresponding to the intersections between the first data lines XB and the scanning lines YB.

  The liquid crystal driving circuit 100 is formed on the element substrate 200 of the liquid crystal panel AA, and includes a first scanning line driving circuit 10, a first data line driving circuit 20, a control circuit 30, a second scanning line driving circuit 60, A second data line driving circuit 70 and a conversion circuit 80 are provided.

The first scanning line driving circuit 10 and the second scanning line driving circuit 60 are arranged on one side intersecting one side parallel to the side adjacent to the first display area A1 and the second display area A2 among the four sides of the liquid crystal panel AA. It is provided along. In the present embodiment, among the four sides of the liquid crystal panel AA, the first scanning line driving circuit 10 is provided on the right side in FIG. 1 and along the first display area A1, and on the right side in FIG. A second scanning line driving circuit 60 is provided along the display area A2.
The first scanning line driving circuit 10 supplies a selection voltage for selecting in a predetermined order to each scanning line YA in the first display area A1. Further, the first scanning line driving circuit 10 transfers various signals output from the control circuit 30 to the conversion circuit 80.
The second scanning line driving circuit 60 supplies a selection voltage for selecting in a predetermined order to each scanning line YB in the second display area A2.

The first data line driving circuit 20 and the second data line driving circuit 70 are provided on two sides facing each other across the partition of the liquid crystal panel AA among the four sides of the liquid crystal panel AA. In the present embodiment, the first data line drive circuit 20 is provided along one upper side in FIG. 1 among the four sides of the liquid crystal panel AA, and the second data line drive circuit 70 is provided along one lower side in FIG. Is provided.
The first data line driving circuit 20 supplies an image signal to each data line XA in the first display area A1 when the scanning line YA in the first display area A1 is selected.
When the scanning line YB in the second display area A2 is selected, the second data line driving circuit 70 supplies an image signal to each first data line XB in the second display area A2, and the polarity of this image signal. Is supplied to each second data line XC of the second display area A2.

The control circuit 30 is provided integrally with the first data line driving circuit 20.
The control circuit 30 controls the operation of the liquid crystal panel AA. Specifically, the control circuit 30 outputs various signals such as an image signal and a clock signal serving as a reference for operation timing to the first scanning line driving circuit 10 and the first data line driving circuit 20.

The conversion circuit 80 is provided adjacent to the second scanning line driving circuit 60 and the second data line driving circuit 70.
The conversion circuit 80 supplies various signals to the second scanning line driving circuit 60 and the second data line driving circuit 70 based on the signals output from the first scanning line driving circuit 10.
Details of the conversion circuit 80 will be described later.

FIG. 2 is a transistor level circuit diagram of the pixel 40 in the first display area A1.
The pixel 40 includes a TFT 41, a liquid crystal cell 46, and a storage capacitor 47.

The TFT 41 supplies the image signal from the data line XA to the liquid crystal cell 46 and the storage capacitor 47 in accordance with the selection voltage from the scanning line YA. The TFT 41 is an nMOS thin film transistor that is turned on / off in accordance with a control signal.
The TFT 41 has a gate connected to the scanning line YA, a source connected to the data line XA, and a drain connected to the liquid crystal cell 46 and the storage capacitor 47.

  The liquid crystal cell 46 includes a pixel electrode 461, the above-described common electrode 462 disposed to face the pixel electrode 461, and liquid crystal sandwiched between the pixel electrode 461 and the common electrode 462.

FIG. 3 is a transistor level circuit diagram of the pixel 90 in the second display area A2.
The pixel 90 includes a memory cell 91, a first TFT 92, a second TFT 93, a first transfer gate 94, a second transfer gate 95, and a liquid crystal cell 96.

  The memory cell 91 is configured by connecting two inverters 911 and 912 in a loop. That is, the input terminal of the inverter 911 is connected to the output terminal of the inverter 912, and the output terminal of the inverter 911 is connected to the input terminal of the inverter 912. Here, in the memory cell 91, an input terminal of the inverter 911, that is, an output terminal of the inverter 912 is a terminal P1, and an output terminal of the inverter 911, that is, an input terminal of the inverter 912 is a terminal P2.

The first TFT 92 supplies the image signal from the first data line XB to the terminal P1 of the memory cell 91 according to the selection voltage from the scanning line YB. The first TFT 92 is an nMOS thin film transistor that is turned on / off in accordance with a control signal.
The gate of the first TFT 92 is connected to the scanning line YB, the source is connected to the first data line XB, and the drain is connected to the terminal P 1 of the memory cell 91.

The second TFT 93 supplies the inverted image signal from the second data line XC to the terminal P2 of the memory cell 91 according to the selection voltage from the scanning line YB. The second TFT 93 is an nMOS thin film transistor that is turned on / off in accordance with a control signal.
The gate of the second TFT 93 is connected to the scanning line YB, the source is connected to the second data line XC, and the drain is connected to the terminal P 2 of the memory cell 91.

  The liquid crystal cell 96 includes a pixel electrode 961, the above-described common electrode 962 disposed to face the pixel electrode 961, and liquid crystal sandwiched between the pixel electrode 961 and the common electrode 962.

  The first transfer gate 94 has a CMOS (complementary) structure, and supplies a drive signal from the first drive line M to the pixel electrode 961 of the liquid crystal cell 96 in accordance with a control signal from the memory cell 91. The control terminal of the first transfer gate 94 is connected to the terminals P 1 and P 2 of the memory cell 91, the input terminal is connected to the first drive line M, and the output terminal is connected to the pixel electrode 961.

  The second transfer gate 95 has a CMOS (complementary) structure, and supplies an inverted drive signal from the second drive line N to the pixel electrode 961 of the liquid crystal cell 96 in accordance with a control signal from the memory cell 91. The control terminal of the second transfer gate 95 is connected to the terminals P 1 and P 2 of the memory cell 91, the input terminal is connected to the second drive line N, and the output terminal is connected to the pixel electrode 961.

FIG. 4 is a circuit diagram of the first scanning line driving circuit 10.
The first scanning line driving circuit 10 includes a shift register circuit 11, a level shifter circuit 12, and output control circuits 13 and 14.

The shift register circuit 11 includes a shift register 111 having the number of stages equal to the number of scanning lines YA, in this embodiment, 208 stages. The shift register circuit 11 is supplied with a clock signal CK serving as a reference for operation timing and a serial data signal DY output from the control circuit 30.
The shift register circuit 11 sequentially shifts the data signal DY in synchronization with the clock signal CK and sequentially outputs it as the transfer signal Q.

The level shifter circuit 12 includes 208 level shifters 121 respectively connected to the shift register 111 of the shift register circuit 11. The level shifter circuit 12 receives the transfer signal Q output from the shift register circuit 11.
The level shifter circuit 12 shifts the voltage level of the input transfer signal Q, converts it to a level suitable for turning on / off the TFT 41 of the pixel 40 in the first display area A1, and outputs it as a control signal.

The output control circuit 13 includes 208 enable buffers 131 respectively connected to the level shifters 121 of the level shifter circuit 12. The output control circuit 13 receives the enable signal ENB and the control signal output from the level shifter circuit 12.
The output control circuit 13 outputs the input control signal in response to the enable signal ENB. Specifically, if the enable signal ENB is at L level, the input control signal is output. If the enable signal ENB is at the H level, the input control signal is not output.

The output control circuit 14 includes one enable buffer 141. The output control circuit 14 receives the enable signal ENB and the transfer signal Q208 output from the shift register circuit 11.
The output control circuit 14 outputs the input transfer signal Q208 in response to the enable signal ENB. Specifically, if the enable signal ENB is at L level, the L level signal is output as a serial data signal SDY. If the enable signal ENB is at the H level, the input transfer signal Q208 is output as a serial data signal SDY.

The first scanning line driving circuit 10 described above operates as follows when performing partial display in the first display area A1.
That is, the shift register 111 sequentially shifts the data signal DY in synchronization with the clock signal CK and sequentially outputs it as the transfer signal Q. The transfer signal Q is shifted in voltage level by the level shifter circuit 12 and output as a control signal. This control signal is output to the scanning line YA by the output control circuit 13 to which the L level enable signal ENB is input.
The transfer signal Q208 is output as an L level data signal SDY by the output control circuit 14 to which the L level enable signal ENB is input.

FIG. 5 is a timing chart of the first scanning line driving circuit 10 when partial display is performed in the first display area A1.
First, at time t1, the shift register 111A takes in the data signal DY in synchronization with the rising edge of the clock signal CK, and outputs an H level transfer signal Q1. The H level transfer signal Q1 is shifted in voltage level by the level shifter 121A and output as an H level control signal. The H level control signal is output to the scanning line YA1 by the enable buffer 131A to which the L level enable signal ENB is input.

Next, at time t2, the shift register 111A captures the data signal DY in synchronization with the rising edge of the clock signal CK, and outputs an L level transfer signal Q1. The L-level transfer signal Q1 is shifted in voltage level by the level shifter 121A and output as an L-level control signal. The L level control signal is output to the scanning line YA1 by the enable buffer 131A to which the L level enable signal ENB is input.
Further, the shift register 111B takes in the transfer signal Q1 in synchronization with the rising edge of the clock signal CK, and outputs an H level transfer signal Q2. The H level transfer signal Q2 is shifted in voltage level by the level shifter 121B and output as an H level control signal. The H level control signal is output to the scanning line YA2 by the enable buffer 131B to which the L level enable signal ENB is input.

Next, at time t3, the shift register 111B takes in the transfer signal Q1 in synchronization with the rising edge of the clock signal CK and outputs the L-level transfer signal Q2. The L level transfer signal Q2 is shifted in voltage level by the level shifter 121B and output as an L level control signal. The L level control signal is output to the scanning line YA2 by the enable buffer 131B to which the L level enable signal ENB is input.
Further, the shift register 111C takes in the transfer signal Q2 in synchronization with the rising edge of the clock signal CK, and outputs an H level transfer signal Q3. The H level transfer signal Q3 is shifted in voltage level by the level shifter 121C and output as an H level control signal. The H level control signal is output to the scanning line YA3 by the enable buffer 131C to which the L level enable signal ENB is input.

As described above, the shift register circuit 11 sequentially shifts the data signal DY in synchronization with the rising edge of the clock signal CK and sequentially outputs it as the transfer signal Q.
At time t4, that is, at the 208th rise of the clock signal CK counted from time t1, the shift register circuit 11 outputs the H level transfer signal Q208, and the output control circuit 13 applies the H level control signal to the scanning line. Output to YA208. The H level transfer signal Q208 is output as the L level data signal SDY by the enable buffer 141 of the output control circuit 14 to which the L level enable signal ENB is input.

On the other hand, the first scanning line driving circuit 10 operates as follows when performing partial display in the second display area A2.
That is, the shift register 111 sequentially shifts the data signal DY in synchronization with the clock signal CK and sequentially outputs it as the transfer signal Q. The transfer signal Q is shifted in voltage level by the level shifter circuit 12 and output as a control signal. This control signal is not output to the scanning line YA by the output control circuit 13 to which the H level enable signal ENB is input.
The transfer signal Q208 is sequentially output as the data signal SDY by the output control circuit 14 to which the H level enable signal ENB is input.

FIG. 6 is a timing chart of the first scanning line driving circuit 10 when partial display is performed in the second display area A2.
First, at time t11, the shift register 111A takes in the data signal DY in synchronization with the rising edge of the clock signal CK, and outputs an H level transfer signal Q1. The H level transfer signal Q1 is shifted in voltage level by the level shifter 121A and output as an H level control signal. This H level control signal is not output to the scanning line YA1 by the enable buffer 131A to which the H level enable signal ENB is input.

Next, at time t12, the shift register 111A captures the data signal DY in synchronization with the rising edge of the clock signal CK, and outputs the L level transfer signal Q1. The L-level transfer signal Q1 is shifted in voltage level by the level shifter 121A and output as an L-level control signal. This L level control signal is not output to the scanning line YA1 by the enable buffer 131A to which the H level enable signal ENB is input.
Further, the shift register 111B takes in the transfer signal Q1 in synchronization with the rising edge of the clock signal CK, and outputs an H level transfer signal Q2. The H level transfer signal Q2 is shifted in voltage level by the level shifter 121B and output as an H level control signal. This H level control signal is not output to the scanning line YA2 by the enable buffer 131B to which the H level enable signal ENB is input.

Next, at time t13, the shift register 111B takes in the transfer signal Q1 in synchronization with the rising edge of the clock signal CK and outputs the L-level transfer signal Q2. The L level transfer signal Q2 is shifted in voltage level by the level shifter 121B and output as an L level control signal. This L level control signal is not output to the scanning line YA2 by the enable buffer 131B to which the H level enable signal ENB is input.
Further, the shift register 111C takes in the transfer signal Q2 in synchronization with the rising edge of the clock signal CK, and outputs an H level transfer signal Q3. The H level transfer signal Q3 is shifted in voltage level by the level shifter 121C and output as an H level control signal. This H level control signal is not output to the scanning line YA3 by the enable buffer 131C to which the H level enable signal ENB is input.

As described above, the shift register circuit 11 sequentially shifts the data signal DY in synchronization with the rising edge of the clock signal CK and sequentially outputs it as the transfer signal Q.
At time t14, that is, at the 208th rise of the clock signal CK counted from time t11, the shift register circuit 11 outputs the H level transfer signal Q208, and the output control circuit 13 applies the L level control signal to the scanning line. Output to YA208. The H level transfer signal Q208 is output as an H level data signal SDY by the enable buffer 141 of the output control circuit 14 to which the H level enable signal ENB is input. The H level data signal SDY becomes L level in synchronization with the next rising edge of the clock signal CK.

FIG. 7 is a block diagram showing a configuration of the conversion circuit 80.
The conversion circuit 80 includes a timing controller circuit 81, a serial / parallel conversion circuit 82, and an address counter circuit 83.

  The timing controller circuit 81 includes an octal counter. The timing controller circuit 81 receives a reset signal RES, a clock signal CK, and a serial data signal SDY output from the first scanning line driving circuit 10.

Here, in the case where partial display is performed in the second display area A2, a pulse that becomes H level over the period of one cycle of the clock signal CK is added to the control circuit 30 at the beginning of the serial image signal. Input from the outside.
When the H level data signal SDY is input over the period of one cycle of the clock signal CK, the timing controller circuit 81 starts counting up with an octal counter and counts one by one in synchronization with the clock signal CK. Up. Each time the octal counter is set to “7”, the write enable signal XWE is set to L level, and each time the octal counter is set to “0”, the conversion reference signal SR_LT is output to H level. Further, in synchronization with the clock signal CK, the address reference signal AD_CK is output as the H level in the next cycle when the conversion reference signal SR_LT becomes the H level.
When the L level reset signal RES is input, the timing controller circuit 81 resets the octal counter to “0”.

The serial / parallel conversion circuit 82 includes an 8-stage shift register, converts an input serial format signal into a parallel format signal, and outputs the parallel format signal. The serial / parallel conversion circuit 82 includes a reset signal RES, a clock signal CK, a serial data signal SDY output from the first scanning line driving circuit 10, and a write enable signal XWE output from the timing controller circuit 81. And a conversion reference signal SR_LT.
The serial / parallel conversion circuit 82 sequentially shifts the data signal SDY by an 8-stage shift register in synchronization with the clock signal CK and holds the data as shift data SQ1 to SQ8. Then, every time the write enable signal XWE is at the L level and the conversion reference signal SR_LT is at the H level, the shift data SQ1 to SQ8 held in the eight-stage shift register are combined into the 8-bit wide image signals D0 to D7. Output.
When the L level reset signal RES is input, the serial-parallel conversion circuit 82 resets the 8-stage shift register to “0”.

The address counter circuit 83 includes a 4096-digit counter. The address counter circuit 83 receives the reset signal RES and the address reference signal AD_CK output from the timing controller circuit 81.
The address counter circuit 83 increments the 4096-digit counter by 1 in synchronization with the address reference signal AD_CK, and outputs the count value as the 12-bit address signals A0 to A11.
When the L level reset signal RES is input, the address counter circuit 83 resets the 4096-digit counter to “0”.

The above conversion circuit 80 operates as follows.
That is, first, when the H level data signal SDY is input over the period of one cycle of the clock signal CK, the timing controller circuit 81 starts counting up with an octal counter.

The serial-parallel conversion circuit 82 outputs the input serial-format data signal SDY as 8-bit parallel-format image signals D0 to D7 each time the octal counter counts “0”.
Further, the address counter circuit 83 outputs the image signals D0 to D7 from the serial / parallel conversion circuit 82, then counts up with a 4096-digit counter, and outputs them as address signals A0 to A11.

FIG. 8 is a timing chart of the conversion circuit 80.
First, during the period from time t21 to t22, the reset signal RES is set to L level, and the octal counter of the timing controller circuit 81 is reset to “0”.

Next, at time t23, data D7 (R1) is input as serial format data signal SDY.
Next, at time t24, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D7 (R1) is held as the shift data SQ1. Also, the octal counter is counted up and set to “1”.

Next, at time t25, data D6 (G1) is input as the serial-format data signal SDY.
Next, at time t26, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D6 (G1) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D7 (R1) is held as the shift data SQ2. Also, the octal counter is counted up and set to “2”.

Next, at time t27, the data D5 (B1) is input as the data signal SDY in the serial format.
Next, at time t28, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D5 (B1) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D6 (G1) is held as the shift data SQ2. Further, the shift data SQ2 is taken in and the data D7 (R1) is held as the shift data SQ3. Also, the octal counter is counted up and set to “3”.

Next, at time t29, data D4 (R2) is input as serial format data signal SDY.
Next, at time t30, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D4 (R2) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D5 (B1) is held as the shift data SQ2. Further, the shift data SQ2 is taken in and the data D6 (G1) is held as the shift data SQ3. Further, the shift data SQ3 is taken in and the data D7 (R1) is held as the shift data SQ4. Also, the octal counter is counted up and set to “4”.

Next, at time t31, data D3 (G2) is input as the serial-format data signal SDY.
Next, at time t32, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D3 (G2) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D4 (R2) is held as the shift data SQ2. Further, the shift data SQ2 is taken in and the data D5 (B1) is held as the shift data SQ3. Further, the shift data SQ3 is taken in and the data D6 (G1) is held as the shift data SQ4. Further, the shift data SQ4 is taken in and D7 (R1) is held as the shift data SQ5. Also, the octal counter is counted up and set to “5”.

Next, at time t33, the data D2 (B2) is input as the data signal SDY in the serial format.
Next, at time t34, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D2 (B2) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D3 (G2) is held as the shift data SQ2. Further, the shift data SQ2 is taken in and the data D4 (R2) is held as the shift data SQ3. Further, the shift data SQ3 is taken in and the data D5 (B1) is held as the shift data SQ4. Further, the shift data SQ4 is taken in and D6 (G1) is held as the shift data SQ5. Further, the shift data SQ5 is taken in and D7 (R1) is held as the shift data SQ6. Also, the octal counter is counted up and set to “6”.

Next, at time t35, the data D1 (R3) is input as the data signal SDY in the serial format.
Next, at time t36, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D1 (R3) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D2 (B2) is held as the shift data SQ2. Further, the shift data SQ2 is taken in and the data D3 (G2) is held as the shift data SQ3. Further, the shift data SQ3 is taken in and the data D4 (R2) is held as the shift data SQ4. Further, the shift data SQ4 is taken in and D5 (B1) is held as the shift data SQ5. Further, the shift data SQ5 is taken in and D6 (G1) is held as the shift data SQ6. Further, the shift data SQ6 is fetched and D7 (R1) is held as the shift data SQ7. Also, the octal counter is counted up and set to “7”.

Next, at time t37, the data D0 (G3) is input as the data signal SDY in the serial format. Further, based on the fact that the octal counter is set to “7”, the write permission signal XWE is set to the L level in synchronization with the fall of the clock signal CK.
Next, at time t38, the data signal SDY is taken in synchronization with the rising edge of the clock signal CK, and the data D0 (G3) is held as the shift data SQ1. Further, the shift data SQ1 is taken in and the data D1 (R3) is held as the shift data SQ2. Further, the shift data SQ2 is taken in and the data D2 (B2) is held as the shift data SQ3. Further, the shift data SQ3 is taken in and the data D3 (G2) is held as the shift data SQ4. Further, the shift data SQ4 is fetched and D4 (R2) is held as the shift data SQ5. Further, the shift data SQ5 is taken in and D5 (B1) is held as the shift data SQ6. Further, the shift data SQ6 is taken in and D6 (G1) is held as the shift data SQ7. Further, the shift data SQ7 is taken in and D7 (R1) is held as the shift data SQ8. Also, the octal counter is counted up and set to “0”. Further, based on the fact that the octal counter is set to “0”, the conversion reference signal SR_LT is set to the H level in synchronization with the rising edge of the clock signal CK. Further, based on the fact that the write permission signal XWE is at the L level and the conversion reference signal SR_LT is at the H level, the shift data SQ1 to SQ8 held in the eight-stage shift register are put together to form the 8-bit wide image signals D0 to D0. Image data DATA (R1, G1, B1, R2, G2, B2, R3, G3) is output as D7.

Next, at time t39, the write permission signal XWE is set to the H level.
Next, at time t40, the conversion reference signal SR_LT is set to the L level. Further, the address reference signal AD_CK is set to the H level. Further, in synchronization with the rising edge of the address reference signal AD_CK, the 4096-digit counter is counted up to output “1” as the address signals A0 to A11.
Next, at time t41, the address reference signal AD_CK is set to the L level.

In the present embodiment, the second display area A2 includes 120 data lines, that is, the first data lines XB1 to XB120 and the second data lines XC1 to XC120. Therefore, 7 bits from address signals A0 to A6 that can represent 128 numbers from 0 to 127 in decimal are output to the second data line drive circuit 70, and decimal 0 that can be represented by address signals A0 to A6. Among 121 to 127, 121 to 127 are invalidated. Accordingly, one first data line XB among the first data lines XB1 to XB120 in the second display area A2 can be selected, and a pair with the first data line XB selected from the second data lines XC1 to XC120 can be selected. One second data line XC is selected.
In the present embodiment, there are 32 scanning lines YB of the scanning lines YB1 to YB32 in the second display area A2. For this reason, 5 bits of the address signals A7 to A11 that can express 32 types of numbers from 0 to 31 in decimal notation are output to the second scanning line driving circuit 60. Accordingly, one scanning line YB is selected from the scanning lines YB1 to YB32 of the second display area A2.

The above electro-optical device 1 operates as follows when rewriting the image data of the pixel 40 in the first display area A1.
That is, first, the shift register circuit 11 of the first scanning line driving circuit 10 receives a clock signal CK and a 1-bit width data signal that becomes H level at the start of one vertical scanning period (1F) output from the control circuit 30. DY. Then, the shift register circuit 11 sequentially shifts the data signal DY in synchronization with the clock signal CK, and sequentially outputs it as the transfer signal Q that becomes H level over the period of one cycle of the clock signal CK.
Next, the voltage level of the transfer signal Q output from the shift register circuit 11 is converted by the level shifter circuit 12 and output to the output control circuit 13 as a control signal.

Next, an L level enable signal ENB is input to the first scanning line driving circuit 10. Then, the output control circuit 14 of the first scanning line driving circuit 10 outputs the L-level serial data signal SDY to the conversion circuit 80. Then, since the timing controller circuit 81 of the conversion circuit 80 does not start counting up with an octal counter, the serial / parallel conversion circuit 82 and the address counter circuit 83 of the conversion circuit 80 do not operate. Therefore, since the second scanning line driving circuit 60 and the second data line driving circuit 70 do not operate, the image data of the pixels 90 in the second display area A2 cannot be rewritten.
On the other hand, the output control circuit 13 of the first scanning line driving circuit 10 outputs the control signal output from the level shifter circuit 12 to the scanning line YA. Then, by supplying a selection voltage as a control signal from the first scanning line driving circuit 10 to the scanning line YA in a line sequential manner, all the pixels 40 associated with each scanning line YA are sequentially selected. Then, the TFT 41 related to the selected pixel 40 is turned on.

  Next, in synchronization with the selection of the pixels 40, the image signal output from the control circuit 30 is supplied from the first data line driving circuit 20 to the data line XA. Then, a voltage corresponding to the image signal is applied to the pixel electrode 461 of the selected pixel 40.

  Then, in the pixel 40 in the first display area A1, a potential difference is generated between the pixel electrode 461 and the common electrode 462, and a driving voltage is applied to the liquid crystal. As a result, the alignment and order of the liquid crystal change and gradation display is performed. Note that the driving voltage applied to the liquid crystal is held by the storage capacitor 47 for a period that is three digits longer than the period during which the image signal is written.

The above electro-optical device 1 operates as follows when rewriting the image data of the pixel 90 in the second display area A2.
That is, first, the control circuit 30 outputs an image signal input from the outside to the first scanning line driving circuit 10 as a serial data signal DY. The serial image signal and the clock signal CK are input to the shift register circuit 11 of the first scanning line driving circuit 10. Then, the shift register circuit 11 sequentially shifts the image signal in synchronization with the clock signal CK and sequentially outputs it as the transfer signal Q.
Next, the voltage level of the transfer signal Q output from the shift register circuit 11 is converted by the level shifter circuit 12 and output to the output control circuit 13 as a control signal.

Next, the H level enable signal ENB is input to the first scanning line driving circuit 10. Then, the output control circuit 13 of the first scanning line driving circuit 10 does not output the control signal output from the level shifter circuit 12 to the scanning line YA. As a result, the first scanning line driving circuit 10 does not supply the selection voltage as a control signal to the scanning line YA in the first display area A1, so that the image data of the pixels 40 in the first display area A1 is not rewritten.
On the other hand, the output control circuit 14 of the first scanning line driving circuit 10 outputs the transfer signal Q output from the shift register circuit 11 to the conversion circuit 80 as the data signal SDY. That is, the first scanning line driving circuit 10 transfers the serial image signal output from the control circuit 30 to the conversion circuit 80.

Next, the serial / parallel conversion circuit 82 of the conversion circuit 80 converts the serial-format image signal into an 8-bit parallel-format image signal and outputs it to the second data line driving circuit 70.
Further, the address counter circuit 83 of the conversion circuit 80 selects the scanning line YB, the first data line XB, and the second data line XC, which are related to the image data rewriting of the pixels 90 in the second display area A2, respectively. Address signals A7 to A11 and address signals A0 to A6 to be supplied are supplied to the second scanning line driving circuit 60 and the second data line driving circuit 70.

  Next, by supplying a selection voltage from the second scanning line driving circuit 60 to the scanning line YB selected based on the address signals A7 to A11, all the pixels 90 related to the selected scanning line YB are selected. Then, the TFTs 92 and 93 related to the selected pixel 90 are turned on.

Next, in synchronization with the selection of the pixels 90, the image data and the inverted image signal from the second data line driving circuit 70 are transferred to the first data line XB and the second data line XC selected based on the address signals A0 to A6. Supply. Then, the image signal and the inverted image signal are written into the memory cell 91 of the selected pixel 90 and supplied to the control terminals of the transfer gates 94 and 95.
As a result, the first transfer gate 94 or the second transfer gate 95 is selectively turned on, and the drive signal from the first drive line M or the inverted drive signal from the second drive line N is written to the pixel electrode 961.

When an image signal or an inverted image signal is written to the pixel electrode 961, a driving voltage is applied to the liquid crystal due to a potential difference between the pixel electrode 961 and the common electrode 962. As a result, the alignment and order of the liquid crystal are changed, and display by light modulation of the pixels 90 is performed.
Note that the image signal and the inverted image signal are held by the memory cell 91, and thus the drive voltage applied to the liquid crystal is also held until the next frame is written.

According to this embodiment, there are the following effects.
(1) The liquid crystal panel AA is composed of a first display area A1 and a second display area A2. Further, when the first scanning line driving circuit 10 for supplying a selection voltage for selecting in a predetermined order to the scanning lines YA in the first display area A1 and the scanning lines YA in the first display area A1 are selected. A first data line driving circuit 20 that supplies an image signal to the data line XA in the first display area A1, and a second scan that supplies a selection voltage to be selected in a predetermined order for the scanning lines YB in the second display area A2. When the line driving circuit 60 and the scanning line YB in the second display area A2 are selected, the image data and the inverted image signal are supplied to the first data line XB and the second data line XC in the second display area A2. 2 data line driving circuit 70.
For this reason, in the partial display mode, for example, image data can be written only to the pixels 40 of the first display area A1, or image data can be written only to the pixels 90 of the second display area A2. By controlling, power consumption can be reduced.

(2) The data line XA in the first display area A1 is insulated from the first data line XB and the second data line XC in the second display area A2.
Therefore, in the partial display mode, for example, when writing image data only to the pixels 40 in the first display area A1, the scanning lines YB, the first data lines XB and the second data lines XC in the second display area A2, It is not affected by capacitive coupling at the intersection. Further, when image data is written only to the pixels 90 in the second display area A2, there is no influence of capacitive coupling at the intersection of the scanning line YA and the data line XA in the first display area A1. Therefore, power consumption in the partial display mode can be further reduced.

(3) A conversion circuit 80 is provided for converting a serial image signal into a parallel image signal and outputting it. When the pixel 90 in the second display area A2 is rewritten, an image signal corresponding to the second display area A2 input from the outside is input to the first scanning line driving circuit 10 in a serial format and the conversion circuit 80 in a serial format. Transferred to. Next, the serial circuit image signal transferred from the first scanning line driving circuit 10 is converted into a parallel image signal by the conversion circuit 80 and supplied to the second data line driving circuit 70.
Therefore, the number of wirings for supplying an image signal corresponding to the second display area A2 input from the outside to the conversion circuit 80 via the first scanning line driving circuit 10 can be reduced, and the electro-optical device 1 can be reduced. Can be downsized.

(4) The first display area A1 and the second display area A2 were formed by partitioning the liquid crystal panel AA in parallel with one side of the liquid crystal panel AA. Further, the first scanning line driving circuit 10 and the second scanning line driving circuit 60 are provided along one side intersecting with the above-mentioned one side, and the first data line driving circuit 20 and the second data line driving circuit 70 are provided on the liquid crystal panel. Of the four sides in AA, the two sides facing each other across the partition of the liquid crystal panel AA were provided.
That is, the first scanning line driving circuit 10 and the first data line driving circuit 20 are provided on two adjacent sides of the first display area A1 among the four sides of the liquid crystal panel AA. For this reason, an image is supplied from the first scanning line driving circuit 10 to the scanning line YA in the first display area A1, and from the first data line driving circuit 20 to the data line XA in the first display area A1. Wiring for supplying signals can be shortened.
In addition, the second scanning line driving circuit 60 and the second data line driving circuit 70 are provided on two adjacent sides of the second display area A2 among the four sides of the liquid crystal panel AA. Therefore, a wiring for supplying a selection voltage from the second scanning line driving circuit 60 to the scanning line YB in the second display region A2, and a first data line XB in the second display region A2 from the second data line driving circuit 70. In addition, the wiring for supplying the image signal and the inverted image signal to the second data line XC can be shortened. Therefore, since the area occupied by the wiring can be reduced, the electro-optical device 1 can be further downsized.

(5) The common electrode 462 in the first display area A1 is insulated from the common electrode 962 in the second display area A2.
Therefore, when image data is written only to the pixels 40 in the first display area A1, power consumption due to the load capacity of the common electrode 962 in the second display area A2 can be prevented. Further, when writing image data only to the pixels 90 in the second display area A2, it is possible to prevent power consumption due to the load capacity of the common electrode 462 in the first display area A1. Therefore, power consumption in the partial display mode can be further reduced.

(6) A memory cell 91 capable of storing the image signal and the inverted image signal supplied to the first data line XB and the second data line XC in synchronization with the selection of the scanning line YB in the pixel 90 of the second display area A2. Was established.
Therefore, by storing the image signal in the memory cell 91, the image signal and the inverted image signal are not supplied from the second data line driving circuit 70 to the first data line XB and the second data line XC, and the pixel 90 is supplied. Since an image signal can be written, power consumption can be further reduced.

(7) A 208-stage shift register 111 equal to the number of scanning lines YA in the first display area A1 is provided in the first scanning line driving circuit 10, and a clock signal CK and a data signal DY as an image signal are input. The first scanning line driving circuit 10 sequentially shifts and outputs the data signal DY as an image signal in synchronization with the clock signal CK.
For this reason, the first scanning line driving circuit 10 can sequentially transfer the data signal DY as an image signal corresponding to the second display area A2 input from the outside in a serial format to the conversion circuit 80.

(8) When the first scanning line driving circuit 10 sequentially shifts the data signal DY as the image signal, the supply of the selection voltage to the scanning line YA in the first display area A1 is stopped.
Therefore, it is possible to prevent the first scanning line driving circuit 10 from supplying the selection voltage to the scanning line YA in the first display area A1 based on the image signal corresponding to the second display area A2 input from the outside. Therefore, in the partial display mode, when image data is written only to the pixels 90 in the second display area A2, it is possible to prevent the image data from being written to the pixels 40 in the first display area A1.

Second Embodiment
FIG. 9 is a block diagram showing a configuration of an electro-optical device 1A according to the second embodiment of the present invention. The electro-optical device 1A does not pass through the first scanning line driving circuit 10 when the signal output from the control circuit 30 is supplied to the second scanning line driving circuit 60 and the second data line driving circuit 70 in FIG. Different from the electro-optical device 1.

  Wirings for transmitting signals such as serial image signals and clock signals output from the control circuit 30 to the conversion circuit 80 are the first scanning line driving circuit 10 and the second scanning line driving circuit among the four sides of the liquid crystal panel AA. It is provided along one side facing one side provided with 60. In the present embodiment, the above-described wiring is provided on the left side of the liquid crystal panel AA in FIG.

According to this embodiment, there are the following effects.
(9) An image signal corresponding to the second display area A2 input from the outside passes through the conversion circuit 80 from the control circuit 30 without passing through the first scanning line driving circuit 10, and is supplied to the second data line driving circuit. 70.
Therefore, the first data line XB and the second data in the second display area A2 are supplied by the second data line driving circuit 70 while the selection voltage is supplied to the scanning lines YA in the first display area A1 by the first scanning line driving circuit 10. An image signal and an inverted image signal can be supplied to the data line XC. Therefore, by supplying the selection voltage to the scanning line YB by the second scanning line driving circuit 60 while supplying the image signal to the data line XA by the first data line driving circuit 20, the pixels 40 in the first display area A1 and Image data can be simultaneously written in the pixels 90 of the second display area A2.

<Modification>
It should be noted that the present invention is not limited to the above-described embodiment, and modifications, improvements, etc. within a scope that can achieve the object of the present invention are included in the present invention.
For example, in each of the above-described embodiments, the first display area A1 and the second display area A2 are formed on the liquid crystal panel AA. However, the present invention is not limited to this, and for example, a third display configured by pixels further including memory cells. Region A3 may be provided.
Further, for example, in each of the above-described embodiments, the pixel electrodes 461 and 961 are provided on the element substrate 200, and the common electrodes 462 and 962 are provided on the counter substrate 300 disposed to face the element substrate 200. However, the present invention is not limited thereto. Alternatively, the pixel electrodes 461 and 961 and the common electrodes 462 and 962 may be provided over the same substrate.

  Further, for example, in each of the above-described embodiments, the present invention is applied to the electro-optical device 1 using liquid crystal. However, the present invention is not limited to this, and can also be applied to an electro-optical device using an electro-optical material other than liquid crystal. An electro-optical material is a material whose optical characteristics such as transmittance and luminance change when an electric signal (current signal or voltage signal) is supplied. For example, a display panel using an OLED element such as an organic EL (Electro-Luminescent) or a light emitting polymer as an electro-optical material, or a microcapsule containing a colored liquid and white particles dispersed in the liquid is used as the electro-optical material. As an electrophoretic display panel, a twist ball display panel using a twist ball painted differently for each region of different polarity as an electro-optical material, a toner display panel using black toner as an electro-optical material, or The present invention can also be applied to various electro-optical devices such as a plasma display panel using a high-pressure gas such as helium or neon as an electro-optical material.

<Application example>
Next, an electronic apparatus to which the electro-optical device 1 according to the above-described embodiment is applied will be described.
FIG. 10 is a perspective view illustrating a configuration of a mobile phone to which the electro-optical device 1 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 1. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled.

  Note that electronic devices to which the electro-optical device 1 is applied include those shown in FIG. 10, personal computers, portable information terminals, digital still cameras, liquid crystal televisions, viewfinder type, monitor direct view type video tape recorders, car navigation systems. Examples of the apparatus include a device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a video phone, a POS terminal, and a touch panel. The electro-optical device described above can be applied as a display unit of these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. FIG. 3 is a circuit diagram of a transistor level of a first pixel related to a first display area of the electro-optical device. FIG. 4 is a circuit diagram of a transistor level of a second pixel related to a second display area of the electro-optical device. FIG. 3 is a circuit diagram of a first scanning line driving circuit of the electro-optical device. 6 is a timing chart of a first scanning line driving circuit of the electro-optical device when partial display is performed in a first display region. 6 is a timing chart of a first scanning line driving circuit of the electro-optical device when partial display is performed in a second display region. FIG. 3 is a block diagram illustrating a configuration of a conversion circuit of the electro-optical device. 10 is a timing chart of the conversion circuit of the electro-optical device when partial display is performed in a second display region. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. It is a perspective view which shows the structure of the mobile telephone to which the said electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 1A ... Electro-optical apparatus, 10 ... 1st scanning line drive circuit, 20 ... 1st data line drive circuit, 30 ... Control circuit, 40, 90 ... Pixel, 60 ... 2nd scanning line drive circuit, 70 ... 2nd Data line drive circuit, 80 ... Conversion circuit, 91 ... Memory cell (memory circuit), 100 ... Liquid crystal drive circuit, AA ... Liquid crystal panel (display unit), A1 ... First display area, A2 ... Second display area, XA ... Data line, XB ... first data line, XC ... second data line, YA, YB ... scanning line.

Claims (7)

An electro-optical device comprising: a plurality of scanning lines; a plurality of data lines; and a display unit including a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. And
The display unit is divided into a first display area and a second display area, and the data lines of the first display area and the data lines of the second display area are insulated,
A first scanning line driving circuit for supplying a selection voltage for selecting in a predetermined order to the scanning lines of the first display region;
A first data line driving circuit for supplying an image signal to a data line in the first display area when a scanning line in the first display area is selected;
A second scanning line driving circuit for supplying a selection voltage to be selected in a predetermined order for the scanning lines of the second display region;
A second data line driving circuit for supplying an image signal to a data line in the second display area when a scanning line in the second display area is selected;
A conversion circuit that converts a serial image signal into a parallel image signal and outputs the converted image signal,
When rewriting the pixels in the second display region, an image signal corresponding to the second display region input from the outside is input to the first scanning line driving circuit in a serial format and is also input to the conversion circuit in a serial format. Transferred,
The conversion circuit converts the serial image signal transferred from the first scanning line driving circuit into a parallel image signal, and supplies the converted image signal to the second data line driving circuit. Optical device. The electro-optical device according to claim 1,
The first and second display areas are formed by partitioning the display unit in parallel with one side of the display unit,
The first and second scanning line driving circuits are provided along one side that intersects the one side,
The electro-optical device, wherein the first and second data line driving circuits are provided on two sides facing each other across a partition of the display unit among the four sides of the display unit. The electro-optical device according to claim 1, wherein
The pixel includes a pixel electrode and a common electrode facing the pixel electrode,
The electro-optical device, wherein the common electrode is insulated between the first display area and the second display area. The electro-optical device according to any one of claims 1 to 3,
The electro-optical device, wherein the pixels in the second display area include a memory circuit capable of storing an image signal supplied to the data line in synchronization with the selection of the scanning line. The electro-optical device according to claim 1,
The first scanning line driving circuit includes a shift register having a number of stages equal to the number of scanning lines in the first display area, and receives a clock signal and the image signal, and the image signal is synchronized with the clock signal. Are sequentially shifted and output. The electro-optical device according to claim 5,
An electro-optical device that stops supply of the selection voltage to the scanning lines in the first display area when the image signals are sequentially shifted in the first scanning line driving circuit.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images